OV - exec - Function .omp_outlined..2#0x461580

	Function: .omp_outlined..2#0x461580	Module: exec	Source: par_strength.c:246-513 [...]	Coverage: 3.8%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 246 - 513

--------------------------------------------------------------------------------

246: #pragma omp parallel private(i,diag,row_scale,row_sum,jA,jS)

247: #endif

248:    {

249:    HYPRE_Int start, stop;

250:    hypre_GetSimpleThreadPartition(&start, &stop, num_variables);

251:    HYPRE_Int jS_diag = 0, jS_offd = 0;

252:

253:    for (i = start; i < stop; i++)

254:    {

255:       S_diag_i[i] = jS_diag;

256:       if (num_cols_offd)

257:       {

258:          S_offd_i[i] = jS_offd;

259:       }

260:

261:       diag = A_diag_data[A_diag_i[i]];

262:

263:       /* compute scaling factor and row sum */

264:       row_scale = 0.0;

265:       row_sum = diag;

266:       if (num_functions > 1)

267:       {

268:          if (diag < 0)

269:          {

270:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

271:             {

272:                if (dof_func[i] == dof_func[A_diag_j[jA]])

273:                {

274:                   row_scale = hypre_max(row_scale, A_diag_data[jA]);

275:                   row_sum += A_diag_data[jA];

276:                }

277:             }

278:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

279:             {

280:                if (dof_func[i] == dof_func_offd[A_offd_j[jA]])

281:                {

282:                   row_scale = hypre_max(row_scale, A_offd_data[jA]);

283:                   row_sum += A_offd_data[jA];

[...]

289:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

290:             {

291:                if (dof_func[i] == dof_func[A_diag_j[jA]])

292:                {

293:                   row_scale = hypre_min(row_scale, A_diag_data[jA]);

294:                   row_sum += A_diag_data[jA];

295:                }

296:             }

297:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

298:             {

299:                if (dof_func[i] == dof_func_offd[A_offd_j[jA]])

300:                {

301:                   row_scale = hypre_min(row_scale, A_offd_data[jA]);

302:                   row_sum += A_offd_data[jA];

[...]

309:          if (diag < 0)

310:          {

311:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

312:             {

313:                row_scale = hypre_max(row_scale, A_diag_data[jA]);

314:                row_sum += A_diag_data[jA];

315:             }

316:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

317:             {

318:                row_scale = hypre_max(row_scale, A_offd_data[jA]);

319:                row_sum += A_offd_data[jA];

320:             }

321:          }

322:          else

323:          {

324:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

325:             {

326:                row_scale = hypre_min(row_scale, A_diag_data[jA]);

327:                row_sum += A_diag_data[jA];

328:             }

329:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

330:             {

331:                row_scale = hypre_min(row_scale, A_offd_data[jA]);

332:                row_sum += A_offd_data[jA];

333:             }

334:          } /* diag >= 0*/

335:       } /* num_functions <= 1 */

336:

337:       jS_diag += A_diag_i[i + 1] - A_diag_i[i] - 1;

338:       jS_offd += A_offd_i[i + 1] - A_offd_i[i];

339:

340:       /* compute row entries of S */

341:       S_temp_diag_j[A_diag_i[i]] = -1;

342:       if ((fabs(row_sum) > fabs(diag)*max_row_sum) && (max_row_sum < 1.0))

343:       {

344:          /* make all dependencies weak */

345:          for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

346:          {

347:             S_temp_diag_j[jA] = -1;

348:          }

349:          jS_diag -= A_diag_i[i + 1] - (A_diag_i[i] + 1);

350:

351:          for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

352:          {

353:             S_temp_offd_j[jA] = -1;

354:          }

355:          jS_offd -= A_offd_i[i + 1] - A_offd_i[i];

356:       }

357:       else

358:       {

359:          if (num_functions > 1)

360:          {

361:             if (diag < 0)

362:             {

363:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

364:                {

365:                   if (A_diag_data[jA] <= strength_threshold * row_scale

366:                       || dof_func[i] != dof_func[A_diag_j[jA]])

367:                   {

368:                      S_temp_diag_j[jA] = -1;

369:                      --jS_diag;

370:                   }

371:                   else

372:                   {

373:                      S_temp_diag_j[jA] = A_diag_j[jA];

374:                   }

375:                }

376:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

377:                {

378:                   if (A_offd_data[jA] <= strength_threshold * row_scale

379:                       || dof_func[i] != dof_func_offd[A_offd_j[jA]])

380:                   {

381:                      S_temp_offd_j[jA] = -1;

382:                      --jS_offd;

383:                   }

384:                   else

385:                   {

386:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

392:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

393:                {

394:                   if (A_diag_data[jA] >= strength_threshold * row_scale

395:                       || dof_func[i] != dof_func[A_diag_j[jA]])

396:                   {

397:                      S_temp_diag_j[jA] = -1;

398:                      --jS_diag;

399:                   }

400:                   else

401:                   {

402:                      S_temp_diag_j[jA] = A_diag_j[jA];

403:                   }

404:                }

405:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

406:                {

407:                   if (A_offd_data[jA] >= strength_threshold * row_scale

408:                       || dof_func[i] != dof_func_offd[A_offd_j[jA]])

409:                   {

410:                      S_temp_offd_j[jA] = -1;

411:                      --jS_offd;

412:                   }

413:                   else

414:                   {

415:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

422:             if (diag < 0)

423:             {

424:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

425:                {

426:                   if (A_diag_data[jA] <= strength_threshold * row_scale)

427:                   {

428:                      S_temp_diag_j[jA] = -1;

429:                      --jS_diag;

430:                   }

431:                   else

432:                   {

433:                      S_temp_diag_j[jA] = A_diag_j[jA];

434:                   }

435:                }

436:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

437:                {

438:                   if (A_offd_data[jA] <= strength_threshold * row_scale)

439:                   {

440:                      S_temp_offd_j[jA] = -1;

441:                      --jS_offd;

442:                   }

443:                   else

444:                   {

445:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

451:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

452:                {

453:                   if (A_diag_data[jA] >= strength_threshold * row_scale)

454:                   {

455:                      S_temp_diag_j[jA] = -1;

456:                      --jS_diag;

457:                   }

458:                   else

459:                   {

460:                      S_temp_diag_j[jA] = A_diag_j[jA];

461:                   }

462:                }

463:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

464:                {

465:                   if (A_offd_data[jA] >= strength_threshold * row_scale)

466:                   {

467:                      S_temp_offd_j[jA] = -1;

468:                      --jS_offd;

469:                   }

470:                   else

471:                   {

472:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

480:    hypre_prefix_sum_pair(&jS_diag, S_diag_i + num_variables, &jS_offd, S_offd_i + num_variables, prefix_sum_workspace);

[...]

492:    for (i = start; i < stop; i++)

493:    {

494:       S_diag_i[i] += jS_diag;

495:       S_offd_i[i] += jS_offd;

496:

497:       jS = S_diag_i[i];

498:       for (jA = A_diag_i[i]; jA < A_diag_i[i+1]; jA++)

499:       {

500:          if (S_temp_diag_j[jA] > -1)

501:          {

502:             S_diag_j[jS]    = S_temp_diag_j[jA];

503:             jS++;

504:          }

505:       }

506:

507:       jS = S_offd_i[i];

508:       for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

509:       {

510:          if (S_temp_offd_j[jA] > -1)

511:          {

512:             S_offd_j[jS]    = S_temp_offd_j[jA];

513:             jS++;

0x461580 SUB	SP, SP, #240

0x461584 STP	X29, X30, [SP, #144]

0x461588 STP	X28, X27, [SP, #160]

0x46158c STP	X26, X25, [SP, #176]

0x461590 STP	X24, X23, [SP, #192]

0x461594 STP	X22, X21, [SP, #208]

0x461598 STP	X20, X19, [SP, #224]

0x46159c ADD	X29, SP, #144

0x4615a0 ORR	X22, XZR, X2

0x4615a4 LDR	X2, [X2]

0x4615a8 LDR	X28, [X29, #184]

0x4615ac LDR	X25, [X29, #168]

0x4615b0 SUB	X0, X29, #8

0x4615b4 SUB	X1, X29, #16

0x4615b8 ORR	X19, XZR, X7

0x4615bc ORR	X24, XZR, X6

0x4615c0 LDR	X27, [X29, #152]

0x4615c4 LDR	X26, [X29, #120]

0x4615c8 ORR	X20, XZR, X5

0x4615cc ORR	X23, XZR, X4

0x4615d0 ORR	X21, XZR, X3

0x4615d4 BL	4a4740

0x4615d8 LDP	X9, X11, [X29, #1008]

0x4615dc LDR	X8, [X21]

0x4615e0 STP	XZR, XZR, [X29, #992]

0x4615e4 CMP	X11, X9

0x4615e8 B.GE	462200

0x4615ec LDP	X10, X9, [X29, #136]

0x4615f0 LDP	X14, X13, [X29, #104]

0x4615f4 LDR	X3, [X29, #176]

0x4615f8 MOVI	D2, #0

0x4615fc FMOV	D3, #1.0000000

0x461600 LDR	X7, [X29, #160]

0x461604 LDR	X17, [X24]

0x461608 LDR	X12, [X29, #128]

0x46160c STP	X20, X19, [SP, #40]

0x461610 LDR	X18, [X19]

0x461614 LDR	X15, [X29, #96]

0x461618 LDR	X16, [X20]

0x46161c LDR	X0, [X26]

0x461620 LDR	X6, [X27]

0x461624 STR	X28, [SP, #8]

0x461628 MOVN	X28, #0

0x46162c STR	X21, [SP, #32]

0x461630 STP	X27, X26, [SP, #16]

0x461634 LDR	X1, [X9]

0x461638 LDR	X5, [X13]

0x46163c LDR	D0, [X7]

0x461640 LDR	D1, [X3]

0x461644 ADD	X3, X17, #16

0x461648 LDR	X19, [X10]

0x46164c LDR	X2, [X14]

0x461650 LDR	X4, [X12]

0x461654 LDR	X7, [X25]

0x461658 STP	X3, X19, [X29, #968]

0x46165c ADD	X3, X1, #16

0x461660 STUR	X5, [X29, #472]

0x461664 STUR	X3, [X29, #448]

0x461668 ADD	X3, X5, #8

0x46166c STR	X3, [SP, #72]

0x461670 ADD	X5, X17, #8

0x461674 ADD	X3, X19, #8

0x461678 STP	X3, X5, [SP, #56]

0x46167c B	46169c

    (572) 0x461680 SUB	X3, X19, X3

    (572) 0x461684 LDUR	X19, [X29, #480]

    (572) 0x461688 ADD	X3, X3, X19

    (572) 0x46168c STUR	X3, [X29, #480]

    (572) 0x461690 LDUR	X3, [X29, #496]

    (572) 0x461694 CMP	X11, X3

    (572) 0x461698 B.GE	4621f4

    (572) 0x46169c ORR	X21, XZR, X11

    (572) 0x4616a0 LDUR	X11, [X29, #488]

    (572) 0x4616a4 STR	X11, [X8, X21,LSL #3]

    (572) 0x4616a8 LDR	X11, [X23]

    (572) 0x4616ac CBZ	X11, 4616b8

    (572) 0x4616b0 LDUR	X11, [X29, #480]

    (572) 0x4616b4 STR	X11, [X16, X21,LSL #3]

    (572) 0x4616b8 LDR	X24, [X18, X21,LSL #3]

    (572) 0x4616bc LDR	X3, [X15]

    (572) 0x4616c0 ADD	X11, X21, #1

    (572) 0x4616c4 MOVI	D4, #0

    (572) 0x4616c8 LDR	X30, [X18, X11,LSL #3]

    (572) 0x4616cc LDR	D5, [X17, X24,LSL #3]

    (572) 0x4616d0 ADD	X26, X24, #1

    (572) 0x4616d4 CMP	X3, #2

    (572) 0x4616d8 B.LT	461720

    (572) 0x4616dc FCMP	D5, #0

    (572) 0x4616e0 B.PL	461884

    (572) 0x4616e4 FMOV	D6, D5

    (572) 0x4616e8 CMP	X26, X30

    (572) 0x4616ec B.GE	461a40

    (572) 0x4616f0 LDR	X27, [X2, X21,LSL #3]

    (572) 0x4616f4 ORN	W3, WZR, W24

    (572) 0x4616f8 MOVI	D4, #0

    (572) 0x4616fc SUB	X19, X30, #2

    (572) 0x461700 ADD	W3, W30, W3

    (572) 0x461704 TBNZ	W3, #0, 461a04

    (572) 0x461708 FMOV	D6, D5

    (572) 0x46170c CMP	X19, X24

    (572) 0x461710 B.EQ	461a40

    (572) 0x461714 B	461adc

0x461718 HINT	#0

0x46171c HINT	#0

    (572) 0x461720 FCMP	D5, #0

    (572) 0x461724 B.PL	4618c0

    (572) 0x461728 FMOV	D6, D5

    (572) 0x46172c CMP	X26, X30

    (572) 0x461730 B.GE	4617e0

    (572) 0x461734 ORN	W3, WZR, W24

    (572) 0x461738 SUB	X19, X30, X24

    (572) 0x46173c MOVI	D4, #0

    (572) 0x461740 FMOV	D6, D5

    (572) 0x461744 SUB	X19, X19, #2

    (572) 0x461748 ADD	W3, W30, W3

    (572) 0x46174c ANDS	X20, X3, #4160

    (572) 0x461750 B.EQ	46177c

    (572) 0x461754 HINT	#0

    (572) 0x461758 HINT	#0

    (572) 0x46175c HINT	#0

      (580) 0x461760 LDR	D7, [X17, X26,LSL #3]

      (580) 0x461764 ADD	X26, X26, #1

      (580) 0x461768 FCMP	D4, D7

      (580) 0x46176c FADD	D6, D6, D7

      (580) 0x461770 FCSEL	D4, D7, D4, #4

      (580) 0x461774 SUBS	X20, X20, #1

      (580) 0x461778 B.NE	461760

    (572) 0x46177c CMP	X19, #3

    (572) 0x461780 B.CC	4617e0

    (572) 0x461784 LDUR	X3, [X29, #456]

    (572) 0x461788 SUB	X19, X30, X26

    (572) 0x46178c ADD	X20, X3, X26,LSL #3

    (572) 0x461790 HINT	#0

    (572) 0x461794 HINT	#0

    (572) 0x461798 HINT	#0

    (572) 0x46179c HINT	#0

      (579) 0x4617a0 LDP	D7, D16, [X20, #1008]

      (579) 0x4617a4 FCMP	D4, D7

      (579) 0x4617a8 FADD	D6, D6, D7

      (579) 0x4617ac FCSEL	D4, D7, D4, #4

      (579) 0x4617b0 FADD	D6, D6, D16

      (579) 0x4617b4 FCMP	D4, D16

      (579) 0x4617b8 FCSEL	D4, D16, D4, #4

      (579) 0x4617bc LDP	D7, D16, [X20], #32

      (579) 0x4617c0 FCMP	D4, D7

      (579) 0x4617c4 FADD	D6, D6, D7

      (579) 0x4617c8 FCSEL	D4, D7, D4, #4

      (579) 0x4617cc FADD	D6, D6, D16

      (579) 0x4617d0 FCMP	D4, D16

      (579) 0x4617d4 FCSEL	D4, D16, D4, #4

      (579) 0x4617d8 SUBS	X19, X19, #4

      (579) 0x4617dc B.NE	4617a0

    (572) 0x4617e0 LDR	X20, [X0, X21,LSL #3]

    (572) 0x4617e4 LDR	X19, [X0, X11,LSL #3]

    (572) 0x4617e8 CMP	X19, X20

    (572) 0x4617ec B.LE	461d08

    (572) 0x4617f0 SUB	W3, W19, W20

    (572) 0x4617f4 ORR	X26, XZR, X20

    (572) 0x4617f8 ANDS	X27, X3, #4160

    (572) 0x4617fc B.EQ	46181c

      (578) 0x461800 LDR	D7, [X1, X26,LSL #3]

      (578) 0x461804 ADD	X26, X26, #1

      (578) 0x461808 FCMP	D4, D7

      (578) 0x46180c FADD	D6, D6, D7

      (578) 0x461810 FCSEL	D4, D7, D4, #4

      (578) 0x461814 SUBS	X27, X27, #1

      (578) 0x461818 B.NE	461800

    (572) 0x46181c ORN	X3, XZR, X20

    (572) 0x461820 ADD	X3, X19, X3

    (572) 0x461824 CMP	X3, #3

    (572) 0x461828 B.CC	461d08

    (572) 0x46182c LDUR	X3, [X29, #448]

    (572) 0x461830 SUB	X19, X19, X26

    (572) 0x461834 ADD	X20, X3, X26,LSL #3

    (572) 0x461838 HINT	#0

    (572) 0x46183c HINT	#0

      (577) 0x461840 LDP	D7, D16, [X20, #1008]

      (577) 0x461844 FCMP	D4, D7

      (577) 0x461848 FADD	D6, D6, D7

      (577) 0x46184c FCSEL	D4, D7, D4, #4

      (577) 0x461850 FADD	D6, D6, D16

      (577) 0x461854 FCMP	D4, D16

      (577) 0x461858 FCSEL	D4, D16, D4, #4

      (577) 0x46185c LDP	D7, D16, [X20], #32

      (577) 0x461860 FCMP	D4, D7

      (577) 0x461864 FADD	D6, D6, D7

      (577) 0x461868 FCSEL	D4, D7, D4, #4

      (577) 0x46186c FADD	D6, D6, D16

      (577) 0x461870 FCMP	D4, D16

      (577) 0x461874 FCSEL	D4, D16, D4, #4

      (577) 0x461878 SUBS	X19, X19, #4

      (577) 0x46187c B.NE	461840

    (572) 0x461880 B	461d08

    (572) 0x461884 FMOV	D6, D5

    (572) 0x461888 CMP	X26, X30

    (572) 0x46188c B.GE	461aa8

    (572) 0x461890 LDR	X27, [X2, X21,LSL #3]

    (572) 0x461894 ORN	W3, WZR, W24

    (572) 0x461898 MOVI	D4, #0

    (572) 0x46189c SUB	X19, X30, #2

    (572) 0x4618a0 ADD	W3, W30, W3

    (572) 0x4618a4 TBNZ	W3, #0, 461a74

    (572) 0x4618a8 FMOV	D6, D5

    (572) 0x4618ac CMP	X19, X24

    (572) 0x4618b0 B.EQ	461aa8

    (572) 0x4618b4 B	461c34

0x4618b8 HINT	#0

0x4618bc HINT	#0

    (572) 0x4618c0 FMOV	D6, D5

    (572) 0x4618c4 CMP	X26, X30

    (572) 0x4618c8 B.GE	461960

    (572) 0x4618cc ORN	W3, WZR, W24

    (572) 0x4618d0 SUB	X19, X30, X24

    (572) 0x4618d4 MOVI	D4, #0

    (572) 0x4618d8 FMOV	D6, D5

    (572) 0x4618dc SUB	X19, X19, #2

    (572) 0x4618e0 ADD	W3, W30, W3

    (572) 0x4618e4 ANDS	X20, X3, #4160

    (572) 0x4618e8 B.EQ	461908

      (576) 0x4618ec LDR	D7, [X17, X26,LSL #3]

      (576) 0x4618f0 ADD	X26, X26, #1

      (576) 0x4618f4 FCMP	D4, D7

      (576) 0x4618f8 FADD	D6, D6, D7

      (576) 0x4618fc FCSEL	D4, D4, D7, #4

      (576) 0x461900 SUBS	X20, X20, #1

      (576) 0x461904 B.NE	4618ec

    (572) 0x461908 CMP	X19, #3

    (572) 0x46190c B.CC	461960

    (572) 0x461910 LDUR	X3, [X29, #456]

    (572) 0x461914 SUB	X19, X30, X26

    (572) 0x461918 ADD	X20, X3, X26,LSL #3

    (572) 0x46191c HINT	#0

      (575) 0x461920 LDP	D7, D16, [X20, #1008]

      (575) 0x461924 FCMP	D4, D7

      (575) 0x461928 FADD	D6, D6, D7

      (575) 0x46192c FCSEL	D4, D4, D7, #4

      (575) 0x461930 FADD	D6, D6, D16

      (575) 0x461934 FCMP	D4, D16

      (575) 0x461938 FCSEL	D4, D4, D16, #4

      (575) 0x46193c LDP	D7, D16, [X20], #32

      (575) 0x461940 FCMP	D4, D7

      (575) 0x461944 FADD	D6, D6, D7

      (575) 0x461948 FCSEL	D4, D4, D7, #4

      (575) 0x46194c FADD	D6, D6, D16

      (575) 0x461950 FCMP	D4, D16

      (575) 0x461954 FCSEL	D4, D4, D16, #4

      (575) 0x461958 SUBS	X19, X19, #4

      (575) 0x46195c B.NE	461920

    (572) 0x461960 LDR	X20, [X0, X21,LSL #3]

    (572) 0x461964 LDR	X19, [X0, X11,LSL #3]

    (572) 0x461968 CMP	X19, X20

    (572) 0x46196c B.LE	461d08

    (572) 0x461970 SUB	W3, W19, W20

    (572) 0x461974 ORR	X26, XZR, X20

    (572) 0x461978 ANDS	X27, X3, #4160

    (572) 0x46197c B.EQ	46199c

      (574) 0x461980 LDR	D7, [X1, X26,LSL #3]

      (574) 0x461984 ADD	X26, X26, #1

      (574) 0x461988 FCMP	D4, D7

      (574) 0x46198c FADD	D6, D6, D7

      (574) 0x461990 FCSEL	D4, D4, D7, #4

      (574) 0x461994 SUBS	X27, X27, #1

      (574) 0x461998 B.NE	461980

    (572) 0x46199c ORN	X3, XZR, X20

    (572) 0x4619a0 ADD	X3, X19, X3

    (572) 0x4619a4 CMP	X3, #3

    (572) 0x4619a8 B.CC	461d08

    (572) 0x4619ac LDUR	X3, [X29, #448]

    (572) 0x4619b0 SUB	X19, X19, X26

    (572) 0x4619b4 ADD	X20, X3, X26,LSL #3

    (572) 0x4619b8 HINT	#0

    (572) 0x4619bc HINT	#0

      (573) 0x4619c0 LDP	D7, D16, [X20, #1008]

      (573) 0x4619c4 FCMP	D4, D7

      (573) 0x4619c8 FADD	D6, D6, D7

      (573) 0x4619cc FCSEL	D4, D4, D7, #4

      (573) 0x4619d0 FADD	D6, D6, D16

      (573) 0x4619d4 FCMP	D4, D16

      (573) 0x4619d8 FCSEL	D4, D4, D16, #4

      (573) 0x4619dc LDP	D7, D16, [X20], #32

      (573) 0x4619e0 FCMP	D4, D7

      (573) 0x4619e4 FADD	D6, D6, D7

      (573) 0x4619e8 FCSEL	D4, D4, D7, #4

      (573) 0x4619ec FADD	D6, D6, D16

      (573) 0x4619f0 FCMP	D4, D16

      (573) 0x4619f4 FCSEL	D4, D4, D16, #4

      (573) 0x4619f8 SUBS	X19, X19, #4

      (573) 0x4619fc B.NE	4619c0

    (572) 0x461a00 B	461d08

    (572) 0x461a04 LDUR	X3, [X29, #472]

    (572) 0x461a08 MOVI	D4, #0

    (572) 0x461a0c FMOV	D6, D5

    (572) 0x461a10 LDR	X3, [X3, X26,LSL #3]

    (572) 0x461a14 LDR	X3, [X2, X3,LSL #3]

    (572) 0x461a18 CMP	X27, X3

    (572) 0x461a1c B.NE	461a2c

    (572) 0x461a20 LDR	D6, [X17, X26,LSL #3]

    (572) 0x461a24 FMAXNM	D4, D6, D2

    (572) 0x461a28 FADD	D6, D5, D6

    (572) 0x461a2c ADD	X26, X24, #2

    (572) 0x461a30 CMP	X19, X24

    (572) 0x461a34 B.NE	461adc

    (572) 0x461a38 HINT	#0

    (572) 0x461a3c HINT	#0

    (572) 0x461a40 LDR	X27, [X0, X21,LSL #3]

    (572) 0x461a44 LDR	X19, [X0, X11,LSL #3]

    (572) 0x461a48 CMP	X19, X27

    (572) 0x461a4c B.LE	461d08

    (572) 0x461a50 LDR	X26, [X2, X21,LSL #3]

    (572) 0x461a54 LDR	X20, [X9]

    (572) 0x461a58 SUB	W3, W19, W27

    (572) 0x461a5c TBNZ	W3, #0, 461b74

    (572) 0x461a60 ORR	X3, XZR, X27

    (572) 0x461a64 ADD	X27, X27, #1

    (572) 0x461a68 CMP	X19, X27

    (572) 0x461a6c B.NE	461ba8

    (572) 0x461a70 B	461d08

    (572) 0x461a74 LDUR	X3, [X29, #472]

    (572) 0x461a78 MOVI	D4, #0

    (572) 0x461a7c FMOV	D6, D5

    (572) 0x461a80 LDR	X3, [X3, X26,LSL #3]

    (572) 0x461a84 LDR	X3, [X2, X3,LSL #3]

    (572) 0x461a88 CMP	X27, X3

    (572) 0x461a8c B.NE	461a9c

    (572) 0x461a90 LDR	D6, [X17, X26,LSL #3]

    (572) 0x461a94 FMIN	D4, D6, D2

    (572) 0x461a98 FADD	D6, D5, D6

    (572) 0x461a9c ADD	X26, X24, #2

    (572) 0x461aa0 CMP	X19, X24

    (572) 0x461aa4 B.NE	461c34

    (572) 0x461aa8 LDR	X27, [X0, X21,LSL #3]

    (572) 0x461aac LDR	X19, [X0, X11,LSL #3]

    (572) 0x461ab0 CMP	X19, X27

    (572) 0x461ab4 B.LE	461d08

    (572) 0x461ab8 LDR	X26, [X2, X21,LSL #3]

    (572) 0x461abc LDR	X20, [X9]

    (572) 0x461ac0 SUB	W3, W19, W27

    (572) 0x461ac4 TBNZ	W3, #0, 461cd4

    (572) 0x461ac8 ORR	X3, XZR, X27

    (572) 0x461acc ADD	X27, X27, #1

    (572) 0x461ad0 CMP	X19, X27

    (572) 0x461ad4 B.EQ	461d08

  (582) 0x461ad8 B	462154

    (572) 0x461adc LDR	X5, [SP, #72]

    (572) 0x461ae0 UBFM	X3, X26, #61, #60

    (572) 0x461ae4 SUB	X19, X30, X26

    (572) 0x461ae8 ADD	X26, X5, X3

    (572) 0x461aec LDR	X5, [SP, #64]

    (572) 0x461af0 ADD	X20, X5, X3

    (572) 0x461af4 B	461b10

0x461af8 HINT	#0

0x461afc HINT	#0

      (585) 0x461b00 SUBS	X19, X19, #2

      (585) 0x461b04 ADD	X26, X26, #16

      (585) 0x461b08 ADD	X20, X20, #16

      (585) 0x461b0c B.EQ	461a40

      (585) 0x461b10 LDUR	X3, [X26, #504]

      (585) 0x461b14 LDR	X3, [X2, X3,LSL #3]

      (585) 0x461b18 CMP	X27, X3

      (585) 0x461b1c B.EQ	461b40

      (585) 0x461b20 LDR	X3, [X26]

      (585) 0x461b24 LDR	X3, [X2, X3,LSL #3]

      (585) 0x461b28 CMP	X27, X3

      (585) 0x461b2c B.NE	461b00

      (585) 0x461b30 B	461b60

0x461b34 HINT	#0

0x461b38 HINT	#0

0x461b3c HINT	#0

      (585) 0x461b40 LDUR	D7, [X20, #504]

      (585) 0x461b44 FCMP	D4, D7

      (585) 0x461b48 FADD	D6, D6, D7

      (585) 0x461b4c FCSEL	D4, D7, D4, #4

      (585) 0x461b50 LDR	X3, [X26]

      (585) 0x461b54 LDR	X3, [X2, X3,LSL #3]

      (585) 0x461b58 CMP	X27, X3

      (585) 0x461b5c B.NE	461b00

      (585) 0x461b60 LDR	D7, [X20]

      (585) 0x461b64 FCMP	D4, D7

      (585) 0x461b68 FADD	D6, D6, D7

      (585) 0x461b6c FCSEL	D4, D7, D4, #4

      (585) 0x461b70 B	461b00

    (572) 0x461b74 LDUR	X3, [X29, #464]

    (572) 0x461b78 LDR	X3, [X3, X27,LSL #3]

    (572) 0x461b7c LDR	X3, [X4, X3,LSL #3]

    (572) 0x461b80 CMP	X26, X3

    (572) 0x461b84 B.NE	461b98

    (572) 0x461b88 LDR	D7, [X20, X27,LSL #3]

    (572) 0x461b8c FCMP	D4, D7

    (572) 0x461b90 FADD	D6, D6, D7

    (572) 0x461b94 FCSEL	D4, D7, D4, #4

    (572) 0x461b98 ADD	X3, X27, #1

    (572) 0x461b9c ADD	X27, X27, #1

    (572) 0x461ba0 CMP	X19, X27

    (572) 0x461ba4 B.EQ	461d08

    (572) 0x461ba8 LDR	X5, [SP, #56]

    (572) 0x461bac SUB	X27, X19, X3

    (572) 0x461bb0 UBFM	X3, X3, #61, #60

    (572) 0x461bb4 ADD	X19, X5, X3

    (572) 0x461bb8 ADD	X3, X20, X3

    (572) 0x461bbc ADD	X20, X3, #8

    (572) 0x461bc0 B	461bd4

      (584) 0x461bc4 SUBS	X27, X27, #2

      (584) 0x461bc8 ADD	X19, X19, #16

      (584) 0x461bcc ADD	X20, X20, #16

      (584) 0x461bd0 B.EQ	461d08

      (584) 0x461bd4 LDUR	X3, [X19, #504]

      (584) 0x461bd8 LDR	X3, [X4, X3,LSL #3]

      (584) 0x461bdc CMP	X26, X3

      (584) 0x461be0 B.EQ	461c00

      (584) 0x461be4 LDR	X3, [X19]

      (584) 0x461be8 LDR	X3, [X4, X3,LSL #3]

      (584) 0x461bec CMP	X26, X3

      (584) 0x461bf0 B.NE	461bc4

      (584) 0x461bf4 B	461c20

0x461bf8 HINT	#0

0x461bfc HINT	#0

      (584) 0x461c00 LDUR	D7, [X20, #504]

      (584) 0x461c04 FCMP	D4, D7

      (584) 0x461c08 FADD	D6, D6, D7

      (584) 0x461c0c FCSEL	D4, D7, D4, #4

      (584) 0x461c10 LDR	X3, [X19]

      (584) 0x461c14 LDR	X3, [X4, X3,LSL #3]

      (584) 0x461c18 CMP	X26, X3

      (584) 0x461c1c B.NE	461bc4

      (584) 0x461c20 LDR	D7, [X20]

      (584) 0x461c24 FCMP	D4, D7

      (584) 0x461c28 FADD	D6, D6, D7

      (584) 0x461c2c FCSEL	D4, D7, D4, #4

      (584) 0x461c30 B	461bc4

    (572) 0x461c34 LDR	X5, [SP, #72]

    (572) 0x461c38 UBFM	X3, X26, #61, #60

    (572) 0x461c3c SUB	X19, X30, X26

    (572) 0x461c40 ADD	X26, X5, X3

    (572) 0x461c44 LDR	X5, [SP, #64]

    (572) 0x461c48 ADD	X20, X5, X3

    (572) 0x461c4c B	461c70

0x461c50 HINT	#0

0x461c54 HINT	#0

0x461c58 HINT	#0

0x461c5c HINT	#0

      (583) 0x461c60 SUBS	X19, X19, #2

      (583) 0x461c64 ADD	X26, X26, #16

      (583) 0x461c68 ADD	X20, X20, #16

      (583) 0x461c6c B.EQ	461aa8

      (583) 0x461c70 LDUR	X3, [X26, #504]

      (583) 0x461c74 LDR	X3, [X2, X3,LSL #3]

      (583) 0x461c78 CMP	X27, X3

      (583) 0x461c7c B.EQ	461ca0

      (583) 0x461c80 LDR	X3, [X26]

      (583) 0x461c84 LDR	X3, [X2, X3,LSL #3]

      (583) 0x461c88 CMP	X27, X3

      (583) 0x461c8c B.NE	461c60

      (583) 0x461c90 B	461cc0

0x461c94 HINT	#0

0x461c98 HINT	#0

0x461c9c HINT	#0

      (583) 0x461ca0 LDUR	D7, [X20, #504]

      (583) 0x461ca4 FCMP	D4, D7

      (583) 0x461ca8 FADD	D6, D6, D7

      (583) 0x461cac FCSEL	D4, D4, D7, #4

      (583) 0x461cb0 LDR	X3, [X26]

      (583) 0x461cb4 LDR	X3, [X2, X3,LSL #3]

      (583) 0x461cb8 CMP	X27, X3

      (583) 0x461cbc B.NE	461c60

      (583) 0x461cc0 LDR	D7, [X20]

      (583) 0x461cc4 FCMP	D4, D7

      (583) 0x461cc8 FADD	D6, D6, D7

      (583) 0x461ccc FCSEL	D4, D4, D7, #4

      (583) 0x461cd0 B	461c60

    (572) 0x461cd4 LDUR	X3, [X29, #464]

    (572) 0x461cd8 LDR	X3, [X3, X27,LSL #3]

    (572) 0x461cdc LDR	X3, [X4, X3,LSL #3]

    (572) 0x461ce0 CMP	X26, X3

    (572) 0x461ce4 B.NE	461cf8

    (572) 0x461ce8 LDR	D7, [X20, X27,LSL #3]

    (572) 0x461cec FCMP	D4, D7

    (572) 0x461cf0 FADD	D6, D6, D7

    (572) 0x461cf4 FCSEL	D4, D4, D7, #4

    (572) 0x461cf8 ADD	X3, X27, #1

    (572) 0x461cfc ADD	X27, X27, #1

    (572) 0x461d00 CMP	X19, X27

    (572) 0x461d04 B.NE	462154

    (572) 0x461d08 ORN	X3, XZR, X24

    (572) 0x461d0c LDUR	X19, [X29, #488]

    (572) 0x461d10 FCMP	D0, D3

    (572) 0x461d14 ADD	X3, X30, X3

    (572) 0x461d18 ADD	X3, X3, X19

    (572) 0x461d1c STUR	X3, [X29, #488]

    (572) 0x461d20 LDR	X3, [X0, X11,LSL #3]

    (572) 0x461d24 LDR	X19, [X0, X21,LSL #3]

    (572) 0x461d28 SUB	X3, X3, X19

    (572) 0x461d2c LDUR	X19, [X29, #480]

    (572) 0x461d30 ADD	X3, X3, X19

    (572) 0x461d34 STUR	X3, [X29, #480]

    (572) 0x461d38 LDR	X3, [X18, X21,LSL #3]

    (572) 0x461d3c STR	X28, [X6, X3,LSL #3]

    (572) 0x461d40 B.PL	461dc4

    (572) 0x461d44 FABS	D7, D5

    (572) 0x461d48 FABS	D6, D6

    (572) 0x461d4c FMUL	D7, D0, D7

    (572) 0x461d50 FCMP	D6, D7

    (572) 0x461d54 B.LE	461dc4

    (572) 0x461d58 LDR	X3, [X18, X21,LSL #3]

    (572) 0x461d5c ADD	X19, X3, #1

    (572) 0x461d60 LDR	X3, [X18, X11,LSL #3]

    (572) 0x461d64 CMP	X19, X3

    (572) 0x461d68 B.GE	461d88

      (595) 0x461d6c STR	X28, [X6, X19,LSL #3]

      (595) 0x461d70 ADD	X19, X19, #1

      (595) 0x461d74 LDR	X3, [X18, X11,LSL #3]

      (595) 0x461d78 CMP	X19, X3

      (595) 0x461d7c B.LT	461d6c

    (572) 0x461d80 LDR	X19, [X18, X21,LSL #3]

    (572) 0x461d84 ADD	X19, X19, #1

    (572) 0x461d88 LDUR	X20, [X29, #488]

    (572) 0x461d8c SUB	X3, X19, X3

    (572) 0x461d90 ADD	X3, X3, X20

    (572) 0x461d94 STUR	X3, [X29, #488]

    (572) 0x461d98 LDR	X19, [X0, X21,LSL #3]

    (572) 0x461d9c LDR	X3, [X0, X11,LSL #3]

    (572) 0x461da0 CMP	X19, X3

    (572) 0x461da4 B.GE	461680

      (594) 0x461da8 STR	X28, [X7, X19,LSL #3]

      (594) 0x461dac ADD	X19, X19, #1

      (594) 0x461db0 LDR	X3, [X0, X11,LSL #3]

      (594) 0x461db4 CMP	X19, X3

      (594) 0x461db8 B.LT	461da8

    (572) 0x461dbc LDR	X19, [X0, X21,LSL #3]

    (572) 0x461dc0 B	461680

    (572) 0x461dc4 LDR	X3, [X18, X21,LSL #3]

    (572) 0x461dc8 LDR	X19, [X15]

    (572) 0x461dcc ADD	X24, X3, #1

    (572) 0x461dd0 LDR	X3, [X18, X11,LSL #3]

    (572) 0x461dd4 CMP	X19, #2

    (572) 0x461dd8 B.LT	461ee0

    (572) 0x461ddc FCMP	D5, #0

    (572) 0x461de0 B.PL	461fac

    (572) 0x461de4 CMP	X24, X3

    (572) 0x461de8 B.GE	461e54

    (572) 0x461dec LDR	X19, [X14]

    (572) 0x461df0 LDR	X20, [X13]

    (572) 0x461df4 FMUL	D5, D1, D4

    (572) 0x461df8 B	461e20

0x461dfc HINT	#0

      (593) 0x461e00 STR	X28, [X6, X24,LSL #3]

      (593) 0x461e04 LDUR	X3, [X29, #488]

      (593) 0x461e08 SUB	X3, X3, #1

      (593) 0x461e0c STUR	X3, [X29, #488]

      (593) 0x461e10 LDR	X3, [X18, X11,LSL #3]

      (593) 0x461e14 ADD	X24, X24, #1

      (593) 0x461e18 CMP	X24, X3

      (593) 0x461e1c B.GE	461e54

      (593) 0x461e20 LDR	D6, [X17, X24,LSL #3]

      (593) 0x461e24 FCMP	D6, D5

      (593) 0x461e28 B.LS	461e00

      (593) 0x461e2c LDR	X3, [X20, X24,LSL #3]

      (593) 0x461e30 LDR	X26, [X19, X21,LSL #3]

      (593) 0x461e34 LDR	X27, [X19, X3,LSL #3]

      (593) 0x461e38 CMP	X26, X27

      (593) 0x461e3c B.NE	461e00

      (593) 0x461e40 STR	X3, [X6, X24,LSL #3]

      (593) 0x461e44 LDR	X3, [X18, X11,LSL #3]

      (593) 0x461e48 ADD	X24, X24, #1

      (593) 0x461e4c CMP	X24, X3

      (593) 0x461e50 B.LT	461e20

    (572) 0x461e54 LDR	X19, [X0, X21,LSL #3]

    (572) 0x461e58 LDR	X3, [X0, X11,LSL #3]

    (572) 0x461e5c CMP	X19, X3

    (572) 0x461e60 B.GE	461690

    (572) 0x461e64 LDR	X20, [X14]

    (572) 0x461e68 LDR	X24, [X12]

    (572) 0x461e6c LDR	X26, [X10]

    (572) 0x461e70 FMUL	D4, D1, D4

    (572) 0x461e74 LDR	X27, [X25]

    (572) 0x461e78 B	461ea0

0x461e7c HINT	#0

      (592) 0x461e80 STR	X28, [X27, X19,LSL #3]

      (592) 0x461e84 LDUR	X3, [X29, #480]

      (592) 0x461e88 SUB	X3, X3, #1

      (592) 0x461e8c STUR	X3, [X29, #480]

      (592) 0x461e90 LDR	X3, [X0, X11,LSL #3]

      (592) 0x461e94 ADD	X19, X19, #1

      (592) 0x461e98 CMP	X19, X3

      (592) 0x461e9c B.GE	461690

      (592) 0x461ea0 LDR	D5, [X1, X19,LSL #3]

      (592) 0x461ea4 FCMP	D5, D4

      (592) 0x461ea8 B.LS	461e80

      (592) 0x461eac LDR	X3, [X26, X19,LSL #3]

      (592) 0x461eb0 LDR	X30, [X20, X21,LSL #3]

      (592) 0x461eb4 LDR	X5, [X24, X3,LSL #3]

      (592) 0x461eb8 CMP	X30, X5

      (592) 0x461ebc B.NE	461e80

      (592) 0x461ec0 STR	X3, [X27, X19,LSL #3]

      (592) 0x461ec4 LDR	X3, [X0, X11,LSL #3]

      (592) 0x461ec8 ADD	X19, X19, #1

      (592) 0x461ecc CMP	X19, X3

      (592) 0x461ed0 B.LT	461ea0

    (572) 0x461ed4 B	461690

0x461ed8 HINT	#0

0x461edc HINT	#0

    (572) 0x461ee0 FCMP	D5, #0

    (572) 0x461ee4 B.PL	462098

    (572) 0x461ee8 CMP	X24, X3

    (572) 0x461eec B.GE	461f44

    (572) 0x461ef0 LDR	X19, [X13]

    (572) 0x461ef4 FMUL	D5, D1, D4

    (572) 0x461ef8 B	461f18

0x461efc HINT	#0

      (589) 0x461f00 LDR	X3, [X19, X24,LSL #3]

      (589) 0x461f04 STR	X3, [X6, X24,LSL #3]

      (589) 0x461f08 LDR	X3, [X18, X11,LSL #3]

      (589) 0x461f0c ADD	X24, X24, #1

      (589) 0x461f10 CMP	X24, X3

      (589) 0x461f14 B.GE	461f44

      (589) 0x461f18 LDR	D6, [X17, X24,LSL #3]

      (589) 0x461f1c FCMP	D6, D5

      (589) 0x461f20 B.HI	461f00

      (589) 0x461f24 STR	X28, [X6, X24,LSL #3]

      (589) 0x461f28 LDUR	X3, [X29, #488]

      (589) 0x461f2c SUB	X3, X3, #1

      (589) 0x461f30 STUR	X3, [X29, #488]

      (589) 0x461f34 LDR	X3, [X18, X11,LSL #3]

      (589) 0x461f38 ADD	X24, X24, #1

      (589) 0x461f3c CMP	X24, X3

      (589) 0x461f40 B.LT	461f18

    (572) 0x461f44 LDR	X19, [X0, X21,LSL #3]

    (572) 0x461f48 LDR	X3, [X0, X11,LSL #3]

    (572) 0x461f4c CMP	X19, X3

    (572) 0x461f50 B.GE	461690

    (572) 0x461f54 LDR	X20, [X25]

    (572) 0x461f58 LDR	X21, [X10]

    (572) 0x461f5c FMUL	D4, D1, D4

    (572) 0x461f60 B	461f7c

      (588) 0x461f64 LDR	X3, [X21, X19,LSL #3]

      (588) 0x461f68 STR	X3, [X20, X19,LSL #3]

      (588) 0x461f6c LDR	X3, [X0, X11,LSL #3]

      (588) 0x461f70 ADD	X19, X19, #1

      (588) 0x461f74 CMP	X19, X3

      (588) 0x461f78 B.GE	461690

      (588) 0x461f7c LDR	D5, [X1, X19,LSL #3]

      (588) 0x461f80 FCMP	D5, D4

      (588) 0x461f84 B.HI	461f64

      (588) 0x461f88 STR	X28, [X20, X19,LSL #3]

      (588) 0x461f8c LDUR	X3, [X29, #480]

      (588) 0x461f90 SUB	X3, X3, #1

      (588) 0x461f94 STUR	X3, [X29, #480]

      (588) 0x461f98 LDR	X3, [X0, X11,LSL #3]

      (588) 0x461f9c ADD	X19, X19, #1

      (588) 0x461fa0 CMP	X19, X3

      (588) 0x461fa4 B.LT	461f7c

    (572) 0x461fa8 B	461690

    (572) 0x461fac CMP	X24, X3

    (572) 0x461fb0 B.GE	462018

    (572) 0x461fb4 LDR	X19, [X14]

    (572) 0x461fb8 LDR	X20, [X13]

    (572) 0x461fbc FMUL	D5, D1, D4

    (572) 0x461fc0 B	461fe4

      (591) 0x461fc4 STR	X28, [X6, X24,LSL #3]

      (591) 0x461fc8 LDUR	X3, [X29, #488]

      (591) 0x461fcc SUB	X3, X3, #1

      (591) 0x461fd0 STUR	X3, [X29, #488]

      (591) 0x461fd4 LDR	X3, [X18, X11,LSL #3]

      (591) 0x461fd8 ADD	X24, X24, #1

      (591) 0x461fdc CMP	X24, X3

      (591) 0x461fe0 B.GE	462018

      (591) 0x461fe4 LDR	D6, [X17, X24,LSL #3]

      (591) 0x461fe8 FCMP	D6, D5

      (591) 0x461fec B.GE	461fc4

      (591) 0x461ff0 LDR	X3, [X20, X24,LSL #3]

      (591) 0x461ff4 LDR	X5, [X19, X21,LSL #3]

      (591) 0x461ff8 LDR	X26, [X19, X3,LSL #3]

      (591) 0x461ffc CMP	X5, X26

      (591) 0x462000 B.NE	461fc4

      (591) 0x462004 STR	X3, [X6, X24,LSL #3]

      (591) 0x462008 LDR	X3, [X18, X11,LSL #3]

      (591) 0x46200c ADD	X24, X24, #1

      (591) 0x462010 CMP	X24, X3

      (591) 0x462014 B.LT	461fe4

    (572) 0x462018 LDR	X19, [X0, X21,LSL #3]

    (572) 0x46201c LDR	X3, [X0, X11,LSL #3]

    (572) 0x462020 CMP	X19, X3

    (572) 0x462024 B.GE	461690

    (572) 0x462028 LDR	X20, [X14]

    (572) 0x46202c LDR	X24, [X12]

    (572) 0x462030 LDR	X26, [X10]

    (572) 0x462034 FMUL	D4, D1, D4

    (572) 0x462038 LDR	X27, [X25]

    (572) 0x46203c B	462060

      (590) 0x462040 STR	X28, [X27, X19,LSL #3]

      (590) 0x462044 LDUR	X3, [X29, #480]

      (590) 0x462048 SUB	X3, X3, #1

      (590) 0x46204c STUR	X3, [X29, #480]

      (590) 0x462050 LDR	X3, [X0, X11,LSL #3]

      (590) 0x462054 ADD	X19, X19, #1

      (590) 0x462058 CMP	X19, X3

      (590) 0x46205c B.GE	461690

      (590) 0x462060 LDR	D5, [X1, X19,LSL #3]

      (590) 0x462064 FCMP	D5, D4

      (590) 0x462068 B.GE	462040

      (590) 0x46206c LDR	X3, [X26, X19,LSL #3]

      (590) 0x462070 LDR	X5, [X20, X21,LSL #3]

      (590) 0x462074 LDR	X30, [X24, X3,LSL #3]

      (590) 0x462078 CMP	X5, X30

      (590) 0x46207c B.NE	462040

      (590) 0x462080 STR	X3, [X27, X19,LSL #3]

      (590) 0x462084 LDR	X3, [X0, X11,LSL #3]

      (590) 0x462088 ADD	X19, X19, #1

      (590) 0x46208c CMP	X19, X3

      (590) 0x462090 B.LT	462060

    (572) 0x462094 B	461690

    (572) 0x462098 FMUL	D4, D1, D4

    (572) 0x46209c CMP	X24, X3

    (572) 0x4620a0 B.GE	4620f0

    (572) 0x4620a4 LDR	X19, [X13]

    (572) 0x4620a8 B	4620c4

      (587) 0x4620ac LDR	X3, [X19, X24,LSL #3]

      (587) 0x4620b0 STR	X3, [X6, X24,LSL #3]

      (587) 0x4620b4 LDR	X3, [X18, X11,LSL #3]

      (587) 0x4620b8 ADD	X24, X24, #1

      (587) 0x4620bc CMP	X24, X3

      (587) 0x4620c0 B.GE	4620f0

      (587) 0x4620c4 LDR	D5, [X17, X24,LSL #3]

      (587) 0x4620c8 FCMP	D5, D4

      (587) 0x4620cc B.LT	4620ac

      (587) 0x4620d0 STR	X28, [X6, X24,LSL #3]

      (587) 0x4620d4 LDUR	X3, [X29, #488]

      (587) 0x4620d8 SUB	X3, X3, #1

      (587) 0x4620dc STUR	X3, [X29, #488]

      (587) 0x4620e0 LDR	X3, [X18, X11,LSL #3]

      (587) 0x4620e4 ADD	X24, X24, #1

      (587) 0x4620e8 CMP	X24, X3

      (587) 0x4620ec B.LT	4620c4

    (572) 0x4620f0 LDR	X19, [X0, X21,LSL #3]

    (572) 0x4620f4 LDR	X3, [X0, X11,LSL #3]

    (572) 0x4620f8 CMP	X19, X3

    (572) 0x4620fc B.GE	461690

    (572) 0x462100 LDR	X20, [X25]

    (572) 0x462104 LDR	X21, [X10]

    (572) 0x462108 B	462124

      (586) 0x46210c LDR	X3, [X21, X19,LSL #3]

      (586) 0x462110 STR	X3, [X20, X19,LSL #3]

      (586) 0x462114 LDR	X3, [X0, X11,LSL #3]

      (586) 0x462118 ADD	X19, X19, #1

      (586) 0x46211c CMP	X19, X3

      (586) 0x462120 B.GE	461690

      (586) 0x462124 LDR	D5, [X1, X19,LSL #3]

      (586) 0x462128 FCMP	D5, D4

      (586) 0x46212c B.LT	46210c

      (586) 0x462130 STR	X28, [X20, X19,LSL #3]

      (586) 0x462134 LDUR	X3, [X29, #480]

      (586) 0x462138 SUB	X3, X3, #1

      (586) 0x46213c STUR	X3, [X29, #480]

      (586) 0x462140 LDR	X3, [X0, X11,LSL #3]

      (586) 0x462144 ADD	X19, X19, #1

      (586) 0x462148 CMP	X19, X3

      (586) 0x46214c B.LT	462124

    (572) 0x462150 B	461690

  (582) 0x462154 LDR	X5, [SP, #56]

  (582) 0x462158 SUB	X27, X19, X3

  (582) 0x46215c UBFM	X3, X3, #61, #60

  (582) 0x462160 ADD	X19, X5, X3

  (582) 0x462164 ADD	X3, X20, X3

  (582) 0x462168 ADD	X20, X3, #8

  (582) 0x46216c B	462190

0x462170 HINT	#0

0x462174 HINT	#0

0x462178 HINT	#0

0x46217c HINT	#0

  (582) 0x462180 SUBS	X27, X27, #2

  (582) 0x462184 ADD	X19, X19, #16

  (582) 0x462188 ADD	X20, X20, #16

  (582) 0x46218c B.EQ	461d08

  (582) 0x462190 LDUR	X3, [X19, #504]

  (582) 0x462194 LDR	X3, [X4, X3,LSL #3]

  (582) 0x462198 CMP	X26, X3

  (582) 0x46219c B.EQ	4621c0

  (582) 0x4621a0 LDR	X3, [X19]

  (582) 0x4621a4 LDR	X3, [X4, X3,LSL #3]

  (582) 0x4621a8 CMP	X26, X3

  (582) 0x4621ac B.NE	462180

  (582) 0x4621b0 B	4621e0

0x4621b4 HINT	#0

0x4621b8 HINT	#0

0x4621bc HINT	#0

(581) 0x4621c0 LDUR	D7, [X20, #504]

(581) 0x4621c4 FCMP	D4, D7

(581) 0x4621c8 FADD	D6, D6, D7

(581) 0x4621cc FCSEL	D4, D4, D7, #4

(581) 0x4621d0 LDR	X3, [X19]

(581) 0x4621d4 LDR	X3, [X4, X3,LSL #3]

(581) 0x4621d8 CMP	X26, X3

(581) 0x4621dc B.NE	462180

  (582) 0x4621e0 LDR	D7, [X20]

  (582) 0x4621e4 FCMP	D4, D7

  (582) 0x4621e8 FADD	D6, D6, D7

  (582) 0x4621ec FCSEL	D4, D4, D7, #4

  (582) 0x4621f0 B	462180

0x4621f4 LDP	X20, X19, [SP, #40]

0x4621f8 LDP	X26, X21, [SP, #24]

0x4621fc LDP	X28, X27, [SP, #8]

0x462200 LDR	X9, [X22]

0x462204 LDR	X4, [X28]

0x462208 SUB	X0, X29, #24

0x46220c SUB	X2, X29, #32

0x462210 UBFM	X9, X9, #61, #60

0x462214 ADD	X1, X8, X9

0x462218 LDR	X8, [X20]

0x46221c ADD	X3, X8, X9

0x462220 BL	4a5310

0x462224 LDP	X8, X10, [X29, #1008]

0x462228 CMP	X10, X8

0x46222c B.GE	462324

0x462230 LDP	X9, X8, [X29, #192]

0x462234 LDR	X11, [X21]

0x462238 LDR	X12, [X20]

0x46223c LDR	X13, [X19]

0x462240 LDR	X14, [X27]

0x462244 LDR	X15, [X26]

0x462248 LDR	X16, [X25]

0x46224c B	46226c

0x462250 HINT	#0

0x462254 HINT	#0

0x462258 HINT	#0

0x46225c HINT	#0

  (569) 0x462260 LDUR	X17, [X29, #496]

  (569) 0x462264 CMP	X10, X17

  (569) 0x462268 B.GE	462324

  (569) 0x46226c ORR	X17, XZR, X10

  (569) 0x462270 LDUR	X10, [X29, #488]

  (569) 0x462274 LDR	X18, [X11, X17,LSL #3]

  (569) 0x462278 ADD	X10, X18, X10

  (569) 0x46227c STR	X10, [X11, X17,LSL #3]

  (569) 0x462280 LDUR	X10, [X29, #480]

  (569) 0x462284 LDR	X18, [X12, X17,LSL #3]

  (569) 0x462288 ADD	X10, X18, X10

  (569) 0x46228c STR	X10, [X12, X17,LSL #3]

  (569) 0x462290 ADD	X10, X17, #1

  (569) 0x462294 LDR	X18, [X13, X17,LSL #3]

  (569) 0x462298 LDR	X0, [X13, X10,LSL #3]

  (569) 0x46229c CMP	X18, X0

  (569) 0x4622a0 B.GE	4622e4

(570) 0x4622a4 LDR	X1, [X11, X17,LSL #3]

(570) 0x4622a8 LDR	X2, [X9]

(570) 0x4622ac B	4622cc

0x4622b0 HINT	#0

0x4622b4 HINT	#0

0x4622b8 HINT	#0

0x4622bc HINT	#0

(570) 0x4622c0 ADD	X18, X18, #1

(570) 0x4622c4 CMP	X18, X0

(570) 0x4622c8 B.GE	4622e4

(570) 0x4622cc LDR	X3, [X14, X18,LSL #3]

(570) 0x4622d0 TBNZ	X3, #63, 4622c0

(570) 0x4622d4 STR	X3, [X2, X1,LSL #3]

(570) 0x4622d8 ADD	X1, X1, #1

(570) 0x4622dc LDR	X0, [X13, X10,LSL #3]

(570) 0x4622e0 B	4622c0

  (569) 0x4622e4 LDR	X18, [X15, X17,LSL #3]

  (569) 0x4622e8 LDR	X0, [X15, X10,LSL #3]

  (569) 0x4622ec CMP	X18, X0

  (569) 0x4622f0 B.GE	462260

  (569) 0x4622f4 LDR	X17, [X12, X17,LSL #3]

  (569) 0x4622f8 LDR	X1, [X8]

  (569) 0x4622fc B	46230c

    (571) 0x462300 ADD	X18, X18, #1

    (571) 0x462304 CMP	X18, X0

    (571) 0x462308 B.GE	462260

    (571) 0x46230c LDR	X2, [X16, X18,LSL #3]

    (571) 0x462310 TBNZ	X2, #63, 462300

    (571) 0x462314 STR	X2, [X1, X17,LSL #3]

    (571) 0x462318 ADD	X17, X17, #1

    (571) 0x46231c LDR	X0, [X15, X10,LSL #3]

    (571) 0x462320 B	462300

0x462324 LDP	X20, X19, [SP, #224]

0x462328 LDP	X22, X21, [SP, #208]

0x46232c LDP	X24, X23, [SP, #192]

0x462330 LDP	X26, X25, [SP, #176]

0x462334 LDP	X28, X27, [SP, #160]

0x462338 LDP	X29, X30, [SP, #144]

0x46233c ADD	SP, SP, #240

0x462340 RET

0x462344 HINT	#0

0x462348 HINT	#0

0x46234c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_strength.c:246-513
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:246-283,289-302,309-386,392-415,422-445,451-472,480,492-513.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.67 to 0.67 cycles (31.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 20.67 to 5.17 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.67 to 1.00 cycles (20.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 480 bytes. The binary function is storing 216 bytes.

General properties

nb instructions	136
loop length	544
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	6.50	6.50	6.50	6.50	0.50	0.50	0.50	0.50	20.67	20.67	20.67	8.00	8.00
cycles	3.50	3.50	6.50	6.50	6.50	6.50	0.50	0.50	0.50	0.50	20.67	20.67	20.67	8.00	8.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.88
Overall L1	20.67

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.67 cycles. At this rate:

24% of peak load performance is reached (23.23 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
21% of peak store performance is reached (10.45 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 461580

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X0, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X1, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X27, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X20, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X23, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4740 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X9, X11, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP XZR, XZR, [X29, #992]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 462200 <.omp_outlined..2+0xc80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X14, X13, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X3, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D3, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X7, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X20, X19, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X28, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVN X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X26, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X1, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D0, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D1, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X3, X17, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X19, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X3, X19, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X1, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X5, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X3, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X3, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X5, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X19, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X3, X5, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 46169c <.omp_outlined..2+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X21, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X0, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X2, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a5310 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X10, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 462324 <.omp_outlined..2+0xda4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X9, X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X11, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 46226c <.omp_outlined..2+0xcec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	par_strength.c:246-513
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.67 to 1.00 cycles (20.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 480 bytes. The binary function is storing 216 bytes.

General properties

nb instructions	136
loop length	544
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	6.50	6.50	6.50	6.50	0.50	0.50	0.50	0.50	20.67	20.67	20.67	8.00	8.00
cycles	3.50	3.50	6.50	6.50	6.50	6.50	0.50	0.50	0.50	0.50	20.67	20.67	20.67	8.00	8.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.88
Overall L1	20.67

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.67 cycles. At this rate:

24% of peak load performance is reached (23.23 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
21% of peak store performance is reached (10.45 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 461580

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X0, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X1, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X27, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X20, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X23, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4740 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X9, X11, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP XZR, XZR, [X29, #992]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 462200 <.omp_outlined..2+0xc80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X14, X13, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X3, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D3, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X7, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X20, X19, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X28, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVN X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X26, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X1, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D0, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D1, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X3, X17, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X19, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X3, X19, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X1, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X5, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X3, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X3, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X5, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X19, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X3, X5, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 46169c <.omp_outlined..2+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X21, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X0, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X2, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a5310 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X10, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 462324 <.omp_outlined..2+0xda4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X9, X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X11, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 46226c <.omp_outlined..2+0xcec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..2#0x461580–	3.8	1.44
▼Loop 570 - par_strength.c:492-513 - exec–	1.75	0.57
▼Loop 569 - par_strength.c:492-513 - exec–	0.07	0.02
○Loop 571 - par_strength.c:508-513 - exec	0	0
▼Loop 581 - par_strength.c:253-472 - exec–	0	0
▼Loop 582 - par_strength.c:253-472 - exec–	0	0
▼Loop 572 - par_strength.c:253-472 - exec–	0.18	0.06
○Loop 587 - par_strength.c:451-460 - exec	1.76	0.58
○Loop 575 - par_strength.c:324-327 - exec	0.04	0.01
○Loop 573 - par_strength.c:329-332 - exec	0	0
○Loop 583 - par_strength.c:289-294 - exec	0	0
○Loop 592 - par_strength.c:376-386 - exec	0	0
○Loop 579 - par_strength.c:311-314 - exec	0	0
○Loop 591 - par_strength.c:392-402 - exec	0	0
○Loop 593 - par_strength.c:363-373 - exec	0	0
○Loop 586 - par_strength.c:463-472 - exec	0	0
○Loop 580 - par_strength.c:311-314 - exec	0	0
○Loop 590 - par_strength.c:405-415 - exec	0	0
○Loop 595 - par_strength.c:345-347 - exec	0	0
○Loop 578 - par_strength.c:316-319 - exec	0	0
○Loop 574 - par_strength.c:329-332 - exec	0	0
○Loop 576 - par_strength.c:324-327 - exec	0	0.01
○Loop 585 - par_strength.c:270-275 - exec	0	0
○Loop 588 - par_strength.c:436-445 - exec	0	0
○Loop 594 - par_strength.c:351-353 - exec	0	0
○Loop 577 - par_strength.c:316-319 - exec	0	0
○Loop 584 - par_strength.c:278-283 - exec	0	0
○Loop 589 - par_strength.c:424-433 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code