OV - exec - Function .omp_outlined..21#0x4928b0

	Function: .omp_outlined..21#0x4928b0	Module: exec	Source: IJMatrix_parcsr.c:3240-3484 [...]	Coverage: 3.42%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 3240 - 3484

--------------------------------------------------------------------------------

3240: #pragma omp parallel

[...]

3256:          num_threads = hypre_NumActiveThreads();

3257:          my_thread_num = hypre_GetThreadNum();

3258:

3259:          len = nrows/num_threads;

3260:          rest = nrows - len*num_threads;

3261:

3262:          if (my_thread_num < rest)

3263:          {

3264:             ns = my_thread_num*(len+1);

3265:             ne = (my_thread_num+1)*(len+1);

3266:          }

3267:          else

3268:          {

3269:             ns = my_thread_num*len+rest;

3270:             ne = (my_thread_num+1)*len+rest;

3271:          }

3272:

3273:          value_start[my_thread_num] = 0;

3274:          for (ii=ns; ii < ne; ii++)

3275:             value_start[my_thread_num] += ncols[ii];

3276:

3277: #ifdef HYPRE_USING_OPENMP

3278: #pragma omp barrier

3279: #endif

3280:          if (my_thread_num == 0)

3281:          {

3282:             for (i=0; i < max_num_threads; i++)

3283:                value_start[i+1] += value_start[i];

3284:          }

3285: #ifdef HYPRE_USING_OPENMP

3286: #pragma omp barrier

3287: #endif

3288:          indx = 0;

3289:          if (my_thread_num)

3290:             indx = value_start[my_thread_num-1];

3291:          for (ii=ns; ii < ne; ii++)

3292:          {

3293:             row = rows[ii];

3294:             n = ncols[ii];

3295:             /* processor owns the row */

3296:             if (row >= row_partitioning[pstart] && row < row_partitioning[pstart+1])

3297:             {

3298:                row_local = row - row_partitioning[pstart];

3299:                /* compute local row number */

3300:                if (need_aux)

3301:                {

3302:                   local_j = aux_j[row_local];

3303:                   local_data = aux_data[row_local];

3304:    	          space = row_space[row_local];

3305:    	          old_size = row_length[row_local];

3306:    	          size = space - old_size;

3307:    	          if (size < n)

3308:       	          {

3309:       	             size = n - size;

3310:       	             tmp_j = hypre_CTAlloc(HYPRE_Int,size);

3311:       	             tmp_data = hypre_CTAlloc(HYPRE_Complex,size);

3312:       	          }

3313:       	          tmp_indx = 0;

3314:       	          not_found = 1;

3315:       	          size = old_size;

3316:                   for (i=0; i < n; i++)

3317:       	          {

3318:       	             for (j=0; j < old_size; j++)

3319:       	             {

3320:       	                if (local_j[j] == cols[indx])

3321:       	                {

3322:                            local_data[j] = values[indx];

[...]

3329:       	                if (size < space)

3330:       	                {

3331:       	                   local_j[size] = cols[indx];

3332:       	                   local_data[size++] = values[indx];

3333:       	                }

3334:       	                else

3335:       	                {

3336:       	                   tmp_j[tmp_indx] = cols[indx];

3337:       	                   tmp_data[tmp_indx++] = values[indx];

3338:       	                }

3339:       	             }

3340:       	             not_found = 1;

3341:         	     indx++;

3342:       	          }

3343:

3344:                   row_length[row_local] = size+tmp_indx;

3345:

3346:                   if (tmp_indx)

3347:                   {

3348:    	             aux_j[row_local] = hypre_TReAlloc(aux_j[row_local],HYPRE_Int,

3349:                                                     size+tmp_indx);

3350:    	             aux_data[row_local] = hypre_TReAlloc(aux_data[row_local],

3351:                                                        HYPRE_Complex,size+tmp_indx);

3352:                      row_space[row_local] = size+tmp_indx;

[...]

3359:    	          for (i=0; i < tmp_indx; i++)

3360:    	          {

3361:    	             local_j[cnt] = tmp_j[i];

3362:    	             local_data[cnt++] = tmp_data[i];

3363: 	          }

3364:

3365: 	          if (tmp_j)

3366: 	          {

3367: 	             hypre_TFree(tmp_j);

3368: 	             hypre_TFree(tmp_data);

[...]

3376: 	          offd_indx = hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local];

3377: 	          diag_indx = hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local];

[...]

3383:   	          for (i=0; i < n; i++)

3384: 	          {

3385: 	             if (cols[indx] < col_0 || cols[indx] > col_n)

3386:                      /* insert into offd */

3387: 	             {

3388: 	                for (j=offd_i[row_local]; j < offd_indx; j++)

3389: 	                {

3390: 		           if (offd_j[j] == cols[indx])

[...]

3399: 	                   if (cnt_offd < offd_space)

3400: 	                   {

3401: 	                      offd_j[cnt_offd] = cols[indx];

3402: 	                      offd_data[cnt_offd++] = values[indx];

3403: 	                   }

3404: 	                   else

3405: 	 	           {

3406:                               hypre_error(HYPRE_ERROR_GENERIC);

3407: #ifdef HYPRE_USING_OPENMP

3408: #pragma omp atomic

3409: #endif

3410:                               error_flag++;

3411: 	    	              if (print_level)

[...]

3422: 	                for (j=diag_i[row_local]; j < diag_indx; j++)

3423: 	                {

3424: 		           if (diag_j[j] == cols[indx])

[...]

3433: 	                   if (cnt_diag < diag_space)

3434: 	                   {

3435: 	                      diag_j[cnt_diag] = cols[indx];

3436: 	                      diag_data[cnt_diag++] = values[indx];

3437: 	                   }

3438: 	                   else

3439: 	 	           {

3440:                               hypre_error(HYPRE_ERROR_GENERIC);

3441: #ifdef HYPRE_USING_OPENMP

3442: #pragma omp atomic

3443: #endif

3444:                               error_flag++;

3445: 	    	              if (print_level)

[...]

3454: 	             indx++;

3455: 	          }

3456:

3457:                   hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local] = cnt_diag;

3458:                   hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local] = cnt_offd;

[...]

3466:                indx +=  n;

3467:    	       if (aux_matrix)

3468:                {

3469:                   col_indx = 0;

3470:                   for (i=0; i < off_proc_i_indx; i=i+2)

3471:                   {

3472: 	             row_len = off_proc_i[i+1];

3473: 	             if (off_proc_i[i] == row)

3474: 		     {

3475: 		        for (j=0; j < n; j++)

3476: 		        {

3477: 			   cnt1 = col_indx;

3478: 			   for (k=0; k < row_len; k++)

3479: 			   {

3480: 			      if (off_proc_j[cnt1] == cols[j])

3481: 			      {

3482:                                  off_proc_j[cnt1++] = -1;

3483:                		         /*cancel_indx++;*/

3484: 	                         offproc_cnt[my_thread_num]++;

0x4928b0 SUB	SP, SP, #336

0x4928b4 STP	X29, X30, [SP, #240]

0x4928b8 STP	X28, X27, [SP, #256]

0x4928bc STP	X26, X25, [SP, #272]

0x4928c0 STP	X24, X23, [SP, #288]

0x4928c4 STP	X22, X21, [SP, #304]

0x4928c8 STP	X20, X19, [SP, #320]

0x4928cc ADD	X29, SP, #240

0x4928d0 ORR	X28, XZR, X7

0x4928d4 STUR	X6, [X29, #448]

0x4928d8 ORR	X24, XZR, X5

0x4928dc ORR	X21, XZR, X4

0x4928e0 ORR	X23, XZR, X3

0x4928e4 ORR	X26, XZR, X2

0x4928e8 ORR	X25, XZR, X0

0x4928ec BL	4a4700

0x4928f0 ORR	X27, XZR, X0

0x4928f4 BL	4a4720

0x4928f8 LDR	X8, [X26]

0x4928fc ADD	X10, X0, #1

0x492900 ORR	X22, XZR, X0

0x492904 SDIV	X9, X8, X27

0x492908 MSUB	X8, X9, X27, X8

0x49290c CMP	X0, X8

0x492910 MADD	X11, X9, X0, X8

0x492914 MADD	X8, X9, X10, X8

0x492918 ADD	X9, X9, #1

0x49291c MADD	X12, X9, X0, XZR

0x492920 MADD	X9, X9, X10, XZR

0x492924 CSEL	X13, X8, X9, #10

0x492928 LDR	X8, [X23]

0x49292c CSEL	X19, X11, X12, #10

0x492930 CMP	X19, X13

0x492934 STR	XZR, [X8, X0,LSL #3]

0x492938 B.GE	492960

0x49293c LDR	X10, [X21]

0x492940 ORR	X9, XZR, XZR

0x492944 ORR	X11, XZR, X19

(542) 0x492948 LDR	X12, [X10, X11,LSL #3]

(542) 0x49294c ADD	X11, X11, #1

(542) 0x492950 CMP	X11, X13

(542) 0x492954 ADD	X9, X12, X9

(542) 0x492958 STR	X9, [X8, X22,LSL #3]

(542) 0x49295c B.LT	492948

0x492960 LDR	W25, [X25]

0x492964 ADRP	X0,

0x492968 ADD	X0, X0, #3752

0x49296c STUR	X13, [X29, #424]

0x492970 ORR	W1, WZR, W25

0x492974 BL	40f4b0

0x492978 CBNZ	X22, 4929bc

0x49297c LDR	X8, [X24]

0x492980 CMP	X8, #1

0x492984 B.LT	4929bc

0x492988 LDR	X8, [X23]

0x49298c ORR	X10, XZR, XZR

0x492990 LDR	X9, [X8], #8

0x492994 HINT	#0

0x492998 HINT	#0

0x49299c HINT	#0

(541) 0x4929a0 LDR	X11, [X8, X10,LSL #3]

(541) 0x4929a4 ADD	X9, X11, X9

(541) 0x4929a8 STR	X9, [X8, X10,LSL #3]

(541) 0x4929ac ADD	X10, X10, #1

(541) 0x4929b0 LDR	X11, [X24]

(541) 0x4929b4 CMP	X10, X11

(541) 0x4929b8 B.LT	4929a0

0x4929bc ORR	W1, WZR, W25

0x4929c0 ADRP	X0,

0x4929c4 ADD	X0, X0, #3776

0x4929c8 BL	40f4b0

0x4929cc CBZ	X22, 4929f4

0x4929d0 LDR	X8, [X23]

0x4929d4 ADD	X8, X8, X22,LSL #3

0x4929d8 LDUR	X24, [X8, #504]

0x4929dc LDUR	X7, [X29, #424]

0x4929e0 LDUR	X13, [X29, #448]

0x4929e4 ORR	X30, XZR, X19

0x4929e8 CMP	X19, X7

0x4929ec B.LT	492a0c

0x4929f0 B	493208

0x4929f4 ORR	X24, XZR, XZR

0x4929f8 LDUR	X7, [X29, #424]

0x4929fc LDUR	X13, [X29, #448]

0x492a00 ORR	X30, XZR, X19

0x492a04 CMP	X19, X7

0x492a08 B.GE	493208

0x492a0c LDR	X8, [X29, #256]

0x492a10 LDR	X9, [X29, #192]

0x492a14 LDP	X26, X19, [X29, #264]

0x492a18 MOVN	X27, #0

0x492a1c STUR	XZR, [X29, #464]

0x492a20 STUR	X21, [X29, #400]

0x492a24 STP	X28, X8, [SP, #104]

0x492a28 LDP	X8, X5, [X29, #240]

0x492a2c STR	X26, [SP, #120]

0x492a30 STR	X8, [SP, #56]

0x492a34 LDR	X8, [X29, #232]

0x492a38 STR	X8, [SP, #48]

0x492a3c LDR	X8, [X29, #224]

0x492a40 STR	X8, [SP, #8]

0x492a44 LDR	X8, [X29, #216]

0x492a48 STR	X8, [SP]

0x492a4c LDR	X8, [X29, #208]

0x492a50 STR	X8, [SP, #40]

0x492a54 LDR	X8, [X29, #200]

0x492a58 STR	X8, [SP, #32]

0x492a5c LDR	X8, [X29, #184]

0x492a60 STP	X8, X9, [X29, #1000]

0x492a64 LDR	X8, [X29, #176]

0x492a68 LDR	X9, [X29, #112]

0x492a6c STR	X8, [SP, #24]

0x492a70 LDR	X8, [X29, #168]

0x492a74 STR	X8, [SP, #16]

0x492a78 LDP	X8, X11, [X29, #152]

0x492a7c STR	X8, [SP, #80]

0x492a80 LDP	X8, X6, [X29, #136]

0x492a84 STUR	X11, [X29, #456]

0x492a88 STUR	X8, [X29, #440]

0x492a8c LDR	X8, [X29, #128]

0x492a90 STP	X5, X6, [X29, #984]

0x492a94 STR	X8, [SP, #96]

0x492a98 LDR	X8, [X29, #120]

0x492a9c STR	X8, [SP, #88]

0x492aa0 LDP	X23, X8, [X29, #96]

0x492aa4 STP	X8, X9, [X29, #920]

0x492aa8 STR	X23, [SP, #72]

0x492aac B	492ad4

0x492ab0 HINT	#0

0x492ab4 HINT	#0

0x492ab8 HINT	#0

0x492abc HINT	#0

      (527) 0x492ac0 LDUR	X11, [X29, #456]

      (527) 0x492ac4 ORR	X13, XZR, X3

      (527) 0x492ac8 ADD	X30, X30, #1

      (527) 0x492acc CMP	X30, X7

      (527) 0x492ad0 B.GE	493208

      (527) 0x492ad4 LDR	X8, [X13]

      (527) 0x492ad8 LDR	X9, [X23]

      (527) 0x492adc LDR	X25, [X8, X30,LSL #3]

      (527) 0x492ae0 LDR	X8, [X21]

      (527) 0x492ae4 LDR	X20, [X8, X30,LSL #3]

      (527) 0x492ae8 LDR	X8, [X28]

      (527) 0x492aec LDR	X10, [X8, X9,LSL #3]

      (527) 0x492af0 SUBS	X16, X25, X10

      (527) 0x492af4 B.LT	492bc0

      (527) 0x492af8 ADD	X8, X8, X9,LSL #3

      (527) 0x492afc LDR	X8, [X8, #8]

      (527) 0x492b00 CMP	X25, X8

      (527) 0x492b04 B.GE	492bc0

      (527) 0x492b08 LDUR	X8, [X29, #408]

      (527) 0x492b0c LDR	X8, [X8]

      (527) 0x492b10 CBZ	X8, 492d18

    (535) 0x492b14 LDUR	X8, [X29, #416]

    (535) 0x492b18 STUR	X30, [X29, #432]

    (535) 0x492b1c LDR	X8, [X8]

    (535) 0x492b20 LDR	X23, [X8, X16,LSL #3]

    (535) 0x492b24 LDR	X8, [SP, #88]

    (535) 0x492b28 LDR	X8, [X8]

    (535) 0x492b2c LDR	X26, [X8, X16,LSL #3]

    (535) 0x492b30 LDR	X8, [SP, #96]

    (535) 0x492b34 LDR	X8, [X8]

    (535) 0x492b38 LDR	X17, [X8, X16,LSL #3]

    (535) 0x492b3c LDUR	X8, [X29, #440]

    (535) 0x492b40 LDR	X8, [X8]

    (535) 0x492b44 LDR	X25, [X8, X16,LSL #3]

    (535) 0x492b48 SUB	X8, X17, X25

    (535) 0x492b4c SUBS	X21, X20, X8

    (535) 0x492b50 B.LE	492e7c

    (535) 0x492b54 ORR	X0, XZR, X21

    (535) 0x492b58 MOVZ	W1, #8

    (535) 0x492b5c STUR	X16, [X29, #464]

    (535) 0x492b60 STR	X17, [SP, #64]

    (535) 0x492b64 BL	4a2570

    (535) 0x492b68 ORR	X28, XZR, X0

    (535) 0x492b6c ORR	X0, XZR, X21

    (535) 0x492b70 MOVZ	W1, #8

    (535) 0x492b74 BL	4a2570

    (535) 0x492b78 LDR	X17, [SP, #64]

    (535) 0x492b7c ORR	X18, XZR, X28

    (535) 0x492b80 LDUR	X16, [X29, #464]

    (535) 0x492b84 LDR	X28, [SP, #104]

    (535) 0x492b88 LDUR	X6, [X29, #480]

    (535) 0x492b8c CMP	X20, #0

    (535) 0x492b90 STUR	X0, [X29, #464]

    (535) 0x492b94 B.GT	492e90

    (535) 0x492b98 LDP	X8, X13, [X29, #952]

    (535) 0x492b9c LDR	X8, [X8]

    (535) 0x492ba0 STR	X25, [X8, X16,LSL #3]

    (535) 0x492ba4 LDUR	X21, [X29, #400]

    (535) 0x492ba8 LDR	X26, [SP, #120]

    (535) 0x492bac LDR	X23, [SP, #72]

    (535) 0x492bb0 CBNZ	X18, 49311c

    (535) 0x492bb4 B	49313c

0x492bb8 HINT	#0

0x492bbc HINT	#0

      (527) 0x492bc0 LDR	X8, [X11]

      (527) 0x492bc4 LDR	X12, [X5]

      (527) 0x492bc8 ADD	X24, X20, X24

      (527) 0x492bcc CMP	X8, #0

      (527) 0x492bd0 CCMP	X12, #1, #8, #1

      (527) 0x492bd4 B.LT	492ac8

      (527) 0x492bd8 CMP	X20, #1

      (527) 0x492bdc B.LT	492ac8

      (527) 0x492be0 LDR	X10, [SP, #112]

      (527) 0x492be4 ORR	X3, XZR, X13

      (527) 0x492be8 ORR	X8, XZR, XZR

      (527) 0x492bec LDR	X10, [X10]

      (527) 0x492bf0 ORR	X9, XZR, XZR

      (527) 0x492bf4 B	492c14

0x492bf8 HINT	#0

0x492bfc HINT	#0

        (528) 0x492c00 LDR	X12, [X5]

        (528) 0x492c04 ADD	X8, X11, X8

        (528) 0x492c08 ADD	X9, X9, #2

        (528) 0x492c0c CMP	X9, X12

        (528) 0x492c10 B.GE	492ac0

        (528) 0x492c14 UBFM	X13, X9, #61, #60

        (528) 0x492c18 ORR	X11, X13, #4157

        (528) 0x492c1c LDR	X13, [X10, X13]

        (528) 0x492c20 LDR	X11, [X10, X11]

        (528) 0x492c24 CMP	X13, X25

        (528) 0x492c28 B.NE	492c04

        (528) 0x492c2c CMP	X11, #1

        (528) 0x492c30 B.LT	492c04

        (528) 0x492c34 LDR	X13, [X26]

        (528) 0x492c38 LDR	X14, [X6]

        (528) 0x492c3c ORR	X12, XZR, XZR

        (528) 0x492c40 AND	X15, X11, #8127

        (528) 0x492c44 B	492c54

          (529) 0x492c48 ADD	X12, X12, #1

          (529) 0x492c4c CMP	X12, X20

          (529) 0x492c50 B.EQ	492c00

          (529) 0x492c54 LDR	X16, [X19]

          (529) 0x492c58 ORR	X17, XZR, X8

          (529) 0x492c5c CMP	X11, #1

          (529) 0x492c60 B.NE	492c8c

          (529) 0x492c64 TBZ	W11, #0, 492c48

          (529) 0x492c68 LDR	X18, [X13, X17,LSL #3]

          (529) 0x492c6c LDR	X0, [X14, X12,LSL #3]

          (529) 0x492c70 CMP	X18, X0

          (529) 0x492c74 B.NE	492c48

          (529) 0x492c78 STR	X27, [X13, X17,LSL #3]

          (529) 0x492c7c LDR	X17, [X16, X22,LSL #3]

          (529) 0x492c80 ADD	X17, X17, #1

          (529) 0x492c84 STR	X17, [X16, X22,LSL #3]

          (529) 0x492c88 B	492c48

          (529) 0x492c8c ORR	X18, XZR, X15

          (529) 0x492c90 ORR	X17, XZR, X8

          (529) 0x492c94 B	492cac

0x492c98 HINT	#0

0x492c9c HINT	#0

            (530) 0x492ca0 ADD	X17, X17, #2

            (530) 0x492ca4 SUBS	X18, X18, #2

            (530) 0x492ca8 B.EQ	492c64

            (530) 0x492cac LDR	X0, [X13, X17,LSL #3]

            (530) 0x492cb0 LDR	X1, [X14, X12,LSL #3]

            (530) 0x492cb4 CMP	X0, X1

            (530) 0x492cb8 B.EQ	492ce0

            (530) 0x492cbc ADD	X0, X13, X17,LSL #3

            (530) 0x492cc0 LDR	X2, [X14, X12,LSL #3]

            (530) 0x492cc4 LDR	X1, [X0, #8]

            (530) 0x492cc8 CMP	X1, X2

            (530) 0x492ccc B.NE	492ca0

            (530) 0x492cd0 B	492d04

0x492cd4 HINT	#0

0x492cd8 HINT	#0

0x492cdc HINT	#0

            (530) 0x492ce0 STR	X27, [X13, X17,LSL #3]

            (530) 0x492ce4 LDR	X0, [X16, X22,LSL #3]

            (530) 0x492ce8 ADD	X0, X0, #1

            (530) 0x492cec STR	X0, [X16, X22,LSL #3]

            (530) 0x492cf0 ADD	X0, X13, X17,LSL #3

            (530) 0x492cf4 LDR	X2, [X14, X12,LSL #3]

            (530) 0x492cf8 LDR	X1, [X0, #8]

            (530) 0x492cfc CMP	X1, X2

            (530) 0x492d00 B.NE	492ca0

            (530) 0x492d04 STR	X27, [X0, #8]

            (530) 0x492d08 LDR	X0, [X16, X22,LSL #3]

            (530) 0x492d0c ADD	X0, X0, #1

            (530) 0x492d10 STR	X0, [X16, X22,LSL #3]

            (530) 0x492d14 B	492ca0

      (527) 0x492d18 LDR	X8, [X11]

      (527) 0x492d1c UBFM	X12, X16, #61, #60

      (527) 0x492d20 CMP	X20, #1

      (527) 0x492d24 LDP	X10, X9, [X8, #56]

      (527) 0x492d28 LDR	X8, [X9, X12]

      (527) 0x492d2c LDR	X9, [X10, X12]

      (527) 0x492d30 B.LT	493038

      (527) 0x492d34 LDP	X11, X13, [SP, #16]

      (527) 0x492d38 ORR	X28, XZR, X16

      (527) 0x492d3c LDP	X16, X18, [SP, #48]

      (527) 0x492d40 LDR	X17, [SP, #80]

      (527) 0x492d44 ADD	X14, X12, #8

      (527) 0x492d48 ORR	X10, XZR, XZR

      (527) 0x492d4c ORR	X21, XZR, X8

      (527) 0x492d50 LDR	X15, [X6]

      (527) 0x492d54 LDP	X0, X1, [SP, #32]

      (527) 0x492d58 ORR	X26, XZR, X9

      (527) 0x492d5c LDR	X11, [X11]

      (527) 0x492d60 LDR	X13, [X13]

      (527) 0x492d64 LDR	X16, [X16]

      (527) 0x492d68 LDR	X17, [X17]

      (527) 0x492d6c LDR	X18, [X18]

      (527) 0x492d70 LDR	X0, [X0]

      (527) 0x492d74 LDR	X1, [X1]

      (527) 0x492d78 LDR	X12, [X11, X14]

      (527) 0x492d7c LDR	X14, [X13, X14]

      (527) 0x492d80 B	492da0

        (531) 0x492d84 LDR	D0, [X17, X24,LSL #3]

        (531) 0x492d88 LDP	X5, X6, [X29, #984]

        (531) 0x492d8c STR	D0, [X3]

        (531) 0x492d90 ADD	X10, X10, #1

        (531) 0x492d94 ADD	X24, X24, #1

        (531) 0x492d98 CMP	X10, X20

        (531) 0x492d9c B.EQ	493044

        (531) 0x492da0 LDP	X3, X4, [X29, #1000]

        (531) 0x492da4 LDR	X2, [X15, X24,LSL #3]

        (531) 0x492da8 LDR	X3, [X3]

        (531) 0x492dac LDR	X4, [X4]

        (531) 0x492db0 CMP	X2, X3

        (531) 0x492db4 CCMP	X2, X4, #0, #10

        (531) 0x492db8 B.LE	492e20

        (531) 0x492dbc LDR	X4, [X13, X28,LSL #3]

        (531) 0x492dc0 CMP	X4, X8

        (531) 0x492dc4 B.GE	492e00

        (531) 0x492dc8 UBFM	X5, X4, #61, #60

        (531) 0x492dcc SUB	X4, X8, X4

        (531) 0x492dd0 ADD	X3, X1, X5

        (531) 0x492dd4 ADD	X5, X0, X5

        (531) 0x492dd8 HINT	#0

        (531) 0x492ddc HINT	#0

          (533) 0x492de0 LDR	X6, [X5]

          (533) 0x492de4 CMP	X6, X2

          (533) 0x492de8 B.EQ	492d84

          (533) 0x492dec ADD	X3, X3, #8

          (533) 0x492df0 SUBS	X4, X4, #1

          (533) 0x492df4 ADD	X5, X5, #8

          (533) 0x492df8 B.NE	492de0

        (531) 0x492dfc LDP	X5, X6, [X29, #984]

        (531) 0x492e00 CMP	X21, X14

        (531) 0x492e04 B.GE	49314c

        (531) 0x492e08 LDR	D0, [X17, X24,LSL #3]

        (531) 0x492e0c STR	X2, [X0, X21,LSL #3]

        (531) 0x492e10 STR	D0, [X1, X21,LSL #3]

        (531) 0x492e14 ADD	X21, X21, #1

        (531) 0x492e18 B	492d90

0x492e1c HINT	#0

        (531) 0x492e20 LDR	X4, [X11, X28,LSL #3]

        (531) 0x492e24 CMP	X4, X9

        (531) 0x492e28 B.GE	492e60

        (531) 0x492e2c UBFM	X5, X4, #61, #60

        (531) 0x492e30 SUB	X4, X9, X4

        (531) 0x492e34 ADD	X3, X18, X5

        (531) 0x492e38 ADD	X5, X16, X5

        (531) 0x492e3c HINT	#0

          (532) 0x492e40 LDR	X6, [X5]

          (532) 0x492e44 CMP	X6, X2

          (532) 0x492e48 B.EQ	492d84

          (532) 0x492e4c ADD	X3, X3, #8

          (532) 0x492e50 SUBS	X4, X4, #1

          (532) 0x492e54 ADD	X5, X5, #8

          (532) 0x492e58 B.NE	492e40

        (531) 0x492e5c LDP	X5, X6, [X29, #984]

        (531) 0x492e60 CMP	X26, X12

        (531) 0x492e64 B.GE	4931c8

        (531) 0x492e68 LDR	D0, [X17, X24,LSL #3]

        (531) 0x492e6c STR	X2, [X16, X26,LSL #3]

        (531) 0x492e70 STR	D0, [X18, X26,LSL #3]

        (531) 0x492e74 ADD	X26, X26, #1

        (531) 0x492e78 B	492d90

    (535) 0x492e7c LDUR	X0, [X29, #464]

    (535) 0x492e80 ORR	X18, XZR, XZR

    (535) 0x492e84 CMP	X20, #0

    (535) 0x492e88 STUR	X0, [X29, #464]

    (535) 0x492e8c B.LE	492b98

  (536) 0x492e90 LDR	X10, [SP, #80]

  (536) 0x492e94 LDR	X9, [X6]

  (536) 0x492e98 ORR	X21, XZR, XZR

  (536) 0x492e9c ORR	X8, XZR, XZR

  (536) 0x492ea0 LDR	X10, [X10]

  (536) 0x492ea4 ORR	X28, XZR, X25

  (536) 0x492ea8 B	492ecc

  (536) 0x492eac LDR	D0, [X10, X24,LSL #3]

  (536) 0x492eb0 STR	X11, [X18, X21,LSL #3]

  (536) 0x492eb4 STR	D0, [X0, X21,LSL #3]

  (536) 0x492eb8 ADD	X21, X21, #1

  (536) 0x492ebc ADD	X8, X8, #1

  (536) 0x492ec0 ADD	X24, X24, #1

  (536) 0x492ec4 CMP	X8, X20

  (536) 0x492ec8 B.EQ	492f2c

  (536) 0x492ecc LDR	X11, [X9, X24,LSL #3]

  (536) 0x492ed0 CMP	X25, #1

  (536) 0x492ed4 B.LT	492f00

(537) 0x492ed8 ORR	X13, XZR, X23

(537) 0x492edc ORR	X14, XZR, X25

(537) 0x492ee0 ORR	X12, XZR, X26

  (538) 0x492ee4 LDR	X15, [X13]

  (538) 0x492ee8 CMP	X15, X11

  (538) 0x492eec B.EQ	492f20

  (538) 0x492ef0 ADD	X12, X12, #8

  (538) 0x492ef4 SUBS	X14, X14, #1

  (538) 0x492ef8 ADD	X13, X13, #8

  (538) 0x492efc B.NE	492ee4

  (536) 0x492f00 CMP	X28, X17

  (536) 0x492f04 B.GE	492eac

  (536) 0x492f08 LDR	D0, [X10, X24,LSL #3]

  (536) 0x492f0c STR	X11, [X23, X28,LSL #3]

  (536) 0x492f10 STR	D0, [X26, X28,LSL #3]

  (536) 0x492f14 ADD	X28, X28, #1

  (536) 0x492f18 B	492ebc

0x492f1c HINT	#0

(537) 0x492f20 LDR	D0, [X10, X24,LSL #3]

(537) 0x492f24 STR	D0, [X12]

(537) 0x492f28 B	492ebc

  (536) 0x492f2c LDP	X8, X13, [X29, #952]

  (536) 0x492f30 ADD	X20, X28, X21

  (536) 0x492f34 LDR	X8, [X8]

  (536) 0x492f38 STR	X20, [X8, X16,LSL #3]

  (536) 0x492f3c CBZ	X21, 493020

  (536) 0x492f40 LDUR	X25, [X29, #416]

  (536) 0x492f44 UBFM	X26, X20, #61, #60

  (536) 0x492f48 STR	X18, [SP, #64]

  (536) 0x492f4c ORR	X23, XZR, X16

  (536) 0x492f50 ORR	X1, XZR, X26

  (536) 0x492f54 LDR	X8, [X25]

  (536) 0x492f58 LDR	X0, [X8, X16,LSL #3]

  (536) 0x492f5c BL	4a25e0

  (536) 0x492f60 LDR	X8, [X25]

  (536) 0x492f64 LDR	X25, [SP, #88]

  (536) 0x492f68 ORR	X1, XZR, X26

  (536) 0x492f6c STR	X0, [X8, X23,LSL #3]

  (536) 0x492f70 LDR	X8, [X25]

  (536) 0x492f74 LDR	X0, [X8, X23,LSL #3]

  (536) 0x492f78 BL	4a25e0

  (536) 0x492f7c LDR	X8, [X25]

  (536) 0x492f80 CMP	X21, #1

  (536) 0x492f84 STR	X0, [X8, X23,LSL #3]

  (536) 0x492f88 LDR	X8, [SP, #96]

  (536) 0x492f8c LDR	X8, [X8]

  (536) 0x492f90 STR	X20, [X8, X23,LSL #3]

  (536) 0x492f94 B.LT	49304c

  (536) 0x492f98 LDUR	X8, [X29, #416]

  (536) 0x492f9c ORR	X9, XZR, X25

  (536) 0x492fa0 LDR	X9, [X25]

  (536) 0x492fa4 LDR	X26, [SP, #120]

  (536) 0x492fa8 CMP	X21, #4

  (536) 0x492fac LDUR	X17, [X29, #464]

  (536) 0x492fb0 LDR	X18, [SP, #64]

  (536) 0x492fb4 LDR	X8, [X8]

  (536) 0x492fb8 LDR	X9, [X9, X23,LSL #3]

  (536) 0x492fbc LDR	X8, [X8, X23,LSL #3]

  (536) 0x492fc0 B.CS	49306c

  (536) 0x492fc4 ORR	X11, XZR, XZR

  (536) 0x492fc8 LDR	X23, [SP, #72]

  (536) 0x492fcc AND	X10, X21, #4160

  (536) 0x492fd0 CBZ	X10, 493110

  (536) 0x492fd4 UBFM	X12, X28, #61, #60

  (536) 0x492fd8 LDUR	X21, [X29, #400]

  (536) 0x492fdc ADD	X9, X9, X12

  (536) 0x492fe0 ADD	X8, X8, X12

  (536) 0x492fe4 UBFM	X12, X11, #61, #60

  (536) 0x492fe8 ADD	X11, X17, X12

  (536) 0x492fec ADD	X12, X18, X12

  (536) 0x492ff0 HINT	#0

  (536) 0x492ff4 HINT	#0

  (536) 0x492ff8 HINT	#0

  (536) 0x492ffc HINT	#0

    (540) 0x493000 LDR	D0, [X11], #8

    (540) 0x493004 LDR	X13, [X12], #8

    (540) 0x493008 SUBS	X10, X10, #1

    (540) 0x49300c STR	X13, [X8], #8

    (540) 0x493010 STR	D0, [X9], #8

    (540) 0x493014 B.NE	493000

  (536) 0x493018 LDR	X28, [SP, #104]

  (536) 0x49301c B	493118

  (536) 0x493020 LDR	X28, [SP, #104]

  (536) 0x493024 LDUR	X21, [X29, #400]

  (536) 0x493028 LDR	X26, [SP, #120]

  (536) 0x49302c LDR	X23, [SP, #72]

  (536) 0x493030 CBNZ	X18, 49311c

  (536) 0x493034 B	49313c

      (527) 0x493038 ORR	X26, XZR, X9

      (527) 0x49303c ORR	X21, XZR, X8

      (527) 0x493040 B	4931ac

      (527) 0x493044 LDUR	X11, [X29, #456]

      (527) 0x493048 B	4931a0

  (536) 0x49304c LDR	X28, [SP, #104]

  (536) 0x493050 LDUR	X21, [X29, #400]

  (536) 0x493054 LDR	X26, [SP, #120]

  (536) 0x493058 LDUR	X6, [X29, #480]

  (536) 0x49305c LDP	X18, X23, [SP, #64]

  (536) 0x493060 LDUR	X13, [X29, #448]

  (536) 0x493064 CBNZ	X18, 49311c

  (536) 0x493068 B	49313c

  (536) 0x49306c UBFM	X15, X28, #61, #60

  (536) 0x493070 AND	X11, X21, #8062

  (536) 0x493074 ORR	X10, XZR, XZR

  (536) 0x493078 ADD	X12, X17, #16

  (536) 0x49307c ADD	X13, X18, #16

  (536) 0x493080 ADD	X14, X8, X15

  (536) 0x493084 ADD	X15, X9, X15

  (536) 0x493088 SUB	X11, XZR, X11

  (536) 0x49308c ADD	X14, X14, #16

  (536) 0x493090 ADD	X15, X15, #16

  (536) 0x493094 HINT	#0

  (536) 0x493098 HINT	#0

  (536) 0x49309c HINT	#0

    (539) 0x4930a0 LDUR	D0, [X12, #496]

    (539) 0x4930a4 LDUR	X16, [X13, #496]

    (539) 0x4930a8 SUB	X10, X10, #4

    (539) 0x4930ac CMP	X11, X10

    (539) 0x4930b0 STUR	X16, [X14, #496]

    (539) 0x4930b4 LDUR	X16, [X13, #504]

    (539) 0x4930b8 STUR	D0, [X15, #496]

    (539) 0x4930bc LDUR	D0, [X12, #504]

    (539) 0x4930c0 STUR	X16, [X14, #504]

    (539) 0x4930c4 LDR	X16, [X13]

    (539) 0x4930c8 STUR	D0, [X15, #504]

    (539) 0x4930cc LDR	D0, [X12]

    (539) 0x4930d0 STR	X16, [X14]

    (539) 0x4930d4 LDR	X16, [X13, #8]

    (539) 0x4930d8 ADD	X13, X13, #32

    (539) 0x4930dc STR	X16, [X14, #8]

    (539) 0x4930e0 ADD	X14, X14, #32

    (539) 0x4930e4 STR	D0, [X15]

    (539) 0x4930e8 LDR	D0, [X12, #8]

    (539) 0x4930ec ADD	X12, X12, #32

    (539) 0x4930f0 STR	D0, [X15, #8]

    (539) 0x4930f4 ADD	X15, X15, #32

    (539) 0x4930f8 B.NE	4930a0

  (536) 0x4930fc SUB	X11, XZR, X10

  (536) 0x493100 SUB	X28, X28, X10

  (536) 0x493104 LDR	X23, [SP, #72]

  (536) 0x493108 AND	X10, X21, #4160

  (536) 0x49310c CBNZ	X10, 492fd4

  (536) 0x493110 LDR	X28, [SP, #104]

  (536) 0x493114 LDUR	X21, [X29, #400]

  (536) 0x493118 LDUR	X13, [X29, #448]

    (534) 0x49311c ORR	X0, XZR, X18

    (534) 0x493120 ORR	X20, XZR, X13

    (534) 0x493124 BL	4a2670

  (536) 0x493128 LDUR	X0, [X29, #464]

  (536) 0x49312c BL	4a2670

  (536) 0x493130 LDUR	X6, [X29, #480]

  (536) 0x493134 ORR	X13, XZR, X20

  (536) 0x493138 STUR	XZR, [X29, #464]

    (535) 0x49313c LDP	X7, X30, [X29, #936]

    (535) 0x493140 LDUR	X5, [X29, #472]

    (535) 0x493144 LDUR	X11, [X29, #456]

    (535) 0x493148 B	492ac8

      (527) 0x49314c ORR	X3, XZR, XZR

      (527) 0x493150 ADRP	X0,

      (527) 0x493154 ADD	X0, X0, #2387

      (527) 0x493158 MOVZ	W1, #3406

      (527) 0x49315c MOVZ	W2, #1

      (527) 0x493160 ORR	X20, XZR, X30

      (527) 0x493164 BL	4a5070

      (527) 0x493168 LDR	X8, [SP]

      (527) 0x49316c MOVZ	W9, #1

      (527) 0x493170 ADRP	X0,

      (527) 0x493174 ADD	X0, X0, #2723

      (527) 0x493178 LDADD	X9, X8, [X8]

      (527) 0x49317c LDR	X8, [SP, #8]

      (527) 0x493180 LDR	X8, [X8]

      (527) 0x493184 CBZ	X8, 493190

      (527) 0x493188 ORR	X1, XZR, X25

      (527) 0x49318c BL	4a2780

      (527) 0x493190 LDUR	X7, [X29, #424]

      (527) 0x493194 LDP	X5, X6, [X29, #984]

      (527) 0x493198 LDUR	X11, [X29, #456]

      (527) 0x49319c ORR	X30, XZR, X20

      (527) 0x4931a0 LDUR	X13, [X29, #448]

      (527) 0x4931a4 ORR	X16, XZR, X28

      (527) 0x4931a8 LDR	X28, [SP, #104]

      (527) 0x4931ac LDR	X8, [X11]

      (527) 0x4931b0 LDP	X9, X8, [X8, #56]

      (527) 0x4931b4 STR	X26, [X9, X16,LSL #3]

      (527) 0x4931b8 STR	X21, [X8, X16,LSL #3]

      (527) 0x4931bc LDUR	X21, [X29, #400]

      (527) 0x4931c0 LDR	X26, [SP, #120]

      (527) 0x4931c4 B	492ac8

      (527) 0x4931c8 ORR	X3, XZR, XZR

      (527) 0x4931cc ADRP	X0,

      (527) 0x4931d0 ADD	X0, X0, #2387

      (527) 0x4931d4 MOVZ	W1, #3440

      (527) 0x4931d8 MOVZ	W2, #1

      (527) 0x4931dc ORR	X20, XZR, X30

      (527) 0x4931e0 BL	4a5070

      (527) 0x4931e4 LDR	X8, [SP]

      (527) 0x4931e8 MOVZ	W9, #1

      (527) 0x4931ec ADRP	X0,

      (527) 0x4931f0 ADD	X0, X0, #2761

      (527) 0x4931f4 LDADD	X9, X8, [X8]

      (527) 0x4931f8 LDR	X8, [SP, #8]

      (527) 0x4931fc LDR	X8, [X8]

      (527) 0x493200 CBNZ	X8, 493188

      (527) 0x493204 B	493190

0x493208 LDP	X20, X19, [SP, #320]

0x49320c LDP	X22, X21, [SP, #304]

0x493210 LDP	X24, X23, [SP, #288]

0x493214 LDP	X26, X25, [SP, #272]

0x493218 LDP	X28, X27, [SP, #256]

0x49321c LDP	X29, X30, [SP, #240]

0x493220 ADD	SP, SP, #336

0x493224 RET

0x493228 HINT	#0

0x49322c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	IJMatrix_parcsr.c:3240-3484
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3240,3256-3322,3329-3352,3359-3368,3376-3377,3383-3390,3399-3411,3422-3424,3433-3445,3454-3458,3466-3484.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 22.33 to 10.00 cycles (2.23x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 22.33 to 2.00 cycles (11.17x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 380 bytes. The binary function is storing 320 bytes.

General properties

nb instructions	140
loop length	560
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.50	6.50	11.25	11.25	11.25	11.25	0.00	0.00	0.00	0.00	22.33	22.33	22.33	15.00	15.00
cycles	6.50	6.50	11.25	11.25	11.25	11.25	0.00	0.00	0.00	0.00	22.33	22.33	22.33	15.00	15.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	15.00
Overall L1	22.33

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.33 cycles. At this rate:

17% of peak load performance is reached (17.01 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
29% of peak store performance is reached (14.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4928b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X28, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X6, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X24, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X23, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4700 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4720 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV X9, X8, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MSUB X8, X9, X27, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X11, X9, X0, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X8, X9, X10, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X12, X9, X0, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X9, X9, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CSEL X13, X8, X9, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CSEL X19, X11, X12, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X19, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STR XZR, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.GE 492960 <.omp_outlined..21+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X11, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W25, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4de964>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3752	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X13, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ X22, 4929bc <.omp_outlined..21+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4929bc <.omp_outlined..21+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X8], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
HINT #0
HINT #0
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4de9c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3776	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X22, 4929f4 <.omp_outlined..21+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X24, [X8, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X7, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X30, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X19, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 492a0c <.omp_outlined..21+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 493208 <.omp_outlined..21+0x958>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X24, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X7, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X30, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X19, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 493208 <.omp_outlined..21+0x958>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X26, X19, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MOVN X27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR XZR, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X21, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X5, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X26, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X11, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X6, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X11, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X5, X6, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X23, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X23, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 492ad4 <.omp_outlined..21+0x224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	IJMatrix_parcsr.c:3240-3484
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 22.33 to 2.00 cycles (11.17x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 380 bytes. The binary function is storing 320 bytes.

General properties

nb instructions	140
loop length	560
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.50	6.50	11.25	11.25	11.25	11.25	0.00	0.00	0.00	0.00	22.33	22.33	22.33	15.00	15.00
cycles	6.50	6.50	11.25	11.25	11.25	11.25	0.00	0.00	0.00	0.00	22.33	22.33	22.33	15.00	15.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	15.00
Overall L1	22.33

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.33 cycles. At this rate:

17% of peak load performance is reached (17.01 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
29% of peak store performance is reached (14.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4928b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X28, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X6, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X24, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X23, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4700 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4720 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV X9, X8, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MSUB X8, X9, X27, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X11, X9, X0, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X8, X9, X10, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X12, X9, X0, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X9, X9, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CSEL X13, X8, X9, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CSEL X19, X11, X12, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X19, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STR XZR, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.GE 492960 <.omp_outlined..21+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X11, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W25, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4de964>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3752	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X13, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ X22, 4929bc <.omp_outlined..21+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4929bc <.omp_outlined..21+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X8], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
HINT #0
HINT #0
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4de9c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3776	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X22, 4929f4 <.omp_outlined..21+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X24, [X8, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X7, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X30, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X19, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 492a0c <.omp_outlined..21+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 493208 <.omp_outlined..21+0x958>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X24, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X7, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X30, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X19, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 493208 <.omp_outlined..21+0x958>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X26, X19, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MOVN X27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR XZR, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X21, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X5, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X26, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X11, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X6, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X11, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X5, X6, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X23, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X23, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 492ad4 <.omp_outlined..21+0x224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..21#0x4928b0–	3.42	1.29
○Loop 542 - IJMatrix_parcsr.c:3274-3275 - exec	0	0
○Loop 541 - IJMatrix_parcsr.c:3282-3283 - exec	0	0
▼Loop 537 - IJMatrix_parcsr.c:3291-3484 - exec–	0	0
▼Loop 536 - IJMatrix_parcsr.c:3291-3484 - exec–	0	0
▼Loop 535 - IJMatrix_parcsr.c:3291-3484 - exec–	0	0
▼Loop 527 - IJMatrix_parcsr.c:3291-3484 - exec–	0.04	0.02
▼Loop 531 - IJMatrix_parcsr.c:3383-3454 - exec–	3.37	1.1
○Loop 533 - IJMatrix_parcsr.c:3388-3390 - exec	0	0
○Loop 532 - IJMatrix_parcsr.c:3422-3424 - exec	0	0
▼Loop 528 - IJMatrix_parcsr.c:3470-3484 - exec–	0	0
▼Loop 529 - IJMatrix_parcsr.c:3475-3484 - exec–	0	0
○Loop 530 - IJMatrix_parcsr.c:3478-3484 - exec	0	0
○Loop 540 - IJMatrix_parcsr.c:3359-3362 - exec	0	0
○Loop 539 - IJMatrix_parcsr.c:3359-3362 - exec	0	0
○Loop 534 - IJMatrix_parcsr.c:3367-3367 - exec	0	0
○Loop 538 - IJMatrix_parcsr.c:3318-3320 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code