OV - exec - Function .omp_outlined..9#0x47f990

	Function: .omp_outlined..9#0x47f990	Module: exec	Source: par_csr_matop.c:829-995 [...]	Coverage: 0.96%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 829 - 995

--------------------------------------------------------------------------------

829: #pragma omp parallel

[...]

840:     ii = hypre_GetThreadNum();

841:     num_threads = hypre_NumActiveThreads();

842:     size = num_rows_diag_A/num_threads;

843:     rest = num_rows_diag_A - size*num_threads;

844:     if (ii < rest)

845:     {

846:        ns = ii*size+ii;

847:        ne = (ii+1)*size+ii+1;

848:     }

849:     else

850:     {

851:        ns = ii*size+rest;

852:        ne = (ii+1)*size+rest;

853:     }

854:     jj_count_diag = C_diag_i[ns];

855:     jj_count_offd = C_offd_i[ns];

856:     if (num_cols_diag_B || num_cols_offd_C)

857:     B_marker = hypre_CTAlloc(HYPRE_Int, num_cols_diag_B+num_cols_offd_C);

858:     for (i1 = 0; i1 < num_cols_diag_B+num_cols_offd_C; i1++)

859:       B_marker[i1] = -1;

[...]

865:     for (i1 = ns; i1 < ne; i1++)

[...]

874:       if ( allsquare )

875:       {

876:          B_marker[i1] = jj_count_diag;

877:          C_diag_data[jj_count_diag] = zero;

878:          C_diag_j[jj_count_diag] = i1;

879:          jj_count_diag++;

[...]

886:       if (num_cols_offd_A)

887:       {

888:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

889:          {

890:             i2 = A_offd_j[jj2];

891:             a_entry = A_offd_data[jj2];

[...]

897:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

898:             {

899:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

907:                if (B_marker[i3] < jj_row_begin_offd)

908:                {

909:                   B_marker[i3] = jj_count_offd;

910:                   C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3];

911:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

912:                   jj_count_offd++;

913:                }

914:                else

915:                   C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3];

916:             }

917:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

918:             {

919:                i3 = B_ext_diag_j[jj3];

920:                if (B_marker[i3] < jj_row_begin_diag)

921:                {

922:                   B_marker[i3] = jj_count_diag;

923:                   C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3];

924:                   C_diag_j[jj_count_diag] = i3;

925:                   jj_count_diag++;

926:                }

927:                else

928:                   C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3];

[...]

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

971:             {

972:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

980:                if (B_marker[i3] < jj_row_begin_offd)

981:                {

982:                   B_marker[i3] = jj_count_offd;

983:                   C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3];

984:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

985:                   jj_count_offd++;

986:                }

987:                else

988:                {

989:                   C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3];

[...]

995:     hypre_TFree(B_marker);

0x47f990 SUB	SP, SP, #320

0x47f994 STP	X29, X30, [SP, #224]

0x47f998 STP	X28, X27, [SP, #240]

0x47f99c STP	X26, X25, [SP, #256]

0x47f9a0 STP	X24, X23, [SP, #272]

0x47f9a4 STP	X22, X21, [SP, #288]

0x47f9a8 STP	X20, X19, [SP, #304]

0x47f9ac ADD	X29, SP, #224

0x47f9b0 LDR	X8, [X29, #296]

0x47f9b4 STUR	X7, [X29, #432]

0x47f9b8 ORR	X19, XZR, X6

0x47f9bc ORR	X20, XZR, X5

0x47f9c0 STUR	X8, [X29, #448]

0x47f9c4 LDR	X8, [X29, #288]

0x47f9c8 ORR	X21, XZR, X4

0x47f9cc ORR	X22, XZR, X3

0x47f9d0 ORR	X26, XZR, X2

0x47f9d4 STR	X8, [SP, #80]

0x47f9d8 LDR	X8, [X29, #280]

0x47f9dc STR	X8, [SP, #72]

0x47f9e0 LDR	X8, [X29, #272]

0x47f9e4 STR	X8, [SP, #64]

0x47f9e8 LDP	X8, X28, [X29, #256]

0x47f9ec STUR	X8, [X29, #456]

0x47f9f0 LDR	X8, [X29, #248]

0x47f9f4 STR	X8, [SP, #56]

0x47f9f8 LDR	X8, [X29, #240]

0x47f9fc STR	X8, [SP, #8]

0x47fa00 LDR	X8, [X29, #216]

0x47fa04 LDP	X27, X24, [X29, #224]

0x47fa08 STR	X8, [SP, #104]

0x47fa0c LDR	X8, [X29, #208]

0x47fa10 STR	X8, [SP, #96]

0x47fa14 LDR	X8, [X29, #200]

0x47fa18 STR	X8, [SP, #48]

0x47fa1c LDR	X8, [X29, #192]

0x47fa20 STR	X8, [SP, #32]

0x47fa24 LDR	X8, [X29, #184]

0x47fa28 STUR	X8, [X29, #488]

0x47fa2c LDR	X8, [X29, #176]

0x47fa30 STR	X8, [SP, #88]

0x47fa34 LDR	X8, [X29, #168]

0x47fa38 STUR	X8, [X29, #480]

0x47fa3c LDR	X8, [X29, #160]

0x47fa40 STR	X8, [SP, #40]

0x47fa44 LDR	X8, [X29, #152]

0x47fa48 STR	X8, [SP, #24]

0x47fa4c LDP	X8, X9, [X29, #136]

0x47fa50 STP	X9, X8, [X29, #976]

0x47fa54 LDR	X8, [X29, #128]

0x47fa58 STR	X8, [SP, #16]

0x47fa5c LDP	X8, X9, [X29, #112]

0x47fa60 STUR	X8, [X29, #496]

0x47fa64 LDP	X25, X8, [X29, #96]

0x47fa68 STP	X8, X9, [X29, #928]

0x47fa6c BL	4a4720

0x47fa70 ORR	X23, XZR, X0

0x47fa74 BL	4a4700

0x47fa78 LDR	X8, [X26]

0x47fa7c ADD	X10, X23, #1

0x47fa80 ORR	X13, XZR, X19

0x47fa84 SDIV	X9, X8, X0

0x47fa88 MSUB	X8, X9, X0, X8

0x47fa8c CMP	X23, X8

0x47fa90 MADD	X11, X9, X23, X8

0x47fa94 MADD	X8, X9, X10, X8

0x47fa98 ADD	X9, X9, #1

0x47fa9c MADD	X12, X9, X23, XZR

0x47faa0 MADD	X9, X9, X10, XZR

0x47faa4 CSEL	X8, X8, X9, #10

0x47faa8 CSEL	X26, X11, X12, #10

0x47faac LDR	X9, [X19]

0x47fab0 STUR	X8, [X29, #440]

0x47fab4 LDR	X8, [X22]

0x47fab8 LDR	X22, [X8, X26,LSL #3]

0x47fabc LDR	X8, [X21]

0x47fac0 LDR	X19, [X8, X26,LSL #3]

0x47fac4 LDR	X8, [X20]

0x47fac8 ORR	X10, X8, X9

0x47facc CBNZ	X10, 47fad8

0x47fad0 ORR	X0, XZR, XZR

0x47fad4 B	47fb38

0x47fad8 ADD	X0, X9, X8

0x47fadc MOVZ	W1, #8

0x47fae0 ORR	X21, XZR, X13

0x47fae4 BL	4a2570

0x47fae8 LDR	X8, [X20]

0x47faec LDR	X9, [X21]

0x47faf0 ADD	X8, X9, X8

0x47faf4 CMP	X8, #1

0x47faf8 B.LT	47fb38

0x47fafc ORR	X12, XZR, X21

0x47fb00 LDP	X30, X21, [SP, #88]

0x47fb04 ORR	X8, XZR, XZR

0x47fb08 MOVN	X9, #0

(443) 0x47fb0c STR	X9, [X0, X8,LSL #3]

(443) 0x47fb10 ADD	X8, X8, #1

(443) 0x47fb14 LDR	X10, [X20]

(443) 0x47fb18 LDR	X11, [X12]

(443) 0x47fb1c ADD	X10, X11, X10

(443) 0x47fb20 CMP	X8, X10

(443) 0x47fb24 B.LT	47fb0c

0x47fb28 LDUR	X8, [X29, #440]

0x47fb2c CMP	X26, X8

0x47fb30 B.LT	47fb48

0x47fb34 B	47ff18

0x47fb38 LDP	X30, X21, [SP, #88]

0x47fb3c LDUR	X8, [X29, #440]

0x47fb40 CMP	X26, X8

0x47fb44 B.GE	47ff18

0x47fb48 LDR	X8, [X25]

0x47fb4c LDR	X16, [X27]

0x47fb50 LDR	X17, [X24]

0x47fb54 ORR	X2, XZR, X22

0x47fb58 STUR	X8, [X29, #408]

0x47fb5c LDUR	X8, [X29, #496]

0x47fb60 LDR	X8, [X8]

0x47fb64 STR	X8, [SP, #112]

0x47fb68 LDR	X8, [SP, #16]

0x47fb6c LDUR	X9, [X29, #472]

0x47fb70 LDR	X8, [X8]

0x47fb74 LDR	X10, [X9]

0x47fb78 LDUR	X9, [X29, #464]

0x47fb7c ADD	X1, X8, #8

0x47fb80 LDR	X9, [X9]

0x47fb84 STP	X9, X10, [X29, #976]

0x47fb88 LDR	X9, [SP, #24]

0x47fb8c LDR	X13, [X9]

0x47fb90 LDR	X9, [SP, #32]

0x47fb94 LDR	X14, [X9]

0x47fb98 LDR	X9, [SP, #104]

0x47fb9c STR	X8, [SP, #104]

0x47fba0 LDR	X15, [X9]

0x47fba4 LDR	X9, [SP, #8]

0x47fba8 LDR	X18, [X9]

0x47fbac B	47fbd8

0x47fbb0 HINT	#0

0x47fbb4 HINT	#0

0x47fbb8 HINT	#0

0x47fbbc HINT	#0

(437) 0x47fbc0 LDP	X30, X21, [SP, #88]

  (436) 0x47fbc4 LDUR	X8, [X29, #440]

  (436) 0x47fbc8 ORR	X19, XZR, X3

  (436) 0x47fbcc ORR	X22, XZR, X2

  (436) 0x47fbd0 CMP	X26, X8

  (436) 0x47fbd4 B.GE	47ff18

  (436) 0x47fbd8 LDUR	X8, [X29, #432]

  (436) 0x47fbdc LDR	X8, [X8]

  (436) 0x47fbe0 CBZ	X8, 47fc04

  (436) 0x47fbe4 LDUR	X8, [X29, #416]

  (436) 0x47fbe8 ADD	X2, X22, #1

  (436) 0x47fbec STR	X22, [X0, X26,LSL #3]

  (436) 0x47fbf0 LDR	D0, [X8]

  (436) 0x47fbf4 LDUR	X8, [X29, #408]

  (436) 0x47fbf8 STR	D0, [X8, X22,LSL #3]

  (436) 0x47fbfc LDR	X8, [SP, #112]

  (436) 0x47fc00 STR	X26, [X8, X22,LSL #3]

  (436) 0x47fc04 LDUR	X8, [X29, #424]

  (436) 0x47fc08 LDR	X8, [X8]

  (436) 0x47fc0c CBZ	X8, 47fd80

  (436) 0x47fc10 LDR	X8, [SP, #104]

  (436) 0x47fc14 LDR	X4, [X8, X26,LSL #3]

  (436) 0x47fc18 LDR	X8, [X1, X26,LSL #3]

  (436) 0x47fc1c CMP	X4, X8

  (436) 0x47fc20 B.GE	47fda0

  (436) 0x47fc24 LDR	X8, [SP, #40]

  (436) 0x47fc28 ORR	X3, XZR, X19

  (436) 0x47fc2c LDR	X5, [X8]

  (436) 0x47fc30 LDR	X8, [SP, #48]

  (436) 0x47fc34 LDR	X6, [X8]

  (436) 0x47fc38 B	47fc50

0x47fc3c HINT	#0

    (440) 0x47fc40 LDR	X8, [X1, X26,LSL #3]

    (440) 0x47fc44 ADD	X4, X4, #1

    (440) 0x47fc48 CMP	X4, X8

    (440) 0x47fc4c B.GE	47fd84

    (440) 0x47fc50 LDUR	X8, [X29, #472]

    (440) 0x47fc54 LDR	X7, [X8, X4,LSL #3]

    (440) 0x47fc58 LDUR	X8, [X29, #464]

    (440) 0x47fc5c LDR	D0, [X8, X4,LSL #3]

    (440) 0x47fc60 ADD	X8, X7, #1

    (440) 0x47fc64 LDR	X9, [X13, X7,LSL #3]

    (440) 0x47fc68 LDR	X24, [X13, X8,LSL #3]

    (440) 0x47fc6c CMP	X9, X24

    (440) 0x47fc70 B.GE	47fcf0

    (440) 0x47fc74 LDUR	X11, [X29, #480]

    (440) 0x47fc78 LDR	X10, [X30]

    (440) 0x47fc7c LDR	X27, [X11]

    (440) 0x47fc80 LDUR	X11, [X29, #488]

    (440) 0x47fc84 LDR	X23, [X11]

    (440) 0x47fc88 B	47fca8

      (442) 0x47fc8c LDR	D1, [X10, X9,LSL #3]

      (442) 0x47fc90 LDR	D2, [X27, X12,LSL #3]

      (442) 0x47fc94 FMADD	D1, D0, D1, D2

      (442) 0x47fc98 STR	D1, [X27, X12,LSL #3]

      (442) 0x47fc9c ADD	X9, X9, #1

      (442) 0x47fca0 CMP	X9, X24

      (442) 0x47fca4 B.GE	47fcf0

      (442) 0x47fca8 LDR	X11, [X20]

      (442) 0x47fcac LDR	X12, [X5, X9,LSL #3]

      (442) 0x47fcb0 ADD	X11, X12, X11

      (442) 0x47fcb4 LDR	X12, [X0, X11,LSL #3]

      (442) 0x47fcb8 CMP	X12, X19

      (442) 0x47fcbc B.GE	47fc8c

      (442) 0x47fcc0 STR	X3, [X0, X11,LSL #3]

      (442) 0x47fcc4 LDR	D1, [X10, X9,LSL #3]

      (442) 0x47fcc8 LDR	X12, [X20]

      (442) 0x47fccc SUB	X11, X11, X12

      (442) 0x47fcd0 FMUL	D1, D0, D1

      (442) 0x47fcd4 STR	X11, [X23, X3,LSL #3]

      (442) 0x47fcd8 LDR	X24, [X13, X8,LSL #3]

      (442) 0x47fcdc STR	D1, [X27, X3,LSL #3]

      (442) 0x47fce0 ADD	X3, X3, #1

      (442) 0x47fce4 ADD	X9, X9, #1

      (442) 0x47fce8 CMP	X9, X24

      (442) 0x47fcec B.LT	47fca8

    (440) 0x47fcf0 LDR	X9, [X14, X7,LSL #3]

    (440) 0x47fcf4 LDR	X23, [X14, X8,LSL #3]

    (440) 0x47fcf8 CMP	X9, X23

    (440) 0x47fcfc B.GE	47fc40

    (440) 0x47fd00 LDUR	X11, [X29, #496]

    (440) 0x47fd04 LDR	X10, [X21]

    (440) 0x47fd08 LDR	X7, [X25]

    (440) 0x47fd0c LDR	X24, [X11]

    (440) 0x47fd10 B	47fd3c

0x47fd14 HINT	#0

0x47fd18 HINT	#0

0x47fd1c HINT	#0

      (441) 0x47fd20 LDR	D1, [X10, X9,LSL #3]

      (441) 0x47fd24 LDR	D2, [X7, X12,LSL #3]

      (441) 0x47fd28 FMADD	D1, D0, D1, D2

      (441) 0x47fd2c STR	D1, [X7, X12,LSL #3]

      (441) 0x47fd30 ADD	X9, X9, #1

      (441) 0x47fd34 CMP	X9, X23

      (441) 0x47fd38 B.GE	47fc40

      (441) 0x47fd3c LDR	X11, [X6, X9,LSL #3]

      (441) 0x47fd40 LDR	X12, [X0, X11,LSL #3]

      (441) 0x47fd44 CMP	X12, X22

      (441) 0x47fd48 B.GE	47fd20

      (441) 0x47fd4c LDR	D1, [X10, X9,LSL #3]

      (441) 0x47fd50 STR	X2, [X0, X11,LSL #3]

      (441) 0x47fd54 STR	X11, [X24, X2,LSL #3]

      (441) 0x47fd58 LDR	X23, [X14, X8,LSL #3]

      (441) 0x47fd5c FMUL	D1, D0, D1

      (441) 0x47fd60 STR	D1, [X7, X2,LSL #3]

      (441) 0x47fd64 ADD	X2, X2, #1

      (441) 0x47fd68 ADD	X9, X9, #1

      (441) 0x47fd6c CMP	X9, X23

      (441) 0x47fd70 B.LT	47fd3c

    (440) 0x47fd74 B	47fc40

0x47fd78 HINT	#0

0x47fd7c HINT	#0

  (436) 0x47fd80 ORR	X3, XZR, X19

  (436) 0x47fd84 LDR	X4, [X15, X26,LSL #3]

  (436) 0x47fd88 ADD	X26, X26, #1

  (436) 0x47fd8c LDR	X8, [X15, X26,LSL #3]

  (436) 0x47fd90 CMP	X4, X8

  (436) 0x47fd94 B.GE	47fbc4

(437) 0x47fd98 B	47fdb8

0x47fd9c HINT	#0

  (436) 0x47fda0 ORR	X3, XZR, X19

  (436) 0x47fda4 LDR	X4, [X15, X26,LSL #3]

  (436) 0x47fda8 ADD	X26, X26, #1

  (436) 0x47fdac LDR	X8, [X15, X26,LSL #3]

  (436) 0x47fdb0 CMP	X4, X8

  (436) 0x47fdb4 B.GE	47fbc4

(437) 0x47fdb8 LDR	X8, [SP, #56]

(437) 0x47fdbc LDR	X5, [X8]

(437) 0x47fdc0 LDR	X8, [SP, #64]

(437) 0x47fdc4 LDR	X6, [X8]

(437) 0x47fdc8 LDR	X8, [SP, #72]

(437) 0x47fdcc LDR	X7, [X8]

(437) 0x47fdd0 LDR	X8, [SP, #80]

(437) 0x47fdd4 LDR	X30, [X8]

(437) 0x47fdd8 B	47fdf0

0x47fddc HINT	#0

(437) 0x47fde0 LDR	X8, [X15, X26,LSL #3]

(437) 0x47fde4 ADD	X4, X4, #1

(437) 0x47fde8 CMP	X4, X8

(437) 0x47fdec B.GE	47fbc0

(437) 0x47fdf0 LDR	X9, [X16, X4,LSL #3]

(437) 0x47fdf4 LDR	D0, [X17, X4,LSL #3]

(437) 0x47fdf8 ADD	X8, X9, #1

(437) 0x47fdfc LDR	X10, [X18, X9,LSL #3]

(437) 0x47fe00 LDR	X27, [X18, X8,LSL #3]

(437) 0x47fe04 CMP	X10, X27

(437) 0x47fe08 B.GE	47fe78

(437) 0x47fe0c LDUR	X11, [X29, #456]

(437) 0x47fe10 LDR	X24, [X25]

(437) 0x47fe14 LDR	X23, [X11]

(437) 0x47fe18 LDUR	X11, [X29, #496]

(437) 0x47fe1c LDR	X11, [X11]

(437) 0x47fe20 B	47fe40

  (439) 0x47fe24 LDR	D1, [X23, X10,LSL #3]

  (439) 0x47fe28 LDR	D2, [X24, X21,LSL #3]

  (439) 0x47fe2c FMADD	D1, D0, D1, D2

  (439) 0x47fe30 STR	D1, [X24, X21,LSL #3]

  (439) 0x47fe34 ADD	X10, X10, #1

  (439) 0x47fe38 CMP	X10, X27

  (439) 0x47fe3c B.GE	47fe78

  (439) 0x47fe40 LDR	X12, [X5, X10,LSL #3]

  (439) 0x47fe44 LDR	X21, [X0, X12,LSL #3]

  (439) 0x47fe48 CMP	X21, X22

  (439) 0x47fe4c B.GE	47fe24

  (439) 0x47fe50 LDR	D1, [X23, X10,LSL #3]

  (439) 0x47fe54 STR	X2, [X0, X12,LSL #3]

  (439) 0x47fe58 STR	X12, [X11, X2,LSL #3]

  (439) 0x47fe5c LDR	X27, [X18, X8,LSL #3]

  (439) 0x47fe60 FMUL	D1, D0, D1

  (439) 0x47fe64 STR	D1, [X24, X2,LSL #3]

  (439) 0x47fe68 ADD	X2, X2, #1

  (439) 0x47fe6c ADD	X10, X10, #1

  (439) 0x47fe70 CMP	X10, X27

  (439) 0x47fe74 B.LT	47fe40

(437) 0x47fe78 LDR	X10, [X28]

(437) 0x47fe7c CBZ	X10, 47fde0

(437) 0x47fe80 LDR	X9, [X6, X9,LSL #3]

(437) 0x47fe84 LDR	X24, [X6, X8,LSL #3]

(437) 0x47fe88 CMP	X9, X24

(437) 0x47fe8c B.GE	47fde0

(437) 0x47fe90 LDUR	X11, [X29, #480]

(437) 0x47fe94 LDUR	X10, [X29, #448]

(437) 0x47fe98 LDR	X27, [X11]

(437) 0x47fe9c LDUR	X11, [X29, #488]

(437) 0x47fea0 LDR	X10, [X10]

(437) 0x47fea4 LDR	X23, [X11]

(437) 0x47fea8 B	47fec8

  (438) 0x47feac LDR	D1, [X10, X9,LSL #3]

  (438) 0x47feb0 LDR	D2, [X27, X12,LSL #3]

  (438) 0x47feb4 FMADD	D1, D0, D1, D2

  (438) 0x47feb8 STR	D1, [X27, X12,LSL #3]

  (438) 0x47febc ADD	X9, X9, #1

  (438) 0x47fec0 CMP	X9, X24

  (438) 0x47fec4 B.GE	47fde0

  (438) 0x47fec8 LDR	X12, [X30, X9,LSL #3]

  (438) 0x47fecc LDR	X11, [X20]

  (438) 0x47fed0 LDR	X12, [X7, X12,LSL #3]

  (438) 0x47fed4 ADD	X11, X12, X11

  (438) 0x47fed8 LDR	X12, [X0, X11,LSL #3]

  (438) 0x47fedc CMP	X12, X19

  (438) 0x47fee0 B.GE	47feac

  (438) 0x47fee4 STR	X3, [X0, X11,LSL #3]

  (438) 0x47fee8 LDR	D1, [X10, X9,LSL #3]

  (438) 0x47feec LDR	X12, [X20]

  (438) 0x47fef0 SUB	X11, X11, X12

  (438) 0x47fef4 FMUL	D1, D0, D1

  (438) 0x47fef8 STR	X11, [X23, X3,LSL #3]

  (438) 0x47fefc LDR	X24, [X6, X8,LSL #3]

  (438) 0x47ff00 STR	D1, [X27, X3,LSL #3]

  (438) 0x47ff04 ADD	X3, X3, #1

  (438) 0x47ff08 ADD	X9, X9, #1

  (438) 0x47ff0c CMP	X9, X24

  (438) 0x47ff10 B.LT	47fec8

(437) 0x47ff14 B	47fde0

0x47ff18 LDP	X20, X19, [SP, #304]

0x47ff1c LDP	X22, X21, [SP, #288]

0x47ff20 LDP	X24, X23, [SP, #272]

0x47ff24 LDP	X26, X25, [SP, #256]

0x47ff28 LDP	X28, X27, [SP, #240]

0x47ff2c LDP	X29, X30, [SP, #224]

0x47ff30 ADD	SP, SP, #320

0x47ff34 B	4a2670

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_csr_matop.c:829-995
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:829,840-859,865,874-879,886-891,897-899,907-928,937-940,946-948,956-972,980-989,995.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 30.33 to 10.00 cycles (3.03x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 30.33 to 1.50 cycles (20.22x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 576 bytes. The binary function is storing 328 bytes.

General properties

nb instructions	149
loop length	596
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	9.50	9.50	9.50	9.50	0.00	0.00	0.00	0.00	30.33	30.33	30.33	16.00	16.00
cycles	5.50	5.50	9.50	9.50	9.50	9.50	0.00	0.00	0.00	0.00	30.33	30.33	30.33	16.00	16.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	17.13
Overall L1	30.33

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 30.33 cycles. At this rate:

19% of peak load performance is reached (18.99 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.81 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 47f990

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X7, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X21, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X28, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X27, X24, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X9, X8, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X25, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #928]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a4720 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4700 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X13, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV X9, X8, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MSUB X8, X9, X0, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X23, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X11, X9, X23, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X8, X9, X10, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X12, X9, X23, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X9, X9, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CSEL X8, X8, X9, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X26, X11, X12, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X10, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ X10, 47fad8 <.omp_outlined..9+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47fb38 <.omp_outlined..9+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 47fb38 <.omp_outlined..9+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X12, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X30, X21, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 47fb48 <.omp_outlined..9+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 47ff18 <.omp_outlined..9+0x588>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X30, X21, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47ff18 <.omp_outlined..9+0x588>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X2, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X9, X10, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47fbd8 <.omp_outlined..9+0x248>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a2670 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	par_csr_matop.c:829-995
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 30.33 to 1.50 cycles (20.22x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 576 bytes. The binary function is storing 328 bytes.

General properties

nb instructions	149
loop length	596
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	9.50	9.50	9.50	9.50	0.00	0.00	0.00	0.00	30.33	30.33	30.33	16.00	16.00
cycles	5.50	5.50	9.50	9.50	9.50	9.50	0.00	0.00	0.00	0.00	30.33	30.33	30.33	16.00	16.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	17.13
Overall L1	30.33

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 30.33 cycles. At this rate:

19% of peak load performance is reached (18.99 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.81 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 47f990

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X7, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X21, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X28, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X27, X24, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X9, X8, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X25, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #928]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a4720 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4700 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X13, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV X9, X8, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MSUB X8, X9, X0, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X23, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X11, X9, X23, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X8, X9, X10, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X12, X9, X23, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X9, X9, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CSEL X8, X8, X9, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X26, X11, X12, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X10, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ X10, 47fad8 <.omp_outlined..9+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47fb38 <.omp_outlined..9+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 47fb38 <.omp_outlined..9+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X12, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X30, X21, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 47fb48 <.omp_outlined..9+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 47ff18 <.omp_outlined..9+0x588>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X30, X21, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47ff18 <.omp_outlined..9+0x588>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X2, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X9, X10, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47fbd8 <.omp_outlined..9+0x248>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a2670 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼.omp_outlined..9#0x47f990–	0.96	0.36
▼Loop 437 - par_csr_matop.c:865-989 - exec–	0.21	0.07
○Loop 439 - par_csr_matop.c:946-965 - exec	0.72	0.24
▼Loop 436 - par_csr_matop.c:865-937 - exec–	0.01	0.01
▼Loop 440 - par_csr_matop.c:888-928 - exec–	0	0
○Loop 442 - par_csr_matop.c:897-915 - exec	0	0
○Loop 441 - par_csr_matop.c:917-928 - exec	0	0
○Loop 438 - par_csr_matop.c:970-989 - exec	0	0
○Loop 443 - par_csr_matop.c:858-859 - exec	0.01	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code