OV - exec - Function .omp_outlined.#0x496ee0

	Function: .omp_outlined.#0x496ee0	Module: exec	Source: csr_matop.c:185-302 [...]	Coverage: 0.7%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c: 185 - 302

--------------------------------------------------------------------------------

185: #pragma omp parallel private(ia, ib, ic, ja, jb, num_nonzeros, row_start, counter, a_entry, b_entry)

[...]

192:     ii = hypre_GetThreadNum();

193:     num_threads = hypre_NumActiveThreads();

194:

195:    size = nrows_A/num_threads;

196:    rest = nrows_A - size*num_threads;

197:     if (ii < rest)

198:     {

199:        ns = ii*size+ii;

200:        ne = (ii+1)*size+ii+1;

201:     }

202:     else

203:     {

204:        ns = ii*size+rest;

205:        ne = (ii+1)*size+rest;

206:     }

207:

208:     B_marker = hypre_CTAlloc(HYPRE_Int, ncols_B);

209:

210:     for (ib = 0; ib < ncols_B; ib++)

211:       B_marker[ib] = -1;

212:

213:     num_nonzeros = 0;

214:     for (ic = ns; ic < ne; ic++)

215:     {

216:         C_i[ic] = num_nonzeros;

217: 	if (allsquare)

218:         {

219:            B_marker[ic] = ic;

220:            num_nonzeros++;

221:         }

222: 	for (ia = A_i[ic]; ia < A_i[ic+1]; ia++)

223: 	{

224: 	   ja = A_j[ia];

225: 	   for (ib = B_i[ja]; ib < B_i[ja+1]; ib++)

226: 	   {

227: 	      jb = B_j[ib];

228: 	      if (B_marker[jb] != ic)

229: 	      {

230: 	 	 B_marker[jb] = ic;

231: 		 num_nonzeros++;

232: 	      }

233: 	   }

234:    	}

235:    }

236:    jj_count[ii] = num_nonzeros;

237:

238: #ifdef HYPRE_USING_OPENMP

239: #pragma omp barrier

240: #endif

241:

242:     if (ii)

243:     {

244:        jj = jj_count[0];

245:        for (i1 = 1; i1 < ii; i1++)

246:           jj += jj_count[i1];

247:

248:        for (i1 = ns; i1 < ne; i1++)

249:           C_i[i1] += jj;

250:     }

251:     else

252:     {

253:        C_i[nrows_A] = 0;

254:        for (i1 = 0; i1 < num_threads; i1++)

255:           C_i[nrows_A] += jj_count[i1];

256:

257:        C = hypre_CSRMatrixCreate(nrows_A, ncols_B, C_i[nrows_A]);

258:        hypre_CSRMatrixI(C) = C_i;

259:        hypre_CSRMatrixInitialize(C);

260:        C_j = hypre_CSRMatrixJ(C);

261:        C_data = hypre_CSRMatrixData(C);

262:     }

263:

264: #ifdef HYPRE_USING_OPENMP

265: #pragma omp barrier

266: #endif

267:

268:    for (ib = 0; ib < ncols_B; ib++)

269:       B_marker[ib] = -1;

270:

271:    counter = C_i[ns];

272:    for (ic = ns; ic < ne; ic++)

273:    {

274:       row_start = C_i[ic];

275:       if (allsquare)

276:       {

277:          B_marker[ic] = counter;

278:          C_data[counter] = 0;

279:          C_j[counter] = ic;

280:          counter++;

281:       }

282:       for (ia = A_i[ic]; ia < A_i[ic+1]; ia++)

283:       {

284: 	 ja = A_j[ia];

285: 	 a_entry = A_data[ia];

286: 	 for (ib = B_i[ja]; ib < B_i[ja+1]; ib++)

287: 	 {

288: 	    jb = B_j[ib];

289: 	    b_entry = B_data[ib];

290: 	    if (B_marker[jb] < row_start)

291: 	    {

292: 		B_marker[jb] = counter;

293: 		C_j[B_marker[jb]] = jb;

294: 		C_data[B_marker[jb]] = a_entry*b_entry;

295: 		counter++;

296: 	    }

297: 	    else

298: 		C_data[B_marker[jb]] += a_entry*b_entry;

299: 	}

300:       }

301:    }

302:    hypre_TFree(B_marker);

0x496ee0 SUB	SP, SP, #192

0x496ee4 STP	X29, X30, [SP, #96]

0x496ee8 STP	X28, X27, [SP, #112]

0x496eec STP	X26, X25, [SP, #128]

0x496ef0 STP	X24, X23, [SP, #144]

0x496ef4 STP	X22, X21, [SP, #160]

0x496ef8 STP	X20, X19, [SP, #176]

0x496efc ADD	X29, SP, #96

0x496f00 STP	X6, X7, [X29, #992]

0x496f04 STUR	X4, [X29, #504]

0x496f08 ORR	X19, XZR, X5

0x496f0c ORR	X24, XZR, X3

0x496f10 ORR	X25, XZR, X2

0x496f14 STR	X0, [SP, #48]

0x496f18 LDR	X8, [X29, #152]

0x496f1c STR	X8, [SP, #32]

0x496f20 LDR	X8, [X29, #144]

0x496f24 STR	X8, [SP, #24]

0x496f28 LDR	X8, [X29, #120]

0x496f2c LDP	X23, X22, [X29, #128]

0x496f30 STR	X8, [SP, #16]

0x496f34 LDP	X27, X8, [X29, #104]

0x496f38 STUR	X8, [X29, #496]

0x496f3c LDR	X8, [X29, #96]

0x496f40 STUR	X8, [X29, #472]

0x496f44 BL	4a4720

0x496f48 ORR	X28, XZR, X0

0x496f4c BL	4a4700

0x496f50 LDR	X8, [X25]

0x496f54 STR	X0, [SP, #8]

0x496f58 ADD	X10, X28, #1

0x496f5c MOVZ	W1, #8

0x496f60 SDIV	X9, X8, X0

0x496f64 MSUB	X8, X9, X0, X8

0x496f68 LDR	X0, [X24]

0x496f6c CMP	X28, X8

0x496f70 MADD	X11, X9, X28, X8

0x496f74 MADD	X8, X9, X10, X8

0x496f78 ADD	X9, X9, #1

0x496f7c MADD	X12, X9, X28, XZR

0x496f80 MADD	X9, X9, X10, XZR

0x496f84 CSEL	X21, X11, X12, #10

0x496f88 CSEL	X26, X8, X9, #10

0x496f8c BL	4a2570

0x496f90 LDR	X8, [X24]

0x496f94 ORR	X20, XZR, X0

0x496f98 CMP	X8, #1

0x496f9c B.LT	496fbc

0x496fa0 ORR	X8, XZR, XZR

0x496fa4 MOVN	X9, #0

(37) 0x496fa8 STR	X9, [X20, X8,LSL #3]

(37) 0x496fac ADD	X8, X8, #1

(37) 0x496fb0 LDR	X10, [X24]

(37) 0x496fb4 CMP	X8, X10

(37) 0x496fb8 B.LT	496fa8

0x496fbc ORR	X8, XZR, XZR

0x496fc0 CMP	X21, X26

0x496fc4 STR	X27, [SP, #40]

0x496fc8 B.GE	497094

0x496fcc LDUR	X12, [X29, #472]

0x496fd0 LDUR	X9, [X29, #504]

0x496fd4 LDP	X10, X11, [X29, #992]

0x496fd8 ORR	X14, XZR, X21

0x496fdc LDR	X12, [X12]

0x496fe0 LDR	X9, [X9]

0x496fe4 LDR	X10, [X10]

0x496fe8 LDR	X11, [X11]

0x496fec ADD	X13, X12, #8

0x496ff0 B	497008

0x496ff4 HINT	#0

0x496ff8 HINT	#0

0x496ffc HINT	#0

    (33) 0x497000 CMP	X14, X26

    (33) 0x497004 B.GE	497094

    (33) 0x497008 STR	X8, [X9, X14,LSL #3]

    (33) 0x49700c ORR	X15, XZR, X14

    (33) 0x497010 LDR	X14, [X19]

    (33) 0x497014 CBZ	X14, 497020

    (33) 0x497018 ADD	X8, X8, #1

    (33) 0x49701c STR	X15, [X20, X15,LSL #3]

    (33) 0x497020 ADD	X14, X15, #1

    (33) 0x497024 LDR	X16, [X10, X15,LSL #3]

    (33) 0x497028 LDR	X1, [X10, X14,LSL #3]

    (33) 0x49702c CMP	X16, X1

    (33) 0x497030 B.GE	497000

  (36) 0x497034 LDR	X17, [X27]

  (36) 0x497038 B	497050

0x49703c HINT	#0

(34) 0x497040 LDR	X1, [X10, X14,LSL #3]

  (36) 0x497044 ADD	X16, X16, #1

  (36) 0x497048 CMP	X16, X1

  (36) 0x49704c B.GE	497000

  (36) 0x497050 LDR	X18, [X11, X16,LSL #3]

  (36) 0x497054 LDR	X0, [X12, X18,LSL #3]

  (36) 0x497058 LDR	X2, [X13, X18,LSL #3]

  (36) 0x49705c CMP	X0, X2

  (36) 0x497060 B.LT	497074

  (36) 0x497064 B	497044

  (35) 0x497068 ADD	X0, X0, #1

  (35) 0x49706c CMP	X0, X2

  (35) 0x497070 B.GE	497040

  (35) 0x497074 LDR	X1, [X17, X0,LSL #3]

  (35) 0x497078 LDR	X3, [X20, X1,LSL #3]

  (35) 0x49707c CMP	X3, X15

  (35) 0x497080 B.EQ	497068

  (35) 0x497084 STR	X15, [X20, X1,LSL #3]

  (35) 0x497088 ADD	X8, X8, #1

  (35) 0x49708c LDR	X2, [X13, X18,LSL #3]

  (35) 0x497090 B	497068

0x497094 LDUR	X27, [X29, #496]

0x497098 ADRP	X0,

0x49709c ADD	X0, X0, #232

0x4970a0 LDR	X9, [X27]

0x4970a4 STR	X8, [X9, X28,LSL #3]

0x4970a8 LDR	X8, [SP, #48]

0x4970ac LDR	W1, [X8]

0x4970b0 STR	W1, [SP, #48]

0x4970b4 BL	40f4b0

0x4970b8 CBZ	X28, 4970f4

0x4970bc LDR	X10, [X27]

0x4970c0 SUBS	X11, X28, #2

0x4970c4 LDR	X8, [X10]

0x4970c8 B.LT	49712c

0x4970cc LDR	X27, [SP, #40]

0x4970d0 SUB	X13, X28, #1

0x4970d4 CMP	X11, #3

0x4970d8 AND	X9, X13, #4160

0x4970dc B.CS	497138

0x4970e0 MOVZ	W11, #1

0x4970e4 LDR	X28, [SP, #32]

0x4970e8 LDR	W1, [SP, #48]

0x4970ec CBNZ	X9, 497188

0x4970f0 B	49719c

0x4970f4 LDUR	X8, [X29, #504]

0x4970f8 LDR	X16, [SP, #8]

0x4970fc LDR	X9, [X25]

0x497100 CMP	X16, #1

0x497104 LDR	X8, [X8]

0x497108 LDP	X28, X27, [SP, #32]

0x49710c STR	XZR, [X8, X9,LSL #3]

0x497110 B.LT	497250

0x497114 LDUR	X9, [X29, #496]

0x497118 CMP	X16, #1

0x49711c LDR	X9, [X9]

0x497120 B.NE	4971f4

0x497124 ORR	X10, XZR, XZR

0x497128 B	497238

0x49712c LDP	X28, X27, [SP, #32]

0x497130 LDR	W1, [SP, #48]

0x497134 B	49719c

0x497138 AND	X13, X13, #8062

0x49713c ORR	X11, XZR, XZR

0x497140 ADD	X12, X10, #16

0x497144 SUB	X13, XZR, X13

(31) 0x497148 LDUR	X14, [X12, #504]

(31) 0x49714c SUB	X11, X11, #4

(31) 0x497150 CMP	X13, X11

(31) 0x497154 ADD	X8, X14, X8

(31) 0x497158 LDP	X14, X15, [X12]

(31) 0x49715c ADD	X14, X15, X14

(31) 0x497160 ADD	X8, X14, X8

(31) 0x497164 LDR	X14, [X12, #16]

(31) 0x497168 ADD	X12, X12, #32

(31) 0x49716c ADD	X8, X14, X8

(31) 0x497170 B.NE	497148

0x497174 MOVZ	W12, #1

0x497178 SUB	X11, X12, X11

0x49717c LDR	X28, [SP, #32]

0x497180 LDR	W1, [SP, #48]

0x497184 CBZ	X9, 49719c

0x497188 ADD	X10, X10, X11,LSL #3

(32) 0x49718c LDR	X11, [X10], #8

(32) 0x497190 SUBS	X9, X9, #1

(32) 0x497194 ADD	X8, X11, X8

(32) 0x497198 B.NE	49718c

0x49719c CMP	X21, X26

0x4971a0 B.GE	4971d8

0x4971a4 LDUR	X9, [X29, #504]

0x4971a8 ORR	X10, XZR, X21

0x4971ac LDR	X9, [X9]

0x4971b0 HINT	#0

0x4971b4 HINT	#0

0x4971b8 HINT	#0

0x4971bc HINT	#0

(30) 0x4971c0 LDR	X11, [X9, X10,LSL #3]

(30) 0x4971c4 ADD	X11, X11, X8

(30) 0x4971c8 STR	X11, [X9, X10,LSL #3]

(30) 0x4971cc ADD	X10, X10, #1

(30) 0x4971d0 CMP	X10, X26

(30) 0x4971d4 B.LT	4971c0

0x4971d8 ADRP	X0,

0x4971dc ADD	X0, X0, #256

0x4971e0 BL	40f4b0

0x4971e4 LDR	X8, [X24]

0x4971e8 CMP	X8, #1

0x4971ec B.GE	4972b0

0x4971f0 B	4972d4

0x4971f4 ORR	X10, XZR, XZR

0x4971f8 AND	X11, X16, #8127

0x4971fc HINT	#0

(29) 0x497200 LDR	X14, [X25]

(29) 0x497204 ADD	X12, X9, X10,LSL #3

(29) 0x497208 ADD	X10, X10, #2

(29) 0x49720c CMP	X11, X10

(29) 0x497210 LDR	X13, [X12]

(29) 0x497214 LDR	X15, [X8, X14,LSL #3]

(29) 0x497218 ADD	X13, X15, X13

(29) 0x49721c STR	X13, [X8, X14,LSL #3]

(29) 0x497220 LDR	X13, [X25]

(29) 0x497224 LDR	X12, [X12, #8]

(29) 0x497228 LDR	X14, [X8, X13,LSL #3]

(29) 0x49722c ADD	X12, X14, X12

(29) 0x497230 STR	X12, [X8, X13,LSL #3]

(29) 0x497234 B.NE	497200

0x497238 TBZ	W16, #0, 497250

0x49723c LDR	X9, [X9, X10,LSL #3]

0x497240 LDR	X10, [X25]

0x497244 LDR	X11, [X8, X10,LSL #3]

0x497248 ADD	X9, X11, X9

0x49724c STR	X9, [X8, X10,LSL #3]

0x497250 LDR	X0, [X25]

0x497254 LDR	X1, [X24]

0x497258 LDR	X2, [X8, X0,LSL #3]

0x49725c BL	497e00

0x497260 LDR	X25, [SP, #16]

0x497264 LDUR	X8, [X29, #504]

0x497268 STR	X0, [X25]

0x49726c LDR	X8, [X8]

0x497270 STR	X8, [X0]

0x497274 LDR	X0, [X25]

0x497278 BL	497ec0

0x49727c LDR	X8, [X25]

0x497280 LDR	W1, [SP, #48]

0x497284 LDR	X8, [X8, #8]

0x497288 STR	X8, [X23]

0x49728c LDR	X8, [X25]

0x497290 LDR	X8, [X8, #48]

0x497294 STR	X8, [X22]

0x497298 ADRP	X0,

0x49729c ADD	X0, X0, #256

0x4972a0 BL	40f4b0

0x4972a4 LDR	X8, [X24]

0x4972a8 CMP	X8, #1

0x4972ac B.LT	4972d4

0x4972b0 ORR	X8, XZR, XZR

0x4972b4 MOVN	X9, #0

0x4972b8 HINT	#0

0x4972bc HINT	#0

(28) 0x4972c0 STR	X9, [X20, X8,LSL #3]

(28) 0x4972c4 ADD	X8, X8, #1

(28) 0x4972c8 LDR	X10, [X24]

(28) 0x4972cc CMP	X8, X10

(28) 0x4972d0 B.LT	4972c0

0x4972d4 CMP	X21, X26

0x4972d8 B.GE	4973f8

0x4972dc LDUR	X8, [X29, #504]

0x4972e0 LDUR	X15, [X29, #472]

0x4972e4 LDP	X12, X13, [X29, #992]

0x4972e8 LDR	X14, [SP, #24]

0x4972ec LDR	X10, [X22]

0x4972f0 LDR	X11, [X23]

0x4972f4 LDR	X8, [X8]

0x4972f8 LDR	X15, [X15]

0x4972fc LDR	X12, [X12]

0x497300 LDR	X13, [X13]

0x497304 LDR	X14, [X14]

0x497308 LDR	X9, [X8, X21,LSL #3]

0x49730c ADD	X16, X15, #8

0x497310 B	497328

0x497314 HINT	#0

0x497318 HINT	#0

0x49731c HINT	#0

    (23) 0x497320 CMP	X21, X26

    (23) 0x497324 B.GE	4973f8

    (23) 0x497328 LDR	X17, [X8, X21,LSL #3]

    (23) 0x49732c LDR	X18, [X19]

    (23) 0x497330 CBZ	X18, 497344

    (23) 0x497334 STR	X9, [X20, X21,LSL #3]

    (23) 0x497338 STR	XZR, [X10, X9,LSL #3]

    (23) 0x49733c STR	X21, [X11, X9,LSL #3]

    (23) 0x497340 ADD	X9, X9, #1

    (23) 0x497344 LDR	X18, [X12, X21,LSL #3]

    (23) 0x497348 ADD	X21, X21, #1

    (23) 0x49734c LDR	X4, [X12, X21,LSL #3]

    (23) 0x497350 CMP	X18, X4

    (23) 0x497354 B.GE	497320

  (24) 0x497358 LDR	X0, [X27]

  (24) 0x49735c LDR	X1, [X28]

  (24) 0x497360 B	497374

  (27) 0x497364 LDR	X4, [X12, X21,LSL #3]

  (24) 0x497368 ADD	X18, X18, #1

  (24) 0x49736c CMP	X18, X4

  (24) 0x497370 B.GE	497320

  (24) 0x497374 LDR	X2, [X13, X18,LSL #3]

  (24) 0x497378 LDR	X3, [X15, X2,LSL #3]

  (24) 0x49737c LDR	X5, [X16, X2,LSL #3]

  (24) 0x497380 CMP	X3, X5

  (24) 0x497384 B.GE	497368

(25) 0x497388 LDR	D0, [X14, X18,LSL #3]

(25) 0x49738c LDR	X4, [X22]

(25) 0x497390 LDR	X6, [X23]

(25) 0x497394 B	4973b8

0x497398 HINT	#0

0x49739c HINT	#0

(25) 0x4973a0 LDR	D2, [X4, X24,LSL #3]

(25) 0x4973a4 FMADD	D1, D0, D1, D2

(25) 0x4973a8 STR	D1, [X4, X24,LSL #3]

(25) 0x4973ac ADD	X3, X3, #1

(25) 0x4973b0 CMP	X3, X5

(25) 0x4973b4 B.GE	497364

  (26) 0x4973b8 LDR	X7, [X0, X3,LSL #3]

  (26) 0x4973bc LDR	D1, [X1, X3,LSL #3]

  (26) 0x4973c0 LDR	X24, [X20, X7,LSL #3]

  (26) 0x4973c4 CMP	X24, X17

  (26) 0x4973c8 B.GE	4973a0

  (26) 0x4973cc STR	X9, [X20, X7,LSL #3]

  (26) 0x4973d0 STR	X7, [X6, X9,LSL #3]

  (26) 0x4973d4 FMUL	D1, D0, D1

  (26) 0x4973d8 ADD	X9, X9, #1

  (26) 0x4973dc LDR	X5, [X20, X7,LSL #3]

  (26) 0x4973e0 STR	D1, [X4, X5,LSL #3]

  (26) 0x4973e4 LDR	X5, [X16, X2,LSL #3]

  (26) 0x4973e8 ADD	X3, X3, #1

  (26) 0x4973ec CMP	X3, X5

  (26) 0x4973f0 B.LT	4973b8

  (27) 0x4973f4 B	497364

0x4973f8 ORR	X0, XZR, X20

0x4973fc LDP	X20, X19, [SP, #176]

0x497400 LDP	X22, X21, [SP, #160]

0x497404 LDP	X24, X23, [SP, #144]

0x497408 LDP	X26, X25, [SP, #128]

0x49740c LDP	X28, X27, [SP, #112]

0x497410 LDP	X29, X30, [SP, #96]

0x497414 ADD	SP, SP, #192

0x497418 B	4a2670

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	csr_matop.c:185-302
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:185,192-302.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 32.33 to 10.00 cycles (3.23x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 32.33 to 4.00 cycles (8.08x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 660 bytes. The binary function is storing 244 bytes.

General properties

nb instructions	202
loop length	808
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

23.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	14.50	14.50	17.00	17.00	17.00	17.00	0.00	0.00	0.00	0.00	32.33	32.33	32.33	12.00	12.00
cycles	14.50	14.50	17.00	17.00	17.00	17.00	0.00	0.00	0.00	0.00	32.33	32.33	32.33	12.00	12.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	23.25
Overall L1	32.33

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 32.33 cycles. At this rate:

21% of peak load performance is reached (20.41 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.55 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 496ee0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X6, X7, [X29, #992]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X4, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X0, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X23, X22, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X27, X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a4720 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X28, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4700 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X10, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV X9, X8, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MSUB X8, X9, X0, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X28, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X11, X9, X28, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X8, X9, X10, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X12, X9, X28, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X9, X9, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CSEL X21, X11, X12, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X26, X8, X9, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 496fbc <.omp_outlined.+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X21, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STR X27, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.GE 497094 <.omp_outlined.+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X12, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X10, X11, [X29, #992]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X14, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 497008 <.omp_outlined.+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
LDUR X27, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4df098>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #232	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W1, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X28, 4970f4 <.omp_outlined.+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X11, X28, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.LT 49712c <.omp_outlined.+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X27, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X13, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
AND X9, X13, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CS 497138 <.omp_outlined.+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X28, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X9, 497188 <.omp_outlined.+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 49719c <.omp_outlined.+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X28, X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR XZR, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LT 497250 <.omp_outlined.+0x370>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.NE 4971f4 <.omp_outlined.+0x314>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 497238 <.omp_outlined.+0x358>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X28, X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W1, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 49719c <.omp_outlined.+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
AND X13, X13, #8062	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X11, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X28, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X9, 49719c <.omp_outlined.+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X10, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X21, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4971d8 <.omp_outlined.+0x2f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X10, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
HINT #0
HINT #0
HINT #0
ADRP X0, <4df1d8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4972b0 <.omp_outlined.+0x3d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4972d4 <.omp_outlined.+0x3f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND X11, X16, #8127	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
TBZ W16, #0, 497250 <.omp_outlined.+0x370>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X9, [X8, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 497e00 <hypre_CSRMatrixCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X25, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 497ec0 <hypre_CSRMatrixInitialize>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADRP X0, <4df298>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4972d4 <.omp_outlined.+0x3f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
CMP X21, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4973f8 <.omp_outlined.+0x518>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X15, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X12, X13, [X29, #992]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X14, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 497328 <.omp_outlined.+0x448>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a2670 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	csr_matop.c:185-302
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:185,192-302.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 32.33 to 4.00 cycles (8.08x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 660 bytes. The binary function is storing 244 bytes.

General properties

nb instructions	202
loop length	808
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

23.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	14.50	14.50	17.00	17.00	17.00	17.00	0.00	0.00	0.00	0.00	32.33	32.33	32.33	12.00	12.00
cycles	14.50	14.50	17.00	17.00	17.00	17.00	0.00	0.00	0.00	0.00	32.33	32.33	32.33	12.00	12.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	23.25
Overall L1	32.33

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 32.33 cycles. At this rate:

21% of peak load performance is reached (20.41 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.55 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 496ee0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X6, X7, [X29, #992]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X4, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X0, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X23, X22, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X27, X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a4720 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X28, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4700 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X10, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV X9, X8, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MSUB X8, X9, X0, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X28, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X11, X9, X28, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X8, X9, X10, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X12, X9, X28, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X9, X9, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CSEL X21, X11, X12, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X26, X8, X9, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 496fbc <.omp_outlined.+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X21, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STR X27, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.GE 497094 <.omp_outlined.+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X12, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X10, X11, [X29, #992]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X14, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 497008 <.omp_outlined.+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
LDUR X27, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4df098>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #232	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W1, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X28, 4970f4 <.omp_outlined.+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X11, X28, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.LT 49712c <.omp_outlined.+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X27, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X13, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
AND X9, X13, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CS 497138 <.omp_outlined.+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X28, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X9, 497188 <.omp_outlined.+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 49719c <.omp_outlined.+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X28, X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR XZR, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LT 497250 <.omp_outlined.+0x370>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.NE 4971f4 <.omp_outlined.+0x314>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 497238 <.omp_outlined.+0x358>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X28, X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W1, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 49719c <.omp_outlined.+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
AND X13, X13, #8062	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X11, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X28, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X9, 49719c <.omp_outlined.+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X10, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X21, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4971d8 <.omp_outlined.+0x2f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X10, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
HINT #0
HINT #0
HINT #0
ADRP X0, <4df1d8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4972b0 <.omp_outlined.+0x3d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4972d4 <.omp_outlined.+0x3f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND X11, X16, #8127	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
TBZ W16, #0, 497250 <.omp_outlined.+0x370>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X9, [X8, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 497e00 <hypre_CSRMatrixCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X25, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 497ec0 <hypre_CSRMatrixInitialize>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADRP X0, <4df298>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4972d4 <.omp_outlined.+0x3f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
CMP X21, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4973f8 <.omp_outlined.+0x518>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X15, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X12, X13, [X29, #992]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X14, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 497328 <.omp_outlined.+0x448>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a2670 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼.omp_outlined.#0x496ee0–	0.7	0.27
▼Loop 25 - csr_matop.c:272-298 - exec–	0.04	0.01
○Loop 26 - csr_matop.c:286-295 - exec	0.35	0.11
▼Loop 24 - csr_matop.c:272-286 - exec–	0.06	0.02
○Loop 23 - csr_matop.c:272-282 - exec	0	0
○Loop 27 - csr_matop.c:282-286 - exec	0	0
○Loop 32 - csr_matop.c:245-246 - exec	0	0
○Loop 30 - csr_matop.c:248-249 - exec	0	0
▼Loop 34 - csr_matop.c:214-231 - exec–	0	0
○Loop 35 - csr_matop.c:225-231 - exec	0.21	0.07
▼Loop 36 - csr_matop.c:214-225 - exec–	0.04	0.01
○Loop 33 - csr_matop.c:214-222 - exec	0	0
○Loop 37 - csr_matop.c:210-211 - exec	0	0
○Loop 28 - csr_matop.c:268-269 - exec	0	0
○Loop 31 - csr_matop.c:245-246 - exec	0	0
○Loop 29 - csr_matop.c:254-255 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code