OV - exec - Function .omp_outlined.#0x47dce0

	Function: .omp_outlined.#0x47dce0	Module: exec	Source: par_csr_matop.c:102-276 [...]	Coverage: 0.76%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 102 - 276

--------------------------------------------------------------------------------

102: #pragma omp parallel private(ii, i1, jj_row_begin_diag, jj_row_begin_offd, jj_count_diag, jj_count_offd, jj2, i2, jj3, i3)

[...]

108:     ii = hypre_GetThreadNum();

109:     if (ii < rest)

110:     {

111:        ns = ii*size+ii;

112:        ne = (ii+1)*size+ii+1;

113:     }

114:     else

115:     {

116:        ns = ii*size+rest;

117:        ne = (ii+1)*size+rest;

118:     }

119:     jj_count_diag = start_indexing;

120:     jj_count_offd = start_indexing;

121:

122:     if (num_cols_diag_B || num_cols_offd_C)

123:     B_marker = hypre_CTAlloc(HYPRE_Int, num_cols_diag_B+num_cols_offd_C);

124:     for (i1 = 0; i1 < num_cols_diag_B+num_cols_offd_C; i1++)

125:       B_marker[i1] = -1;

126:

127:     for (i1 = ns; i1 < ne; i1++)

[...]

135:       if ( allsquare ) {

136:          B_marker[i1] = jj_count_diag;

137:          jj_count_diag++;

[...]

144:       if (num_cols_offd_A)

145:       {

146:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

147:          {

148:             i2 = A_offd_j[jj2];

[...]

154:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

155:             {

156:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

164:                if (B_marker[i3] < jj_row_begin_offd)

165:                {

166:                   B_marker[i3] = jj_count_offd;

167:                   jj_count_offd++;

168:                }

169:             }

170:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

171:             {

172:                i3 = B_ext_diag_j[jj3];

173:

174:                if (B_marker[i3] < jj_row_begin_diag)

175:                {

176:                   B_marker[i3] = jj_count_diag;

177:                   jj_count_diag++;

[...]

187:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

188:       {

189:          i2 = A_diag_j[jj2];

[...]

195:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

196:          {

197:             i3 = B_diag_j[jj3];

[...]

205:             if (B_marker[i3] < jj_row_begin_diag)

206:             {

207:                B_marker[i3] = jj_count_diag;

208:                jj_count_diag++;

[...]

216:          if (num_cols_offd_B)

217:          {

218:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

219:             {

220:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

228:                if (B_marker[i3] < jj_row_begin_offd)

229:                {

230:                   B_marker[i3] = jj_count_offd;

231:                   jj_count_offd++;

[...]

241:       (*C_diag_i)[i1] = jj_row_begin_diag;

242:       (*C_offd_i)[i1] = jj_row_begin_offd;

243:

244:     }

245:     jj_count_diag_array[ii] = jj_count_diag;

246:     jj_count_offd_array[ii] = jj_count_offd;

247:

248:     hypre_TFree(B_marker);

249: #ifdef HYPRE_USING_OPENMP

250: #pragma omp barrier

251: #endif

252:

253:     if (ii)

254:     {

255:        jj_count_diag = jj_count_diag_array[0];

256:        jj_count_offd = jj_count_offd_array[0];

257:        for (i1 = 1; i1 < ii; i1++)

258:        {

259:           jj_count_diag += jj_count_diag_array[i1];

260:           jj_count_offd += jj_count_offd_array[i1];

261:        }

262:

263:        for (i1 = ns; i1 < ne; i1++)

264:        {

265:           (*C_diag_i)[i1] += jj_count_diag;

266:           (*C_offd_i)[i1] += jj_count_offd;

267:        }

268:     }

269:     else

270:     {

271:        (*C_diag_i)[num_rows_diag_A] = 0;

272:        (*C_offd_i)[num_rows_diag_A] = 0;

273:        for (i1 = 0; i1 < num_threads; i1++)

274:        {

275:           (*C_diag_i)[num_rows_diag_A] += jj_count_diag_array[i1];

276:           (*C_offd_i)[num_rows_diag_A] += jj_count_offd_array[i1];

0x47dce0 SUB	SP, SP, #224

0x47dce4 STP	X29, X30, [SP, #128]

0x47dce8 STP	X28, X27, [SP, #144]

0x47dcec STP	X26, X25, [SP, #160]

0x47dcf0 STP	X24, X23, [SP, #176]

0x47dcf4 STP	X22, X21, [SP, #192]

0x47dcf8 STP	X20, X19, [SP, #208]

0x47dcfc ADD	X29, SP, #128

0x47dd00 LDR	X8, [X29, #240]

0x47dd04 LDP	X20, X19, [X29, #216]

0x47dd08 STUR	X7, [X29, #504]

0x47dd0c ORR	X23, XZR, X6

0x47dd10 ORR	X22, XZR, X5

0x47dd14 ORR	X24, XZR, X4

0x47dd18 STR	X0, [SP, #24]

0x47dd1c ORR	X25, XZR, X3

0x47dd20 STR	X8, [SP, #48]

0x47dd24 LDR	X8, [X29, #232]

0x47dd28 ORR	X26, XZR, X2

0x47dd2c STR	X8, [SP, #40]

0x47dd30 BL	4a4720

0x47dd34 LDR	X8, [X26]

0x47dd38 LDR	X9, [X25]

0x47dd3c ADD	X10, X0, #1

0x47dd40 LDR	X27, [X24]

0x47dd44 CMP	X0, X8

0x47dd48 MADD	X11, X9, X0, X8

0x47dd4c MADD	X8, X9, X10, X8

0x47dd50 ADD	X9, X9, #1

0x47dd54 STR	X0, [SP, #32]

0x47dd58 MADD	X12, X9, X0, XZR

0x47dd5c MADD	X9, X9, X10, XZR

0x47dd60 CSEL	X6, X11, X12, #10

0x47dd64 CSEL	X11, X8, X9, #10

0x47dd68 LDR	X8, [X22]

0x47dd6c LDR	X9, [X23]

0x47dd70 STUR	X11, [X29, #496]

0x47dd74 ORR	X10, X8, X9

0x47dd78 CBNZ	X10, 47dd98

0x47dd7c ORR	X0, XZR, XZR

0x47dd80 CMP	X6, X11

0x47dd84 STR	X6, [SP, #16]

0x47dd88 B.LT	47ddf4

0x47dd8c ORR	X6, XZR, X27

0x47dd90 ORR	X24, XZR, X27

0x47dd94 B	47e09c

0x47dd98 ADD	X0, X9, X8

0x47dd9c MOVZ	W1, #8

0x47dda0 ORR	X21, XZR, X6

0x47dda4 BL	4a2570

0x47dda8 LDR	X8, [X22]

0x47ddac LDR	X9, [X23]

0x47ddb0 ADD	X8, X9, X8

0x47ddb4 CMP	X8, #1

0x47ddb8 B.LT	47dde0

0x47ddbc ORR	X8, XZR, XZR

0x47ddc0 MOVN	X9, #0

(56) 0x47ddc4 STR	X9, [X0, X8,LSL #3]

(56) 0x47ddc8 ADD	X8, X8, #1

(56) 0x47ddcc LDR	X10, [X22]

(56) 0x47ddd0 LDR	X11, [X23]

(56) 0x47ddd4 ADD	X10, X11, X10

(56) 0x47ddd8 CMP	X8, X10

(56) 0x47dddc B.LT	47ddc4

0x47dde0 LDUR	X11, [X29, #496]

0x47dde4 ORR	X6, XZR, X21

0x47dde8 CMP	X21, X11

0x47ddec STR	X21, [SP, #16]

0x47ddf0 B.GE	47dd8c

0x47ddf4 LDP	X8, X9, [X29, #200]

0x47ddf8 LDP	X12, X10, [X29, #144]

0x47ddfc ORR	X30, XZR, X27

0x47de00 LDP	X15, X16, [X29, #96]

0x47de04 STP	X20, X19, [SP]

0x47de08 LDR	X16, [X16]

0x47de0c STP	X8, X9, [X29, #984]

0x47de10 LDP	X11, X9, [X29, #184]

0x47de14 LDR	X8, [X29, #176]

0x47de18 STR	X12, [SP, #64]

0x47de1c LDP	X13, X12, [X29, #128]

0x47de20 LDR	X2, [X10]

0x47de24 STP	X8, X9, [X29, #968]

0x47de28 LDP	X9, X8, [X29, #160]

0x47de2c STR	X13, [SP, #56]

0x47de30 LDP	X14, X13, [X29, #112]

0x47de34 LDR	X1, [X12]

0x47de38 ADD	X23, X16, #8

0x47de3c STUR	X16, [X29, #488]

0x47de40 LDR	X4, [X8]

0x47de44 LDR	X8, [X20]

0x47de48 LDR	X17, [X14]

0x47de4c LDUR	X14, [X29, #496]

0x47de50 LDR	X18, [X13]

0x47de54 LDR	X3, [X9]

0x47de58 ORR	X20, XZR, X6

0x47de5c ORR	X6, XZR, X27

0x47de60 LDR	X5, [X8]

0x47de64 LDR	X8, [X19]

0x47de68 LDR	X7, [X8]

0x47de6c B	47dea0

0x47de70 HINT	#0

0x47de74 HINT	#0

0x47de78 HINT	#0

0x47de7c HINT	#0

    (49) 0x47de80 LDUR	X14, [X29, #496]

      (48) 0x47de84 STR	X30, [X5, X20,LSL #3]

      (48) 0x47de88 STR	X27, [X7, X20,LSL #3]

      (48) 0x47de8c ORR	X27, XZR, X24

      (48) 0x47de90 ORR	X30, XZR, X6

      (48) 0x47de94 ORR	X20, XZR, X25

      (48) 0x47de98 CMP	X25, X14

      (48) 0x47de9c B.EQ	47e098

      (48) 0x47dea0 LDUR	X8, [X29, #504]

      (48) 0x47dea4 LDR	X8, [X8]

      (48) 0x47dea8 CBZ	X8, 47deb4

      (48) 0x47deac ADD	X6, X30, #1

      (48) 0x47deb0 STR	X30, [X0, X20,LSL #3]

      (48) 0x47deb4 LDR	X8, [X15]

      (48) 0x47deb8 CBZ	X8, 47df80

      (48) 0x47debc LDUR	X8, [X29, #488]

      (48) 0x47dec0 LDR	X13, [X8, X20,LSL #3]

      (48) 0x47dec4 LDR	X8, [X23, X20,LSL #3]

      (48) 0x47dec8 CMP	X13, X8

      (48) 0x47decc B.GE	47df80

      (48) 0x47ded0 LDP	X8, X9, [SP, #56]

      (48) 0x47ded4 ORR	X24, XZR, X27

      (48) 0x47ded8 LDR	X8, [X8]

      (48) 0x47dedc LDR	X14, [X9]

      (48) 0x47dee0 B	47def4

        (52) 0x47dee4 LDR	X9, [X23, X20,LSL #3]

        (52) 0x47dee8 ADD	X13, X13, #1

        (52) 0x47deec CMP	X13, X9

        (52) 0x47def0 B.GE	47dfa0

        (52) 0x47def4 LDR	X10, [X17, X13,LSL #3]

        (52) 0x47def8 ADD	X9, X10, #1

        (52) 0x47defc LDR	X19, [X18, X10,LSL #3]

        (52) 0x47df00 LDR	X12, [X18, X9,LSL #3]

        (52) 0x47df04 B	47df0c

          (54) 0x47df08 ADD	X19, X19, #1

          (54) 0x47df0c CMP	X19, X12

          (54) 0x47df10 B.GE	47df40

          (54) 0x47df14 LDR	X16, [X22]

          (54) 0x47df18 LDR	X25, [X8, X19,LSL #3]

          (54) 0x47df1c ADD	X16, X16, X25

          (54) 0x47df20 LDR	X25, [X0, X16,LSL #3]

          (54) 0x47df24 CMP	X25, X27

          (54) 0x47df28 B.GE	47df08

          (54) 0x47df2c STR	X24, [X0, X16,LSL #3]

          (54) 0x47df30 ADD	X24, X24, #1

          (54) 0x47df34 LDR	X12, [X18, X9,LSL #3]

          (54) 0x47df38 B	47df08

0x47df3c HINT	#0

        (52) 0x47df40 LDR	X10, [X1, X10,LSL #3]

        (52) 0x47df44 LDR	X12, [X1, X9,LSL #3]

        (52) 0x47df48 B	47df50

          (53) 0x47df4c ADD	X10, X10, #1

          (53) 0x47df50 CMP	X10, X12

          (53) 0x47df54 B.GE	47dee4

          (53) 0x47df58 LDR	X16, [X14, X10,LSL #3]

          (53) 0x47df5c LDR	X19, [X0, X16,LSL #3]

          (53) 0x47df60 CMP	X19, X30

          (53) 0x47df64 B.GE	47df4c

          (53) 0x47df68 STR	X6, [X0, X16,LSL #3]

          (53) 0x47df6c ADD	X6, X6, #1

          (53) 0x47df70 LDR	X12, [X1, X9,LSL #3]

          (53) 0x47df74 B	47df4c

0x47df78 HINT	#0

0x47df7c HINT	#0

      (48) 0x47df80 ORR	X24, XZR, X27

      (48) 0x47df84 ADD	X25, X20, #1

      (48) 0x47df88 LDR	X28, [X2, X20,LSL #3]

      (48) 0x47df8c LDR	X8, [X2, X25,LSL #3]

      (48) 0x47df90 CMP	X28, X8

      (48) 0x47df94 B.GE	47de84

    (49) 0x47df98 B	47dfb8

0x47df9c HINT	#0

      (48) 0x47dfa0 LDUR	X14, [X29, #496]

      (48) 0x47dfa4 ADD	X25, X20, #1

      (48) 0x47dfa8 LDR	X28, [X2, X20,LSL #3]

      (48) 0x47dfac LDR	X8, [X2, X25,LSL #3]

      (48) 0x47dfb0 CMP	X28, X8

      (48) 0x47dfb4 B.GE	47de84

    (49) 0x47dfb8 LDUR	X8, [X29, #456]

    (49) 0x47dfbc LDR	X13, [X8]

    (49) 0x47dfc0 LDUR	X8, [X29, #464]

    (49) 0x47dfc4 LDR	X14, [X8]

    (49) 0x47dfc8 LDUR	X8, [X29, #472]

    (49) 0x47dfcc LDR	X19, [X8]

    (49) 0x47dfd0 LDUR	X8, [X29, #480]

    (49) 0x47dfd4 LDR	X8, [X8]

    (49) 0x47dfd8 B	47dff0

0x47dfdc HINT	#0

    (49) 0x47dfe0 LDR	X9, [X2, X25,LSL #3]

    (49) 0x47dfe4 ADD	X28, X28, #1

    (49) 0x47dfe8 CMP	X28, X9

    (49) 0x47dfec B.GE	47de80

    (49) 0x47dff0 LDR	X10, [X3, X28,LSL #3]

    (49) 0x47dff4 ADD	X9, X10, #1

    (49) 0x47dff8 LDR	X12, [X4, X10,LSL #3]

    (49) 0x47dffc LDR	X16, [X4, X9,LSL #3]

    (49) 0x47e000 B	47e008

      (51) 0x47e004 ADD	X12, X12, #1

      (51) 0x47e008 CMP	X12, X16

      (51) 0x47e00c B.GE	47e040

      (51) 0x47e010 LDR	X26, [X13, X12,LSL #3]

      (51) 0x47e014 LDR	X21, [X0, X26,LSL #3]

      (51) 0x47e018 CMP	X21, X30

      (51) 0x47e01c B.GE	47e004

      (51) 0x47e020 STR	X6, [X0, X26,LSL #3]

      (51) 0x47e024 ADD	X6, X6, #1

      (51) 0x47e028 LDR	X16, [X4, X9,LSL #3]

      (51) 0x47e02c B	47e004

0x47e030 HINT	#0

0x47e034 HINT	#0

0x47e038 HINT	#0

0x47e03c HINT	#0

    (49) 0x47e040 LDR	X12, [X11]

    (49) 0x47e044 CBZ	X12, 47dfe0

  (50) 0x47e048 LDR	X10, [X14, X10,LSL #3]

  (50) 0x47e04c LDR	X12, [X14, X9,LSL #3]

  (50) 0x47e050 B	47e064

0x47e054 HINT	#0

0x47e058 HINT	#0

0x47e05c HINT	#0

(55) 0x47e060 ADD	X10, X10, #1

  (50) 0x47e064 CMP	X10, X12

  (50) 0x47e068 B.GE	47dfe0

(55) 0x47e06c LDR	X21, [X8, X10,LSL #3]

(55) 0x47e070 LDR	X16, [X22]

(55) 0x47e074 LDR	X21, [X19, X21,LSL #3]

(55) 0x47e078 ADD	X16, X16, X21

(55) 0x47e07c LDR	X21, [X0, X16,LSL #3]

(55) 0x47e080 CMP	X21, X27

(55) 0x47e084 B.GE	47e060

(55) 0x47e088 STR	X24, [X0, X16,LSL #3]

(55) 0x47e08c ADD	X24, X24, #1

(55) 0x47e090 LDR	X12, [X14, X9,LSL #3]

(55) 0x47e094 B	47e060

0x47e098 LDP	X20, X19, [SP]

0x47e09c LDP	X22, X21, [SP, #40]

0x47e0a0 LDP	X25, X23, [SP, #24]

0x47e0a4 LDR	X8, [X22]

0x47e0a8 STR	X6, [X8, X23,LSL #3]

0x47e0ac LDR	X8, [X21]

0x47e0b0 STR	X24, [X8, X23,LSL #3]

0x47e0b4 BL	4a2670

0x47e0b8 LDR	W1, [X25]

0x47e0bc ADRP	X0,

0x47e0c0 ADD	X0, X0, #2696

0x47e0c4 BL	40f4b0

0x47e0c8 CBZ	X23, 47e104

0x47e0cc LDR	X10, [X22]

0x47e0d0 LDR	X11, [X21]

0x47e0d4 LDUR	X14, [X29, #496]

0x47e0d8 CMP	X23, #2

0x47e0dc LDR	X8, [X10]

0x47e0e0 LDR	X9, [X11]

0x47e0e4 B.LT	47e180

0x47e0e8 LDR	X18, [SP, #16]

0x47e0ec SUB	X12, X23, #1

0x47e0f0 CMP	X23, #2

0x47e0f4 B.NE	47e188

0x47e0f8 MOVZ	W13, #1

0x47e0fc TBNZ	W12, #0, 47e1dc

0x47e100 B	47e1ec

0x47e104 LDR	X8, [X29, #248]

0x47e108 LDR	X9, [X20]

0x47e10c LDR	X11, [X19]

0x47e110 LDR	X9, [X9]

0x47e114 LDR	X10, [X8]

0x47e118 LDR	X11, [X11]

0x47e11c STR	XZR, [X9, X10,LSL #3]

0x47e120 LDR	X10, [X29, #256]

0x47e124 LDR	X12, [X8]

0x47e128 STR	XZR, [X11, X12,LSL #3]

0x47e12c LDR	X12, [X10]

0x47e130 CMP	X12, #1

0x47e134 B.LT	47e240

0x47e138 LDR	X13, [X22]

0x47e13c LDR	X14, [X21]

0x47e140 ORR	X12, XZR, XZR

(45) 0x47e144 LDR	X16, [X8]

(45) 0x47e148 LDR	X15, [X13, X12,LSL #3]

(45) 0x47e14c LDR	X17, [X9, X16,LSL #3]

(45) 0x47e150 ADD	X15, X17, X15

(45) 0x47e154 STR	X15, [X9, X16,LSL #3]

(45) 0x47e158 LDR	X16, [X8]

(45) 0x47e15c LDR	X15, [X14, X12,LSL #3]

(45) 0x47e160 ADD	X12, X12, #1

(45) 0x47e164 LDR	X17, [X11, X16,LSL #3]

(45) 0x47e168 ADD	X15, X17, X15

(45) 0x47e16c STR	X15, [X11, X16,LSL #3]

(45) 0x47e170 LDR	X15, [X10]

(45) 0x47e174 CMP	X12, X15

(45) 0x47e178 B.LT	47e144

0x47e17c B	47e240

0x47e180 LDR	X18, [SP, #16]

0x47e184 B	47e1ec

0x47e188 AND	X14, X12, #8127

0x47e18c ORR	X13, XZR, XZR

0x47e190 ADD	X15, X10, #16

0x47e194 ADD	X16, X11, #16

0x47e198 SUB	X14, XZR, X14

0x47e19c HINT	#0

(47) 0x47e1a0 LDUR	X17, [X15, #504]

(47) 0x47e1a4 SUB	X13, X13, #2

(47) 0x47e1a8 CMP	X14, X13

(47) 0x47e1ac ADD	X8, X17, X8

(47) 0x47e1b0 LDUR	X17, [X16, #504]

(47) 0x47e1b4 ADD	X9, X17, X9

(47) 0x47e1b8 LDR	X17, [X15], #16

(47) 0x47e1bc ADD	X8, X17, X8

(47) 0x47e1c0 LDR	X17, [X16], #16

(47) 0x47e1c4 ADD	X9, X17, X9

(47) 0x47e1c8 B.NE	47e1a0

0x47e1cc MOVZ	W14, #1

0x47e1d0 SUB	X13, X14, X13

0x47e1d4 LDUR	X14, [X29, #496]

0x47e1d8 TBZ	W12, #0, 47e1ec

0x47e1dc LDR	X10, [X10, X13,LSL #3]

0x47e1e0 ADD	X8, X10, X8

0x47e1e4 LDR	X10, [X11, X13,LSL #3]

0x47e1e8 ADD	X9, X10, X9

0x47e1ec CMP	X18, X14

0x47e1f0 B.GE	47e240

0x47e1f4 LDR	X10, [X20]

0x47e1f8 UBFM	X13, X18, #61, #60

0x47e1fc LDR	X12, [X10]

0x47e200 LDR	X10, [X19]

0x47e204 LDR	X11, [X10]

0x47e208 SUB	X10, X14, X18

0x47e20c ADD	X12, X12, X13

0x47e210 ADD	X11, X11, X13

0x47e214 HINT	#0

0x47e218 HINT	#0

0x47e21c HINT	#0

(46) 0x47e220 LDR	X13, [X12]

(46) 0x47e224 SUBS	X10, X10, #1

(46) 0x47e228 ADD	X13, X13, X8

(46) 0x47e22c STR	X13, [X12], #8

(46) 0x47e230 LDR	X13, [X11]

(46) 0x47e234 ADD	X13, X13, X9

(46) 0x47e238 STR	X13, [X11], #8

(46) 0x47e23c B.NE	47e220

0x47e240 LDP	X20, X19, [SP, #208]

0x47e244 LDP	X22, X21, [SP, #192]

0x47e248 LDP	X24, X23, [SP, #176]

0x47e24c LDP	X26, X25, [SP, #160]

0x47e250 LDP	X28, X27, [SP, #144]

0x47e254 LDP	X29, X30, [SP, #128]

0x47e258 ADD	SP, SP, #224

0x47e25c RET

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_csr_matop.c:102-276
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:102,108-127,135-137,144-148,154-156,164-177,187-189,195-197,205-208,216-220,228-231,241-276.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 30.67 to 3.83 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 30.67 to 2.00 cycles (15.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 676 bytes. The binary function is storing 264 bytes.

General properties

nb instructions	190
loop length	760
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

21.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	10.50	10.50	15.25	15.25	15.25	15.25	0.00	0.00	0.00	0.00	30.67	30.67	30.67	12.00	12.00
cycles	10.50	10.50	15.25	15.25	15.25	15.25	0.00	0.00	0.00	0.00	30.67	30.67	30.67	12.00	12.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.25
Overall L1	30.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 30.67 cycles. At this rate:

22% of peak load performance is reached (22.04 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.61 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 47dce0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X20, X19, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X7, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X0, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a4720 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X27, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X11, X9, X0, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X8, X9, X10, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X0, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X12, X9, X0, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X9, X9, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CSEL X6, X11, X12, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X11, X8, X9, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X11, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X10, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ X10, 47dd98 <.omp_outlined.+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X6, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STR X6, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LT 47ddf4 <.omp_outlined.+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X6, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47e09c <.omp_outlined.+0x3bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 47dde0 <.omp_outlined.+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X11, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X6, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X21, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STR X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.GE 47dd8c <.omp_outlined.+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X10, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X30, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X15, X16, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X20, X19, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X11, X9, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X12, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X13, X12, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X2, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X9, X8, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X13, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X14, X13, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X1, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X23, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X16, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X14, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X20, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X6, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47dea0 <.omp_outlined.+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X23, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X6, [X8, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X24, [X8, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W1, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4de0bc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2696	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X23, 47e104 <.omp_outlined.+0x424>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X14, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X23, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.LT 47e180 <.omp_outlined.+0x4a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X12, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X23, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47e188 <.omp_outlined.+0x4a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBNZ W12, #0, 47e1dc <.omp_outlined.+0x4fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 47e1ec <.omp_outlined.+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X11, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 47e240 <.omp_outlined.+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X12, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47e240 <.omp_outlined.+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47e1ec <.omp_outlined.+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
AND X14, X12, #8127	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X13, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X14, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
MOVZ W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, X14, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X14, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
TBZ W12, #0, 47e1ec <.omp_outlined.+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X10, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X11, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47e240 <.omp_outlined.+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X13, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X10, X14, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	par_csr_matop.c:102-276
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 30.67 to 2.00 cycles (15.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 676 bytes. The binary function is storing 264 bytes.

General properties

nb instructions	190
loop length	760
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

21.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	10.50	10.50	15.25	15.25	15.25	15.25	0.00	0.00	0.00	0.00	30.67	30.67	30.67	12.00	12.00
cycles	10.50	10.50	15.25	15.25	15.25	15.25	0.00	0.00	0.00	0.00	30.67	30.67	30.67	12.00	12.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.25
Overall L1	30.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 30.67 cycles. At this rate:

22% of peak load performance is reached (22.04 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.61 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 47dce0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X20, X19, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X7, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X0, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a4720 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X27, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X11, X9, X0, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X8, X9, X10, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X0, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X12, X9, X0, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X9, X9, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CSEL X6, X11, X12, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X11, X8, X9, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X11, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X10, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ X10, 47dd98 <.omp_outlined.+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X6, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STR X6, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LT 47ddf4 <.omp_outlined.+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X6, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47e09c <.omp_outlined.+0x3bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 47dde0 <.omp_outlined.+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X11, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X6, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X21, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STR X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.GE 47dd8c <.omp_outlined.+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X10, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X30, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X15, X16, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X20, X19, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X11, X9, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X12, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X13, X12, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X2, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X9, X8, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X13, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X14, X13, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X1, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X23, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X16, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X14, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X20, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X6, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47dea0 <.omp_outlined.+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X23, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X6, [X8, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X24, [X8, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W1, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4de0bc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2696	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X23, 47e104 <.omp_outlined.+0x424>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X14, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X23, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.LT 47e180 <.omp_outlined.+0x4a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X12, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X23, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47e188 <.omp_outlined.+0x4a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBNZ W12, #0, 47e1dc <.omp_outlined.+0x4fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 47e1ec <.omp_outlined.+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X11, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 47e240 <.omp_outlined.+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X12, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47e240 <.omp_outlined.+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 47e1ec <.omp_outlined.+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
AND X14, X12, #8127	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X13, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X14, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
MOVZ W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, X14, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X14, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
TBZ W12, #0, 47e1ec <.omp_outlined.+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X10, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X11, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 47e240 <.omp_outlined.+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X13, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X10, X14, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼.omp_outlined.#0x47dce0–	0.76	0.29
○Loop 46 - par_csr_matop.c:263-266 - exec	0.03	0.01
○Loop 47 - par_csr_matop.c:257-260 - exec	0	0
▼Loop 55 - par_csr_matop.c:127-242 - exec–	0	0
▼Loop 50 - par_csr_matop.c:127-242 - exec–	0	0
▼Loop 49 - par_csr_matop.c:127-242 - exec–	0.21	0.07
○Loop 51 - par_csr_matop.c:195-208 - exec	0.48	0.16
▼Loop 48 - par_csr_matop.c:127-242 - exec–	0.04	0.02
▼Loop 52 - par_csr_matop.c:146-177 - exec–	0	0
○Loop 53 - par_csr_matop.c:170-177 - exec	0	0
○Loop 54 - par_csr_matop.c:154-167 - exec	0	0
○Loop 45 - par_csr_matop.c:273-276 - exec	0	0
○Loop 56 - par_csr_matop.c:124-125 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code