	*************************************************
	*                                               *
	*          ONE-View report generation           *
	*                                               *
	*************************************************

[MAQAO] Info: Experiment configuration summary is available adding -dbg=1 in command line

* [MAQAO] Warning: Experiment directory /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9639/intel/AMG/run/oneview_runs/compilers/gcc_2/oneview_results_1786695611 already exists and is reused.
           It can be replaced using --replace in the command line.
[MAQAO] Info: 
[MAQAO] Info: START THE APPLICATION PROFILING
[MAQAO] Info: -> RUNNING THE PROFILER...
[MAQAO] Info:   LPROF has already been run
[MAQAO] Info: STOP THE APPLICATION PROFILING
[MAQAO] Info: 
[MAQAO] Info: START FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: STOP FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: 
[MAQAO] Info: START THE REPORT GENERATION
[MAQAO] Info: -> ONE-VIEW EXPERIMENT DIRECTORY: /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9639/intel/AMG/run/oneview_runs/compilers/gcc_2/oneview_results_1786695611


+====================================================================================================================+
+                                                    1  -  GLOBAL                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             1.1  -  Experiment Summary                                             +
+--------------------------------------------------------------------------------------------------------------------+

  Application:			/beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9639/intel/AMG/run/binaries/gcc_2/exec
  Timestamp:			2026-08-14 10:20:11
  Universal Timestamp:		1786695611
  Experiment Type:		MPI; OpenMP; Throughput; 
  Machine:			isix07.benchmarkcenter.megware.com
  Architecture:			x86_64
  Micro Architecture:		GRANITE_RAPIDS
  Model Name:			Intel(R) Xeon(R) 6972P
  Cache Size:			491520 KB
  Number of Cores:		96
  OS Version:			Linux 5.14.0-687.31.1.el9_8.x86_64 #1 SMP PREEMPT_DYNAMIC Sat Aug 1 05:38:01 EDT 2026
  Compilation Options:		
		exec: GNU C89 15.1.0 -march=graniterapids -mprefer-vector-width=512 -g -O3 -O3 -std=gnu90 -ffast-math -fno-omit-frame-pointer -fcf-protection=none -fopenmp -funroll-loops 
  Number of processes observed:	6
  Number of threads observed:	192
  MAQAO version:		2026.1.0
  MAQAO build:			6d1be1d51c1e63266254997eb301734a7264775d::20260810-150026




+--------------------------------------------------------------------------------------------------------------------+
+                                               1.2  -  Global Metrics                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Total Time:				47.63 s
  Max (Thread Active Time):		46.86 s
  Average Active Time:			39.35 s
  Activity Ratio:			83.4 %
  Average number of active threads:	158.648
  Affinity Stability:			99.5 %
  Time spent in analyzed loops:		93.7 %
  Time spent in analyzed innermost loops: 17.0 %
  Time spent in user code:		93.7 %
  Compilation Options Score:		100
  Array Access Efficiency:		77.3 %

   Potential Speedups
  ----------------------------------------------------
  Perfect Flow Complexity:		1.03
  Perfect OpenMP/MPI/Pthread/TBB:	1.03
  Perfect OpenMP/MPI/Pthread/TBB + Load Distribution:	1.23
  If No Scalar Integer:
      Potential Speedup:		1.12
      Nb Loops to get 80%:		8
  If FP Vectorized:
      Potential Speedup:		1.02
      Nb Loops to get 80%:		5
  If Fully Vectorized:
      Potential Speedup:		1.29
      Nb Loops to get 80%:		22
  If Only FP Arithmetic:
      Potential Speedup:		2.36
      Nb Loops to get 80%:		12




+--------------------------------------------------------------------------------------------------------------------+
+                                             1.3  -  Potential Speedups                                             +
+--------------------------------------------------------------------------------------------------------------------+

  If No Scalar Integer:
      Number of loops   | 1      | 10     | 20     | 29     | 40     | 
      Cumulated Speedup | 1.0573 | 1.1008 | 1.1135 | 1.1154 | 1.1156 | 
  Top 5 loops:
    exec - 2137:	1.0573
    exec - 3138:	1.0672
    exec - 3147:	1.0733
    exec - 10:	1.0784
    exec - 2856:	1.0828

  If FP Vectorized:
      Number of loops   | 1      | 10     | 20     | 29     | 40     | 
      Cumulated Speedup | 1.0051 | 1.0206 | 1.0208 | 1.0208 | 1.0208 | 
  Top 5 loops:
    exec - 656:	1.0051
    exec - 3147:	1.0099
    exec - 2497:	1.014
    exec - 670:	1.0164
    exec - 3014:	1.0187

  If Fully Vectorized:
      Number of loops   | 1      | 10     | 20     | 29     | 40     | 
      Cumulated Speedup | 1.0518 | 1.1456 | 1.2234 | 1.2600 | 1.2755 | 
  Top 5 loops:
    exec - 2137:	1.0518
    exec - 3138:	1.0645
    exec - 3147:	1.0769
    exec - 3121:	1.0891
    exec - 656:	1.0986

  If Only FP Arithmetic:
      Number of loops   | 1      | 10     | 20     | 29     | 40     | 
      Cumulated Speedup | 1.4668 | 2.0599 | 2.2059 | 2.2752 | 2.3138 | 
  Top 5 loops:
    exec - 2137:	1.4668
    exec - 3138:	1.656
    exec - 3121:	1.8692
    exec - 3130:	1.9129
    exec - 2136:	1.9565



+====================================================================================================================+
+                                                   2  -  SUMMARY                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             2.1  -  EXPERIMENT QUALITY                                             +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Application profile is long enough (46.86 s)
To have good quality measurements, it is advised that the application profiling time is greater than 10 seconds.

  [3 / 3] Most of time spent in analyzed modules comes from functions with source/debug info
-g option gives access to debugging informations, such are source locations.

  [2.9965884969707 / 3] Most of time spent in analyzed modules (99.89%) comes from functions compiled with architecture specialization option
-march=graniterapids


  [3 / 3] Most of time spent in analyzed modules comes from functions with compilation options informations and
-fno-omit-frame-pointer is present
-fno-omit-frame-pointer improves the accuracy of callchains found during the application profiling.

  [3 / 3] Optimization level option is correctly used


  [3 / 3] Host configuration allows retrieval of all necessary metrics.


  [2 / 2] Application is correctly profiled ("Others" category represents 0.00 % of the execution time)
To have a representative profiling, it is advised that the category "Others" represents less than 20% of the execution
time in order to analyze as much as possible of the user code

  [1 / 1] Lstopo present. The Topology lstopo report will be generated.



+--------------------------------------------------------------------------------------------------------------------+
+                                                2.2  -  CODE QUALITY                                                +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Enough time of the experiment time spent in analyzed loops (93.65%)
If the time spent in analyzed loops is less than 30%, standard loop optimizations will have a limited impact on
application performances.

  [3 / 4] A significant amount of threads are idle (17.37%)
On average, more than 10% of observed threads are idle. Such threads are probably IO/sync waiting. Some hints: use
faster filesystems to read/write data, improve parallel load balancing and/or scheduling.

  [3 / 4] CPU activity is below 90% (83.35%)
CPU cores are idle more than 10% of time. Threads supposed to run on these cores are probably IO/sync waiting. Some
hints: use faster filesystems to read/write data, improve parallel load balancing and/or scheduling.

  [4 / 4] Loop profile is not flat
At least one loop coverage is greater than 4% (45.26%), representing an hotspot for the application

  [4 / 4] Enough time of the experiment time spent in analyzed innermost loops (17.00%)
If the time spent in analyzed innermost loops is less than 15%, standard innermost loop optimizations such as
vectorisation will have a limited impact on application performances.

  [4 / 4] Affinity is good (99.54%)
Threads are not migrating to CPU cores: probably successfully pinned

  [3 / 3] Less than 10% (0.00%) is spend in BLAS1 operations
It could be more efficient to inline by hand BLAS1 operations

  [0 / 3] Too many functions do not use all threads
Functions running on a reduced number of threads (typically sequential code) cover at least 10% of application
walltime (17.00%). Check both "Max Inclusive Time Over Threads" and "Nb Threads" in Functions or Loops tabs and
consider parallelizing sequential regions or improving parallelization of regions running on a reduced number of
threads

  [0 / 3] Cumulative Outermost/In between loops coverage (76.66%) greater than cumulative innermost loop coverage (17.00%)
Having cumulative Outermost/In between loops coverage greater than cumulative innermost loop coverage will make loop
optimization more complex

  [2 / 2] Less than 10% (0.00%) is spend in BLAS2 operations
BLAS2 calls usually could make a poor cache usage and could benefit from inlining.

  [2 / 2] Less than 10% (0.00%) is spend in Libm/SVML (special functions)



+--------------------------------------------------------------------------------------------------------------------+
+                                               2.3  -  LOOPS OVERVIEW                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Top 5 loops:
   + exec - 2137:
     analysis: Execution Time: 45 % - Vectorization Ratio: 59.20 % - Vector Length Use: 47.10 %
     Loop Computation Issues: 6
        [4] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 1
            issues (= instructions) costing 4 points each.
        [2] [SA] Presence of a large number of scalar integer instructions - Simplify loop structure, perform loop
            splitting or perform unroll and jam. This issue costs 2 points.
     Control Flow Issues: 1002
        [1000] [SA] Too many paths (16385 paths) - Simplify control structure. There are 16385 issues ( = paths) costing
            1 point, limited to 1000.
        [2] [SA] Non innermost loop (Outermost) - Collapse loop with innermost ones. This issue costs 2 points.
     Data Access Issues: 74
        [64] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 16 issues (=
            instructions) costing 4 points each.
        [10] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE) - Simplify
            data access and try to get stride 1 access. There are 10 issues (= instructions) costing 1 point each.
     Vectorization Roadblocks: 1002
        [1000] [SA] Too many paths (16385 paths) - Simplify control structure. There are 16385 issues ( = paths) costing
            1 point, limited to 1000.
        [2] [SA] Non innermost loop (Outermost) - Collapse loop with innermost ones. This issue costs 2 points.
     Inefficient Vectorization: 74
        [64] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 16 issues (=
            instructions) costing 4 points each.
        [10] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE) - Simplify
            data access and try to get stride 1 access. There are 10 issues (= instructions) costing 1 point each.

   + exec - 3138:
     analysis: Execution Time: 11 % - Vectorization Ratio: 60.66 % - Vector Length Use: 47.95 %
     Control Flow Issues: 134
        [132] [SA] Too many paths (128 paths) - Simplify control structure. There are 128 issues ( = paths) costing 1
            point each with a malus of 4 points.
        [2] [SA] Non innermost loop (Outermost) - Collapse loop with innermost ones. This issue costs 2 points.
     Data Access Issues: 37
        [32] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 8 issues (=
            instructions) costing 4 points each.
        [5] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE) - Simplify
            data access and try to get stride 1 access. There are 5 issues (= instructions) costing 1 point each.
     Vectorization Roadblocks: 134
        [132] [SA] Too many paths (128 paths) - Simplify control structure. There are 128 issues ( = paths) costing 1
            point each with a malus of 4 points.
        [2] [SA] Non innermost loop (Outermost) - Collapse loop with innermost ones. This issue costs 2 points.
     Inefficient Vectorization: 37
        [32] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 8 issues (=
            instructions) costing 4 points each.
        [5] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE) - Simplify
            data access and try to get stride 1 access. There are 5 issues (= instructions) costing 1 point each.

   + exec - 3121:
     analysis: Execution Time: 10 % - Vectorization Ratio: 59.32 % - Vector Length Use: 48.62 %
     Control Flow Issues: 2
        [2] [SA] Non innermost loop (InBetween) - Collapse loop with innermost ones. This issue costs 2 points.
     Data Access Issues: 37
        [32] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 8 issues (=
            instructions) costing 4 points each.
        [5] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE) - Simplify
            data access and try to get stride 1 access. There are 5 issues (= instructions) costing 1 point each.
     Vectorization Roadblocks: 1002
        [1000] [SA] Too many paths (at least 1000 paths) - Simplify control structure. There are at least 1000 issues ( =
            paths) costing 1 point.
        [2] [SA] Non innermost loop (InBetween) - Collapse loop with innermost ones. This issue costs 2 points.
     Inefficient Vectorization: 37
        [32] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 8 issues (=
            instructions) costing 4 points each.
        [5] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE) - Simplify
            data access and try to get stride 1 access. There are 5 issues (= instructions) costing 1 point each.

   + exec - 3130:
     analysis: Execution Time: 1 % - Vectorization Ratio: 60.66 % - Vector Length Use: 47.95 %
     Control Flow Issues: 134
        [132] [SA] Too many paths (128 paths) - Simplify control structure. There are 128 issues ( = paths) costing 1
            point each with a malus of 4 points.
        [2] [SA] Non innermost loop (Outermost) - Collapse loop with innermost ones. This issue costs 2 points.
     Data Access Issues: 37
        [32] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 8 issues (=
            instructions) costing 4 points each.
        [5] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE) - Simplify
            data access and try to get stride 1 access. There are 5 issues (= instructions) costing 1 point each.
     Vectorization Roadblocks: 134
        [132] [SA] Too many paths (128 paths) - Simplify control structure. There are 128 issues ( = paths) costing 1
            point each with a malus of 4 points.
        [2] [SA] Non innermost loop (Outermost) - Collapse loop with innermost ones. This issue costs 2 points.
     Inefficient Vectorization: 37
        [32] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 8 issues (=
            instructions) costing 4 points each.
        [5] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE) - Simplify
            data access and try to get stride 1 access. There are 5 issues (= instructions) costing 1 point each.

   + exec - 3182:
     analysis: Execution Time: 1 % - Vectorization Ratio: 100.00 % - Vector Length Use: 100.00 %



+====================================================================================================================+
+                                                 3  -  APPLICATION                                                  +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                               3.1  -  Categorization                                               +
+--------------------------------------------------------------------------------------------------------------------+

   Category | IO     | Exe    | System  | Others  | Memory | String | MPI   | TBB   | OMP   | Pthread | Math  |
  ----------+--------+--------+---------+---------+--------+--------+-------+-------+-------+---------+-------+
   Time (%) | 0.00   | 93.69  | 3.22    | 0.00    | 0.00   | 0.18   | 0.04  | 0.00  | 2.87  | 0.00    | 0.00  |




+--------------------------------------------------------------------------------------------------------------------+
+                                          3.2  -  Function Based Profiling                                          +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Functions              | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 2                         | 68.77                     | 68.77                     |
   4% to 8%                   | 0                         | 0.00                      | 68.77                     |
   2% to 4%                   | 2                         | 5.25                      | 74.02                     |
   1% to 2%                   | 12                        | 17.56                     | 91.58                     |
   0.5% to 1%                 | 6                         | 4.55                      | 96.13                     |
   0.25% to 0.5%              | 7                         | 2.55                      | 98.68                     |
   0.125% to 0.25%            | 4                         | 0.72                      | 99.40                     |
   < 0.125%                   | 127                       | 0.60                      | 100.00                    |




+--------------------------------------------------------------------------------------------------------------------+
+                                            3.3  -  Loop Based Profiling                                            +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Loops                  | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 0                         | 0.00                      | 0.00                      |
   4% to 8%                   | 0                         | 0.00                      | 0.00                      |
   2% to 4%                   | 0                         | 0.00                      | 0.00                      |
   1% to 2%                   | 2                         | 3.27                      | 3.27                      |
   0.5% to 1%                 | 13                        | 9.08                      | 12.34                     |
   0.25% to 0.5%              | 6                         | 2.29                      | 14.63                     |
   0.125% to 0.25%            | 5                         | 0.93                      | 15.56                     |
   < 0.125%                   | 169                       | 1.43                      | 17.00                     |


+====================================================================================================================+
+                                                  4  -  FUNCTIONS                                                   +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                              4.1  -  Top 10 Functions                                              +
+--------------------------------------------------------------------------------------------------------------------+

   Function                                               | Module              | Coverage (%)   | Time (s)       |
  --------------------------------------------------------+---------------------+----------------+----------------+
   hypre_ParCSRRelaxThreads._omp_fn.1                     | exec                | 45.46          | 17.89          |
   hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6              | exec                | 23.31          | 9.17           |
   unknown_kernel_region                                  | kernel              | 3.23           | 1.27           |
   hypre_BoomerAMGCreate2ndS._omp_fn.7                    | exec                | 2.03           | 0.80           |
   hypre_SeqVectorAxpy._omp_fn.0                          | exec                | 1.72           | 0.68           |
   hypre_BoomerAMGBuildMultipass._omp_fn.5                | exec                | 1.70           | 0.67           |
   gomp_barrier_wait_end                                  | libgomp.so.1.0.0    | 1.70           | 0.68           |
   hypre_BoomerAMGBuildMultipass._omp_fn.10               | exec                | 1.62           | 0.64           |
   hypre_BoomerAMGCreateS._omp_fn.1                       | exec                | 1.61           | 0.63           |
   hypre_ParCSRRelaxThreads._omp_fn.0                     | exec                | 1.55           | 0.61           |


+====================================================================================================================+
+                                                    5  -  LOOPS                                                     +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                5.1  -  Top 10 Loops                                                +
+--------------------------------------------------------------------------------------------------------------------+

   Loop Id        | Module              | Source Location                                        | Coverage (%)   |
  ----------------+---------------------+--------------------------------------------------------+----------------+
   2137           | exec                | ams.c:3669-3682                                        | 45.26          |
   3138           | exec                | csr_matvec.c:307-314                                   | 11.34          |
   3121           | exec                | csr_matvec.c:256-263                                   | 10.14          |
   3130           | exec                | csr_matvec.c:334-341                                   | 1.78           |
   3182           | exec                | vector.c:452-452                                       | 1.72           |
   2136           | exec                | ams.c:3659-3659                                        | 1.55           |
   3147           | exec                | csr_matvec.c:564-564,csr_matvec.c:567-567              | 1.24           |
   2856           | exec                | IJMatrix_parcsr.c:3378-3378,IJMatrix_parcsr.c:3383-... | 1.19           |
   656            | exec                | par_multi_interp.c:1811-1811,par_multi_interp.c:181... | 0.91           |
   2497           | exec                | par_csr_matop.c:946-948,par_csr_matop.c:956-965        | 0.88           |





+====================================================================================================================+
+                                                     6  -  CQA                                                      +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                   6.1  -  Loops                                                    +
+--------------------------------------------------------------------------------------------------------------------+





      6.1.1  -  Loop 2137 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9639/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3669-3682.

Warnings:
 - Non-innermost loop: analyzing only self part (ignoring child loops).
 - Ignoring paths for analysis
 - Too many paths. If you really need to analyze all of the 16385 paths individually, rerun with max-paths=16385
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 16385 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.1.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

13% of peak computational performance is used (4.42 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 64.00 to 56.33 cycles (1.14x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.1.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
Only 47% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 64.00 to 57.04 cycles (1.12x speedup).

Details
59% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 73% of SSE/AVX loads are used in vector version.
 - 0% of SSE/AVX stores are used in vector version.
 - 66% of SSE/AVX addition or subtraction instructions are used in vector version.
 - 0% of SSE/AVX multiply instructions are used in vector version.
 - 72% of SSE/AVX fused multiply-add instructions are used in vector version.
 - 0% of SSE/AVX divide and square root instructions are used in vector version.
 - 51% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.1.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by reading data from caches/RAM (load units are a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 64.00 to 60.83 cycles (1.05x speedup).


Workaround
 - Read less array elements
All SSE and/or AVX registers are used:
in that case, try to relax register pressure by reducing the unroll factor or splitting your loop
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop
  * use the 'restrict' C99 keyword





      6.1.1.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 126 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.1.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VCOMISD: 1 occurrences<<list_path_1_complex_1>>
 - VGATHERQPD: 16 occurrences<<list_path_1_complex_2>>



      6.1.1.1.6  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses). By removing them, you can lower the cost of an iteration from 64.00 to 50.17 cycles (1.28x speedup).

Details
 - VGATHERQPD: 16 occurrences<<list_path_1_gather_scatter_1>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.1.1.7  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

14 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).
4 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).
14 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.1.1.8  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 283 FP arithmetical operations:
 - 155: addition or subtraction (126 inside FMA instructions)
 - 127: multiply (126 inside FMA instructions)
 - 1: divide
The binary loop is loading 3200 bytes (400 double precision FP elements).
The binary loop is storing 8 bytes (1 double precision FP elements).


      6.1.1.1.9  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.







      6.1.2  -  Loop 3138 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9639/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:307-314.

Warnings:
 - Non-innermost loop: analyzing only self part (ignoring child loops).
 - Ignoring paths for analysis
 - Too many paths. If you really need to analyze all of the 128 paths individually, rerun with max-paths=128
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 128 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.2.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

14% of peak computational performance is used (4.62 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.2.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 30.33 to 28.00 cycles (1.08x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.2.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
Only 47% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 30.33 to 27.29 cycles (1.11x speedup).

Details
60% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 77% of SSE/AVX loads are used in vector version.
 - 0% of SSE/AVX stores are used in vector version.
 - 71% of SSE/AVX addition or subtraction instructions are used in vector version.
 - 72% of SSE/AVX fused multiply-add instructions are used in vector version.
 - 53% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.2.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by reading data from caches/RAM (load units are a bottleneck).


Workaround
 - Read less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop
  * use the 'restrict' C99 keyword





      6.1.2.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 63 FMA (fused multiply-add) operations.




      6.1.2.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VGATHERQPD: 8 occurrences<<list_path_1_complex_1>>



      6.1.2.1.6  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses). By removing them, you can lower the cost of an iteration from 30.33 to 23.67 cycles (1.28x speedup).

Details
 - VGATHERQPD: 8 occurrences<<list_path_1_gather_scatter_1>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.2.1.7  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).
2 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).
7 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.2.1.8  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 140 FP arithmetical operations:
 - 77: addition or subtraction (63 inside FMA instructions)
 - 63: multiply (all inside FMA instructions)
The binary loop is loading 1560 bytes (195 double precision FP elements).
The binary loop is storing 8 bytes (1 double precision FP elements).


      6.1.2.1.9  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.







      6.1.3  -  Loop 3121 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9639/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:256-263.

Warnings:
 - Non-innermost loop: analyzing only self part (ignoring child loops).
 - Ignoring paths for analysis
 - Failed to get the number of paths
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths


      6.1.3.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

14% of peak computational performance is used (4.65 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.3.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
Only 48% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 29.67 to 26.62 cycles (1.11x speedup).

Details
59% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 77% of SSE/AVX loads are used in vector version.
 - 0% of SSE/AVX stores are used in vector version.
 - 83% of SSE/AVX addition or subtraction instructions are used in vector version.
 - 72% of SSE/AVX fused multiply-add instructions are used in vector version.
 - 46% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.3.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by reading data from caches/RAM (load units are a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 29.67 to 27.67 cycles (1.07x speedup).


Workaround
 - Read less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop
  * use the 'restrict' C99 keyword





      6.1.3.1.3  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 63 FMA (fused multiply-add) operations.




      6.1.3.1.4  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VGATHERQPD: 8 occurrences<<list_path_1_complex_1>>



      6.1.3.1.5  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses). By removing them, you can lower the cost of an iteration from 29.67 to 22.33 cycles (1.33x speedup).

Details
 - VGATHERQPD: 8 occurrences<<list_path_1_gather_scatter_1>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.3.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).
2 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).
7 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.3.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 138 FP arithmetical operations:
 - 75: addition or subtraction (63 inside FMA instructions)
 - 63: multiply (all inside FMA instructions)
The binary loop is loading 1544 bytes (193 double precision FP elements).
The binary loop is storing 8 bytes (1 double precision FP elements).


      6.1.3.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.







      6.1.4  -  Loop 3130 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9639/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:334-341.

Warnings:
 - Non-innermost loop: analyzing only self part (ignoring child loops).
 - Ignoring paths for analysis
 - Too many paths. If you really need to analyze all of the 128 paths individually, rerun with max-paths=128
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 128 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.4.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

14% of peak computational performance is used (4.62 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.4.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 30.33 to 28.00 cycles (1.08x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.4.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
Only 47% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 30.33 to 27.29 cycles (1.11x speedup).

Details
60% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 77% of SSE/AVX loads are used in vector version.
 - 0% of SSE/AVX stores are used in vector version.
 - 71% of SSE/AVX addition or subtraction instructions are used in vector version.
 - 72% of SSE/AVX fused multiply-add instructions are used in vector version.
 - 53% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.4.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by reading data from caches/RAM (load units are a bottleneck).


Workaround
 - Read less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop
  * use the 'restrict' C99 keyword





      6.1.4.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 63 FMA (fused multiply-add) operations.




      6.1.4.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VGATHERQPD: 8 occurrences<<list_path_1_complex_1>>



      6.1.4.1.6  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses). By removing them, you can lower the cost of an iteration from 30.33 to 23.67 cycles (1.28x speedup).

Details
 - VGATHERQPD: 8 occurrences<<list_path_1_gather_scatter_1>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.4.1.7  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).
2 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).
7 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.4.1.8  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 140 FP arithmetical operations:
 - 77: addition or subtraction (63 inside FMA instructions)
 - 63: multiply (all inside FMA instructions)
The binary loop is loading 1560 bytes (195 double precision FP elements).
The binary loop is storing 8 bytes (1 double precision FP elements).


      6.1.4.1.9  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.







      6.1.5  -  Loop 3182 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9639/intel/AMG/build/AMG/AMG/seq_mv/vector.c:452.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

      6.1.5.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

70% of peak computational performance is used (22.59 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.5.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is fully vectorized, using full register length.


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).



      6.1.5.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.5.1.3  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 64 FMA (fused multiply-add) operations.




      6.1.5.1.4  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.5.1.5  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 128 FP arithmetical operations:
 - 64: addition or subtraction (all inside FMA instructions)
 - 64: multiply (all inside FMA instructions)
The binary loop is loading 1024 bytes (128 double precision FP elements).
The binary loop is storing 512 bytes (64 double precision FP elements).


      6.1.5.1.6  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.6  -  Loop 2136 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9639/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3659.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

      6.1.6.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.00 out of 64.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.6.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is fully vectorized, using full register length.


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).



      6.1.6.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck).


Workaround
 - Write less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop
  * use the 'restrict' C99 keyword




No data for this section



      6.1.6.1.3  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.


      6.1.6.1.4  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is loading 512 bytes.
The binary loop is storing 512 bytes.







      6.1.7  -  Loop 3147 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9639/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:564-567.

Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9639/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:564,567.

Warnings:
 - Non-innermost loop: analyzing only self part (ignoring child loops).
 - Ignoring paths for analysis
 - Too many paths. Rerun with max-paths=16
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 16 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.7.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

3% of peak computational performance is used (1.14 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.7.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 12.33 to 7.00 cycles (1.76x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.7.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
8 data elements could be processed at once in vector registers.
<<image_1x64_512>>By vectorizing your loop, you can lower the cost of an iteration from 12.33 to 1.54 cycles (8.00x speedup).

Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.7.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.7.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 7 FMA (fused multiply-add) operations.




      6.1.7.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).



      6.1.7.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 14 FP arithmetical operations:
 - 7: addition or subtraction (all inside FMA instructions)
 - 7: multiply (all inside FMA instructions)
The binary loop is loading 240 bytes (30 double precision FP elements).
The binary loop is storing 56 bytes (7 double precision FP elements).


      6.1.7.1.7  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.







      6.1.8  -  Loop 2856 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9639/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3378-3402,3422-3436,3454.

Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9639/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3378,3383-3385,3388-3392,3397-3402,3422-3426,3431-3436,3454.

Warnings:
 - Non-innermost loop: analyzing only self part (ignoring child loops).
 - Ignoring paths for analysis
 - Too many paths. If you really need to analyze all of the 77514 paths individually, rerun with max-paths=77514
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 77514 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.8.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.00 out of 64.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.8.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 99.67 to 67.50 cycles (1.48x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.8.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
Only 29% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 99.67 to 80.50 cycles (1.24x speedup).

Details
18% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 20% of SSE/AVX loads are used in vector version.
 - 0% of SSE/AVX stores are used in vector version.
 - 11% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.8.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.



No data for this section



      6.1.8.1.4  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VPCMPEQQ: 14 occurrences<<list_path_1_complex_1>>



      6.1.8.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------




      6.1.8.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is loading 1520 bytes.
The binary loop is storing 96 bytes.







      6.1.9  -  Loop 656 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9639/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1811-1837.

Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9639/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1811,1814-1816,1819-1824,1827-1830,1835-1837.

Warnings:
 - Non-innermost loop: analyzing only self part (ignoring child loops).
 - Ignoring paths for analysis
 - Too many paths. If you really need to analyze all of the 68 paths individually, rerun with max-paths=68
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 68 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.9.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

3% of peak computational performance is used (1.22 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.9.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 20.50 to 12.83 cycles (1.60x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.9.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
8 data elements could be processed at once in vector registers.
<<image_1x64_512>>By vectorizing your loop, you can lower the cost of an iteration from 20.50 to 2.56 cycles (8.00x speedup).

Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.9.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.9.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.04x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.9.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

25 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).



      6.1.9.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 25 FP arithmetical operations:
 - 19: addition or subtraction
 - 6: multiply
The binary loop is loading 384 bytes (48 double precision FP elements).
The binary loop is storing 56 bytes (7 double precision FP elements).


      6.1.9.1.7  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.







      6.1.10  -  Loop 2497 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9639/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:946-948,956-965.

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.10.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

3% of peak computational performance is used (1.09 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.10.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 1.83 to 1.50 cycles (1.22x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.10.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
8 data elements could be processed at once in vector registers.
<<image_1x64_512>>By vectorizing your loop, you can lower the cost of an iteration from 1.83 to 0.23 cycles (8.00x speedup).

Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.10.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.10.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.10x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.10.1.5  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 2 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.10.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).



      6.1.10.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 2 FP arithmetical operations:
 - 1: addition or subtraction
 - 1: multiply
The binary loop is loading 32 bytes (4 double precision FP elements).
The binary loop is storing 8 bytes (1 double precision FP elements).


      6.1.10.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.


      6.1.10.1.9  -  Unroll opportunity
  ----------------------------------------------------------------------------------------------------------

Loop is potentially data access bound.

Workaround
Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N




      6.1.10.2  -  Path 2
  ----------------------------------------------------------------------------------------------------------

1% of peak computational performance is used (0.43 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.10.2.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 2.33 to 1.50 cycles (1.56x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.10.2.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
8 data elements could be processed at once in vector registers.
<<image_1x64_512>>By vectorizing your loop, you can lower the cost of an iteration from 2.33 to 0.29 cycles (8.00x speedup).

Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.10.2.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.



No data for this section



      6.1.10.2.4  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 1 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.10.2.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).



      6.1.10.2.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 1 FP arithmetical operations:
 - 1: multiply
The binary loop is loading 40 bytes (5 double precision FP elements).
The binary loop is storing 24 bytes (3 double precision FP elements).


      6.1.10.2.7  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.


      6.1.10.2.8  -  Unroll opportunity
  ----------------------------------------------------------------------------------------------------------

Loop is data access bound.

Workaround
Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N





[MAQAO] Info: STOP THE REPORT GENERATION
[MAQAO] Info: 
[MAQAO] Info: If your application produces files, they can be found in directory "/beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9639/intel/AMG/run/oneview_runs/compilers/gcc_2/oneview_run_1786695611"
[MAQAO] Info: 
