OV - exec - Loop 4341

0x4dfb80 LEA	0x1(%RDX),%RAX

0x4dfb84 CMP	%R11,%RDX

0x4dfb87 MOV	%RAX,%RDX

0x4dfb8a JE	4dfa13

0x4dfb90 LEA	(%RCX,%RDX,1),%RSI

0x4dfb94 MOV	-0x88(%RBP),%RAX

0x4dfb9b MOV	(%RAX,%RSI,8),%RDI

0x4dfb9f MOV	0x8(%RAX,%RSI,8),%R8

0x4dfba4 MOV	%R8,%R9

0x4dfba7 SUB	%RDI,%R9

0x4dfbaa JLE	4dfb80

0x4dfbac CMP	$0x4,%R9

0x4dfbb0 JB	4dfc5b

0x4dfbb6 MOV	%R9,%R10

0x4dfbb9 SHR	$0x2,%R10

0x4dfbbd LEA	0x18(,%RDI,8),%R11

0x4dfbc5 NOPW	%CS:(%RAX,%RAX,1)

  (4343) 0x4dfbd0 VMOVSD	(%R15,%RSI,8),%XMM0

  (4343) 0x4dfbd6 VMOVSD	-0x18(%R12,%R11,1),%XMM1

  (4343) 0x4dfbdd MOV	-0x18(%R14,%R11,1),%RAX

  (4343) 0x4dfbe2 ADD	%R13,%RAX

  (4343) 0x4dfbe5 VFMADD213SD	(%RBX,%RAX,8),%XMM0,%XMM1

  (4343) 0x4dfbeb VMOVSD	%XMM1,(%RBX,%RAX,8)

  (4343) 0x4dfbf0 VMOVSD	(%R15,%RSI,8),%XMM0

  (4343) 0x4dfbf6 VMOVSD	-0x10(%R12,%R11,1),%XMM1

  (4343) 0x4dfbfd MOV	-0x10(%R14,%R11,1),%RAX

  (4343) 0x4dfc02 ADD	%R13,%RAX

  (4343) 0x4dfc05 VFMADD213SD	(%RBX,%RAX,8),%XMM0,%XMM1

  (4343) 0x4dfc0b VMOVSD	%XMM1,(%RBX,%RAX,8)

  (4343) 0x4dfc10 VMOVSD	(%R15,%RSI,8),%XMM0

  (4343) 0x4dfc16 VMOVSD	-0x8(%R12,%R11,1),%XMM1

  (4343) 0x4dfc1d MOV	-0x8(%R14,%R11,1),%RAX

  (4343) 0x4dfc22 ADD	%R13,%RAX

  (4343) 0x4dfc25 VFMADD213SD	(%RBX,%RAX,8),%XMM0,%XMM1

  (4343) 0x4dfc2b VMOVSD	%XMM1,(%RBX,%RAX,8)

  (4343) 0x4dfc30 VMOVSD	(%R15,%RSI,8),%XMM0

  (4343) 0x4dfc36 VMOVSD	(%R12,%R11,1),%XMM1

  (4343) 0x4dfc3c MOV	(%R14,%R11,1),%RAX

  (4343) 0x4dfc40 ADD	%R13,%RAX

  (4343) 0x4dfc43 VFMADD213SD	(%RBX,%RAX,8),%XMM0,%XMM1

  (4343) 0x4dfc49 VMOVSD	%XMM1,(%RBX,%RAX,8)

  (4343) 0x4dfc4e ADD	$0x20,%R11

  (4343) 0x4dfc52 DEC	%R10

  (4343) 0x4dfc55 JNE	4dfbd0

0x4dfc5b MOV	%R9,%R10

0x4dfc5e AND	$-0x4,%R10

0x4dfc62 CMP	%R9,%R10

0x4dfc65 MOV	-0x30(%RBP),%R11

0x4dfc69 JAE	4dfb80

0x4dfc6f ADD	%R10,%RDI

0x4dfc72 NOPW	%CS:(%RAX,%RAX,1)

  (4342) 0x4dfc80 VMOVSD	(%R15,%RSI,8),%XMM0

  (4342) 0x4dfc86 VMOVSD	(%R12,%RDI,8),%XMM1

  (4342) 0x4dfc8c MOV	(%R14,%RDI,8),%RAX

  (4342) 0x4dfc90 ADD	%R13,%RAX

  (4342) 0x4dfc93 VFMADD213SD	(%RBX,%RAX,8),%XMM0,%XMM1

  (4342) 0x4dfc99 VMOVSD	%XMM1,(%RBX,%RAX,8)

  (4342) 0x4dfc9e INC	%RDI

  (4342) 0x4dfca1 CMP	%RDI,%R8

  (4342) 0x4dfca4 JNE	4dfc80

0x4dfca6 JMP	4dfb80

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 560 - 567

--------------------------------------------------------------------------------

560: #pragma omp for HYPRE_SMP_SCHEDULE

561: #endif

562:             for (i = 0; i < num_rows; i++)

563:             {

564:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

565:                {

566:                   j = A_j[jj];

567:                   y_data_expand[offset + j] += A_data[jj] * x_data[i];

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.67
Bottlenecks	micro-operation queue,
Function	hypre_CSRMatrixMatvecT.extracted.49
Source	csr_matvec.c:560-564
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.17
CQA cycles if no scalar integer	4.17
CQA cycles if FP arith vectorized	4.17
CQA cycles if fully vectorized	0.52
Front-end cycles	4.17
P0 cycles	2.50
P1 cycles	2.00
P2 cycles	1.33
P3 cycles	1.33
P4 cycles	0.00
P5 cycles	2.00
P6 cycles	2.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	2.00
P11 cycles	1.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	25.00
Nb loads	4.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.68
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.67
Bottlenecks	micro-operation queue,
Function	hypre_CSRMatrixMatvecT.extracted.49
Source	csr_matvec.c:560-564
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.17
CQA cycles if no scalar integer	4.17
CQA cycles if FP arith vectorized	4.17
CQA cycles if fully vectorized	0.52
Front-end cycles	4.17
P0 cycles	2.50
P1 cycles	2.00
P2 cycles	1.33
P3 cycles	1.33
P4 cycles	0.00
P5 cycles	2.00
P6 cycles	2.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	2.00
P11 cycles	1.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	25.00
Nb loads	4.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.68
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixMatvecT.extracted.49
Source file and lines	csr_matvec.c:560-567
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560-567.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560-564.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.17 to 0.52 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes.

General properties

nb instructions	25
nb uops	25
loop length	122
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.17 cycles
front end	4.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.50	2.00	1.33	1.33	0.00	2.00	2.50	0.00	0.00	0.00	2.00	1.33
cycles	2.50	2.00	1.33	1.33	0.00	2.00	2.50	0.00	0.00	0.00	2.00	1.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.17
Dispatch	2.50
Overall L1	4.17

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.17 cycles. At this rate:

4% of peak load performance is reached (7.68 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.17 to 2.50 cycles (1.67x speedup).

ASM code

In the binary file, the address of the loop is: 4dfb90

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
LEA 0x1(%RDX),%RAX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R11,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 4dfa13 <hypre_CSRMatrixMatvecT.extracted.49+0xc3>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
LEA (%RCX,%RDX,1),%RSI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x88(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%RSI,8),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX,%RSI,8),%R8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDI,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JLE 4dfb80 <hypre_CSRMatrixMatvecT.extracted.49+0x230>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP $0x4,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JB 4dfc5b <hypre_CSRMatrixMatvecT.extracted.49+0x30b>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV %R9,%R10	1	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x2,%R10	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
LEA 0x18(,%RDI,8),%R11	1	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,%R10	1	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
CMP %R9,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
MOV -0x30(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
JAE 4dfb80 <hypre_CSRMatrixMatvecT.extracted.49+0x230>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
ADD %R10,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4dfb80 <hypre_CSRMatrixMatvecT.extracted.49+0x230>	1	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	hypre_CSRMatrixMatvecT.extracted.49
Source file and lines	csr_matvec.c:560-567
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560-567.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560-564.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.17 to 0.52 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes.

General properties

nb instructions	25
nb uops	25
loop length	122
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.17 cycles
front end	4.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.50	2.00	1.33	1.33	0.00	2.00	2.50	0.00	0.00	0.00	2.00	1.33
cycles	2.50	2.00	1.33	1.33	0.00	2.00	2.50	0.00	0.00	0.00	2.00	1.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.17
Dispatch	2.50
Overall L1	4.17

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.17 cycles. At this rate:

4% of peak load performance is reached (7.68 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.17 to 2.50 cycles (1.67x speedup).

ASM code

In the binary file, the address of the loop is: 4dfb90

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
LEA 0x1(%RDX),%RAX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R11,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 4dfa13 <hypre_CSRMatrixMatvecT.extracted.49+0xc3>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
LEA (%RCX,%RDX,1),%RSI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x88(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%RSI,8),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX,%RSI,8),%R8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDI,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JLE 4dfb80 <hypre_CSRMatrixMatvecT.extracted.49+0x230>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP $0x4,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JB 4dfc5b <hypre_CSRMatrixMatvecT.extracted.49+0x30b>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV %R9,%R10	1	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x2,%R10	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
LEA 0x18(,%RDI,8),%R11	1	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,%R10	1	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
CMP %R9,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
MOV -0x30(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
JAE 4dfb80 <hypre_CSRMatrixMatvecT.extracted.49+0x230>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
ADD %R10,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4dfb80 <hypre_CSRMatrixMatvecT.extracted.49+0x230>	1	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code