OV - exec - Loop 278

	Loop Id: 278	Module: exec	Source: par_coarsen.c:2354-2381	Coverage: 0.08%

0x4251c0 LEA	0x1(%RCX),%RDX

0x4251c4 CMP	%RAX,%RCX

0x4251c7 MOV	%RDX,%RCX

0x4251ca JE	42518e

0x4251cc MOV	(%R10,%RCX,8),%RDX

0x4251d0 VMOVSD	(%RBX,%RDX,8),%XMM1

0x4251d5 VUCOMISD	%XMM1,%XMM0

0x4251d9 JAE	4251c0

0x4251db MOV	(%R13,%RDX,8),%RSI

0x4251e0 CMP	0x8(%R13,%RDX,8),%RSI

0x4251e5 MOV	-0x38(%RBP),%R8

0x4251e9 JL	425212

0x4251eb MOV	(%R15,%RDX,8),%RSI

0x4251ef CMP	0x8(%R15,%RDX,8),%RSI

0x4251f4 JGE	4251c0

0x4251f6 MOV	-0x38(%RBP),%RDI

0x4251fa LEA	(%RDI,%RDX,8),%RDI

0x4251fe JMP	425259

  (280) 0x425200 MOVQ	$0,(%R8,%RDI,8)

  (280) 0x425208 INC	%RSI

  (280) 0x42520b CMP	0x8(%R13,%RDX,8),%RSI

  (280) 0x425210 JGE	4251eb

  (280) 0x425212 MOV	(%R12,%RSI,8),%RDI

  (280) 0x425216 VMOVSD	(%RBX,%RDI,8),%XMM2

  (280) 0x42521b VUCOMISD	%XMM2,%XMM0

  (280) 0x42521f JAE	425208

  (280) 0x425221 VUCOMISD	%XMM2,%XMM1

  (280) 0x425225 JA	425200

  (280) 0x425227 VUCOMISD	%XMM1,%XMM2

  (280) 0x42522b MOV	%RDX,%RDI

  (280) 0x42522e JA	425200

  (280) 0x425230 JMP	425208

  (279) 0x425240 LEA	(%R11,%R8,8),%R8

  (279) 0x425244 MOVQ	$0,(%R8)

  (279) 0x42524b INC	%RSI

  (279) 0x42524e CMP	0x8(%R15,%RDX,8),%RSI

  (279) 0x425253 JGE	4251c0

  (279) 0x425259 MOV	(%R14,%RSI,8),%R8

  (279) 0x42525d MOV	-0x58(%RBP),%R9

  (279) 0x425261 ADD	%R8,%R9

  (279) 0x425264 VMOVSD	(%RBX,%R9,8),%XMM2

  (279) 0x42526a VUCOMISD	%XMM2,%XMM0

  (279) 0x42526e JAE	42524b

  (279) 0x425270 VUCOMISD	%XMM2,%XMM1

  (279) 0x425274 JA	425240

  (279) 0x425276 VUCOMISD	%XMM1,%XMM2

  (279) 0x42527a MOV	%RDI,%R8

  (279) 0x42527d JA	425244

  (279) 0x42527f JMP	42524b

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2354 - 2381

--------------------------------------------------------------------------------

2354: #pragma omp parallel for private(ig, i, jS, j, jj) HYPRE_SMP_SCHEDULE

2355: #endif

2356:         for (ig = 0; ig < graph_size; ig++)

2357:         {

2358:            i = graph_array[ig];

2359:            if (measure_array[i] > 1)

2360:            {

2361:               for (jS = S_diag_i[i]; jS < S_diag_i[i+1]; jS++)

2362:               {

2363:                  j = S_diag_j[jS];

2364:                  if (measure_array[j] > 1)

2365:                  {

2366:                     if (measure_array[i] > measure_array[j])

2367:                        CF_marker[j] = 0;

2368:                     else if (measure_array[j] > measure_array[i])

2369:                        CF_marker[i] = 0;

2370:                  }

2371:               } /* for each local neighbor j of i */

2372:               for (jS = S_offd_i[i]; jS < S_offd_i[i+1]; jS++)

2373:               {

2374:                  jj = S_offd_j[jS];

2375:                  j = num_variables+jj;

2376:                  if (measure_array[j] > 1)

2377:                  {

2378:                     if (measure_array[i] > measure_array[j])

2379:                        CF_marker_offd[jj] = 0;

2380:                     else if (measure_array[j] > measure_array[i])

2381:                        CF_marker[i] = 0;

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.33
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGCoarsenPMIS.extracted.15
Source	par_coarsen.c:2354-2361,par_coarsen.c:2372-2372,par_coarsen.c:2381-2381
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.33
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	3.33
CQA cycles if fully vectorized	0.42
Front-end cycles	3.33
P0 cycles	2.50
P1 cycles	1.00
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	0.00
P5 cycles	1.00
P6 cycles	2.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	2.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	18.00
Nb loads	8.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.20
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.33
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGCoarsenPMIS.extracted.15
Source	par_coarsen.c:2354-2361,par_coarsen.c:2372-2372,par_coarsen.c:2381-2381
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.33
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	3.33
CQA cycles if fully vectorized	0.42
Front-end cycles	3.33
P0 cycles	2.50
P1 cycles	1.00
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	0.00
P5 cycles	1.00
P6 cycles	2.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	2.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	18.00
Nb loads	8.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.20
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCoarsenPMIS.extracted.15
Source file and lines	par_coarsen.c:2354-2381
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354-2381.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354-2361,2372,2381.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=26
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 26 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.33 to 2.50 cycles (1.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 3.33 to 0.42 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes (8 double precision FP elements).

General properties

nb instructions	18
nb uops	18
loop length	64
used x86 registers	11
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.33 cycles
front end	3.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.50	1.00	2.67	2.67	0.00	1.00	2.50	0.00	0.00	0.00	1.00	2.67
cycles	2.50	1.00	2.67	2.67	0.00	1.00	2.50	0.00	0.00	0.00	1.00	2.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.33
Dispatch	2.67
Overall L1	3.33

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.33 cycles. At this rate:

10% of peak load performance is reached (19.20 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.33 to 2.67 cycles (1.25x speedup).

ASM code

In the binary file, the address of the loop is: 4251cc

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
LEA 0x1(%RCX),%RDX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 42518e <hypre_BoomerAMGCoarsenPMIS.extracted.15+0x9e>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV (%R10,%RCX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RBX,%RDX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VUCOMISD %XMM1,%XMM0	1	1	0	0	0	0	0	0	0	3	1	scal (12.5%)
JAE 4251c0 <hypre_BoomerAMGCoarsenPMIS.extracted.15+0xd0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV (%R13,%RDX,8),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP 0x8(%R13,%RDX,8),%RSI	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x38(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
JL 425212 <hypre_BoomerAMGCoarsenPMIS.extracted.15+0x122>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV (%R15,%RDX,8),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP 0x8(%R15,%RDX,8),%RSI	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	N/A
JGE 4251c0 <hypre_BoomerAMGCoarsenPMIS.extracted.15+0xd0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x38(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
LEA (%RDI,%RDX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 425259 <hypre_BoomerAMGCoarsenPMIS.extracted.15+0x169>	1	0	0	0	0	0	0	0	0	0	5.84	N/A

Function	hypre_BoomerAMGCoarsenPMIS.extracted.15
Source file and lines	par_coarsen.c:2354-2381
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=26
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.33 to 2.50 cycles (1.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 3.33 to 0.42 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes (8 double precision FP elements).

General properties

nb instructions	18
nb uops	18
loop length	64
used x86 registers	11
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.33 cycles
front end	3.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.50	1.00	2.67	2.67	0.00	1.00	2.50	0.00	0.00	0.00	1.00	2.67
cycles	2.50	1.00	2.67	2.67	0.00	1.00	2.50	0.00	0.00	0.00	1.00	2.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.33
Dispatch	2.67
Overall L1	3.33

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.33 cycles. At this rate:

10% of peak load performance is reached (19.20 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4251cc

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
LEA 0x1(%RCX),%RDX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 42518e <hypre_BoomerAMGCoarsenPMIS.extracted.15+0x9e>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV (%R10,%RCX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RBX,%RDX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VUCOMISD %XMM1,%XMM0	1	1	0	0	0	0	0	0	0	3	1	scal (12.5%)
JAE 4251c0 <hypre_BoomerAMGCoarsenPMIS.extracted.15+0xd0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV (%R13,%RDX,8),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP 0x8(%R13,%RDX,8),%RSI	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x38(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
JL 425212 <hypre_BoomerAMGCoarsenPMIS.extracted.15+0x122>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV (%R15,%RDX,8),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP 0x8(%R15,%RDX,8),%RSI	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	N/A
JGE 4251c0 <hypre_BoomerAMGCoarsenPMIS.extracted.15+0xd0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x38(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
LEA (%RDI,%RDX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 425259 <hypre_BoomerAMGCoarsenPMIS.extracted.15+0x169>	1	0	0	0	0	0	0	0	0	0	5.84	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code