OV - exec - Loop 275

	Loop Id: 275	Module: exec	Source: par_coarsen.c:2435-2477 [...]	Coverage: 0.03%

0x425020 MOVQ	$0x1,(%R15,%RDX,8)

0x425028 LEA	0x1(%RCX),%RDX

0x42502c CMP	%RAX,%RCX

0x42502f MOV	%RDX,%RCX

0x425032 JE	424ff7

0x425034 MOV	(%R9,%RCX,8),%RDX

0x425038 VUCOMISD	(%R10,%RDX,8),%XMM0

0x42503e JBE	425060

0x425040 MOVQ	$-0x1,(%R15,%RDX,8)

0x425048 MOV	$-0x1,%RSI

0x42504f TEST	%RSI,%RSI

0x425052 JG	425020

0x425054 JMP	425069

0x425060 MOV	(%R15,%RDX,8),%RSI

0x425064 TEST	%RSI,%RSI

0x425067 JG	425020

0x425069 MOV	(%R13,%RDX,8),%RSI

0x42506e MOV	0x8(%R13,%RDX,8),%RDI

0x425073 JMP	425083

  (277) 0x425080 INC	%RSI

  (277) 0x425083 CMP	%RDI,%RSI

  (277) 0x425086 JGE	4250b0

  (277) 0x425088 MOV	(%R12,%RSI,8),%R8

  (277) 0x42508c CMPQ	$0,(%R15,%R8,8)

  (277) 0x425091 JLE	425080

  (277) 0x425093 MOVQ	$-0x1,(%R15,%RDX,8)

  (277) 0x42509b MOV	0x8(%R13,%RDX,8),%RDI

  (277) 0x4250a0 JMP	425080

0x4250b0 MOV	(%R11,%RDX,8),%RSI

0x4250b4 MOV	0x8(%R11,%RDX,8),%RDI

0x4250b9 JMP	4250c3

  (276) 0x4250c0 INC	%RSI

  (276) 0x4250c3 CMP	%RDI,%RSI

  (276) 0x4250c6 JGE	425028

  (276) 0x4250cc MOV	(%R14,%RSI,8),%R8

  (276) 0x4250d0 CMPQ	$0,(%RBX,%R8,8)

  (276) 0x4250d5 JLE	4250c0

  (276) 0x4250d7 MOVQ	$-0x1,(%R15,%RDX,8)

  (276) 0x4250df MOV	0x8(%R11,%RDX,8),%RDI

  (276) 0x4250e4 JMP	4250c0

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2435 - 2477

--------------------------------------------------------------------------------

2435: #pragma omp parallel for private(ig, i, jS, j) HYPRE_SMP_SCHEDULE

2436: #endif

2437:      for (ig = 0; ig < graph_size; ig++) {

2438:        i = graph_array[ig];

[...]

2446:        if(measure_array[i]<1.) CF_marker[i]= F_PT;

[...]

2453:        if (CF_marker[i] > 0) CF_marker[i] = C_PT;

[...]

2465: 	 for (jS = S_diag_i[i]; jS < S_diag_i[i+1]; jS++)

2466:          {

2467: 	   /* j is the column number, or the local number of the point influencing i */

2468: 	   j = S_diag_j[jS];

2469: 	   if (CF_marker[j] > 0) /* j is a C-point */

2470: 	     CF_marker[i] = F_PT;

2471: 	 }

2472: 	 /* now the external part */

2473: 	 for (jS = S_offd_i[i]; jS < S_offd_i[i+1]; jS++)

2474: 	 {

2475: 	   j = S_offd_j[jS];

2476: 	   if (CF_marker_offd[j] > 0) /* j is a C-point */

2477: 	     CF_marker[i] = F_PT;

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.53
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.04
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.53
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGCoarsenPMIS.extracted.10
Source	par_coarsen.c:2435-2438,par_coarsen.c:2446-2446,par_coarsen.c:2453-2453,par_coarsen.c:2465-2465,par_coarsen.c:2473-2473
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.83
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	3.83
CQA cycles if fully vectorized	0.29
Front-end cycles	3.83
P0 cycles	2.50
P1 cycles	1.40
P2 cycles	2.33
P3 cycles	2.33
P4 cycles	1.00
P5 cycles	1.40
P6 cycles	2.50
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	1.20
P11 cycles	2.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	23.00
Nb loads	7.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.78
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.71
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.53
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.04
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.53
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGCoarsenPMIS.extracted.10
Source	par_coarsen.c:2435-2438,par_coarsen.c:2446-2446,par_coarsen.c:2453-2453,par_coarsen.c:2465-2465,par_coarsen.c:2473-2473
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.83
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	3.83
CQA cycles if fully vectorized	0.29
Front-end cycles	3.83
P0 cycles	2.50
P1 cycles	1.40
P2 cycles	2.33
P3 cycles	2.33
P4 cycles	1.00
P5 cycles	1.40
P6 cycles	2.50
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	1.20
P11 cycles	2.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	23.00
Nb loads	7.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.78
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.71
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCoarsenPMIS.extracted.10
Source file and lines	par_coarsen.c:2435-2477
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2435-2438,2446,2453,2465-2477.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2435-2438,2446,2453,2465,2473.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=12
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 12 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.83 to 2.50 cycles (1.53x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.83 to 0.29 cycles (13.04x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2446

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes (7 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

General properties

nb instructions	22
nb uops	23
loop length	86
used x86 registers	10
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.83 cycles
front end	3.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.50	1.40	2.33	2.33	1.00	1.40	2.50	1.00	1.00	1.00	1.20	2.33
cycles	2.50	1.40	2.33	2.33	1.00	1.40	2.50	1.00	1.00	1.00	1.20	2.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.83
Dispatch	2.50
Overall L1	3.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.83 cycles. At this rate:

7% of peak load performance is reached (14.61 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.17 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.83 to 2.50 cycles (1.53x speedup).

ASM code

In the binary file, the address of the loop is: 425034

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOVQ $0x1,(%R15,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x1(%RCX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 424ff7 <hypre_BoomerAMGCoarsenPMIS.extracted.10+0x97>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R9,%RCX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R10,%RDX,8),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JBE 425060 <hypre_BoomerAMGCoarsenPMIS.extracted.10+0x100>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $-0x1,(%R15,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $-0x1,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
TEST %RSI,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JG 425020 <hypre_BoomerAMGCoarsenPMIS.extracted.10+0xc0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 425069 <hypre_BoomerAMGCoarsenPMIS.extracted.10+0x109>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV (%R15,%RDX,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RSI,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JG 425020 <hypre_BoomerAMGCoarsenPMIS.extracted.10+0xc0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R13,%RDX,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R13,%RDX,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 425083 <hypre_BoomerAMGCoarsenPMIS.extracted.10+0x123>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV (%R11,%RDX,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R11,%RDX,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 4250c3 <hypre_BoomerAMGCoarsenPMIS.extracted.10+0x163>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Function	hypre_BoomerAMGCoarsenPMIS.extracted.10
Source file and lines	par_coarsen.c:2435-2477
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=12
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.83 to 2.50 cycles (1.53x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2446

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

General properties

nb instructions	22
nb uops	23
loop length	86
used x86 registers	10
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.83 cycles
front end	3.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.50	1.40	2.33	2.33	1.00	1.40	2.50	1.00	1.00	1.00	1.20	2.33
cycles	2.50	1.40	2.33	2.33	1.00	1.40	2.50	1.00	1.00	1.00	1.20	2.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.83
Dispatch	2.50
Overall L1	3.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.83 cycles. At this rate:

7% of peak load performance is reached (14.61 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.17 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 425034

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOVQ $0x1,(%R15,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x1(%RCX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 424ff7 <hypre_BoomerAMGCoarsenPMIS.extracted.10+0x97>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R9,%RCX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R10,%RDX,8),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JBE 425060 <hypre_BoomerAMGCoarsenPMIS.extracted.10+0x100>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $-0x1,(%R15,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $-0x1,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
TEST %RSI,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JG 425020 <hypre_BoomerAMGCoarsenPMIS.extracted.10+0xc0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 425069 <hypre_BoomerAMGCoarsenPMIS.extracted.10+0x109>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV (%R15,%RDX,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RSI,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JG 425020 <hypre_BoomerAMGCoarsenPMIS.extracted.10+0xc0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R13,%RDX,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R13,%RDX,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 425083 <hypre_BoomerAMGCoarsenPMIS.extracted.10+0x123>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV (%R11,%RDX,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R11,%RDX,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 4250c3 <hypre_BoomerAMGCoarsenPMIS.extracted.10+0x163>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code