OV - exec - Loop 2513

0x4901e0 INC	%RSI

0x4901e3 MOV	-0x58(%RBP),%RDI

0x4901e7 CMP	0x8(%RDI,%RAX,8),%RSI

0x4901ec JGE	4900c7

0x4901f2 MOV	(%R15,%RSI,8),%RDI

0x4901f6 CMPQ	$0,(%R13,%RDI,8)

0x4901fc JLE	49022b

0x4901fe MOV	0x78(%RBP),%R8

0x490202 MOV	(%R8,%RDI,8),%R8

0x490206 MOV	-0x48(%RBP),%R9

0x49020a CMP	%RCX,(%R9,%R8,8)

0x49020e JGE	49022b

0x490210 MOV	-0x30(%RBP),%R9

0x490214 MOV	-0x48(%RBP),%R10

0x490218 MOV	%R9,(%R10,%R8,8)

0x49021c MOV	0x30(%RBP),%R10

0x490220 MOV	(%R10),%R10

0x490223 MOV	%R8,(%R10,%R9,8)

0x490227 INCQ	-0x30(%RBP)

0x49022b MOV	-0x58(%RBP),%R9

0x49022f MOV	(%R9,%RDI,8),%R8

0x490233 MOV	0x8(%R9,%RDI,8),%R9

0x490238 JMP	490243

  (2515) 0x490240 INC	%R8

  (2515) 0x490243 CMP	%R9,%R8

  (2515) 0x490246 JGE	4902a0

  (2515) 0x490248 MOV	(%R15,%R8,8),%R10

  (2515) 0x49024c CMPQ	$0,(%R13,%R10,8)

  (2515) 0x490252 JLE	490240

  (2515) 0x490254 MOV	0x78(%RBP),%R11

  (2515) 0x490258 MOV	(%R11,%R10,8),%R10

  (2515) 0x49025c CMP	%RBX,%R10

  (2515) 0x49025f JE	490240

  (2515) 0x490261 MOV	-0x48(%RBP),%R11

  (2515) 0x490265 CMP	%RCX,(%R11,%R10,8)

  (2515) 0x490269 JGE	490240

  (2515) 0x49026b MOV	-0x30(%RBP),%R9

  (2515) 0x49026f MOV	-0x48(%RBP),%R11

  (2515) 0x490273 MOV	%R9,(%R11,%R10,8)

  (2515) 0x490277 MOV	0x30(%RBP),%R11

  (2515) 0x49027b MOV	(%R11),%R11

  (2515) 0x49027e MOV	%R10,(%R11,%R9,8)

  (2515) 0x490282 INCQ	-0x30(%RBP)

  (2515) 0x490286 MOV	-0x58(%RBP),%R9

  (2515) 0x49028a MOV	0x8(%R9,%RDI,8),%R9

  (2515) 0x49028f JMP	490240

0x4902a0 MOV	0x10(%RBP),%R9

0x4902a4 MOV	(%R9,%RDI,8),%R8

0x4902a8 MOV	0x8(%R9,%RDI,8),%R9

0x4902ad JMP	4902b3

  (2514) 0x4902b0 INC	%R8

  (2514) 0x4902b3 CMP	%R9,%R8

  (2514) 0x4902b6 JGE	4901e0

  (2514) 0x4902bc MOV	0x18(%RBP),%R10

  (2514) 0x4902c0 MOV	(%R10,%R8,8),%R10

  (2514) 0x4902c4 MOV	0x70(%RBP),%R11

  (2514) 0x4902c8 CMPQ	$0,(%R11,%R10,8)

  (2514) 0x4902cd JLE	4902b0

  (2514) 0x4902cf MOV	0x80(%RBP),%R11

  (2514) 0x4902d6 MOV	(%R11,%R10,8),%R10

  (2514) 0x4902da CMP	%RDX,(%R14,%R10,8)

  (2514) 0x4902de JGE	4902b0

  (2514) 0x4902e0 MOV	-0x38(%RBP),%R9

  (2514) 0x4902e4 MOV	%R9,(%R14,%R10,8)

  (2514) 0x4902e8 MOV	(%R12),%R11

  (2514) 0x4902ec MOV	%R10,(%R11,%R9,8)

  (2514) 0x4902f0 INCQ	-0x38(%RBP)

  (2514) 0x4902f4 MOV	0x10(%RBP),%R9

  (2514) 0x4902f8 MOV	0x8(%R9,%RDI,8),%R9

  (2514) 0x4902fd JMP	4902b0

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 2011 - 2048

--------------------------------------------------------------------------------

2011:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

2012:              {

2013:                  i2 = S_diag_j[jj1];

2014:                  if (CF_marker[i2] > 0)

2015:                  {

2016:                     index = fine_to_coarse[i2];

2017:                     if (S_marker[index] < jj_row_begin_diag)

2018:                     {

2019:                        S_marker[index] = num_nonzeros_diag;

2020:                        C_diag_j[num_nonzeros_diag] = index;

2021:                        num_nonzeros_diag++;

2022:                     }

2023:                  }

2024:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

2025:                  {

2026:                     i3 = S_diag_j[jj2];

2027:                     if (CF_marker[i3] > 0)

2028:                     {

2029:                        index = fine_to_coarse[i3];

2030:                        if (index != ic && S_marker[index] < jj_row_begin_diag)

2031:                        {

2032:                           S_marker[index] = num_nonzeros_diag;

2033:                           C_diag_j[num_nonzeros_diag] = index;

2034:                           num_nonzeros_diag++;

2035:                        }

2036:                     }

2037:                  }

2038:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

2039:                  {

2040:                     i3 = S_offd_j[jj2];

2041:                     if (CF_marker_offd[i3] > 0)

2042:                     {

2043:                        index = map_S_to_C[i3];

2044:                        if (S_marker_offd[index] < jj_row_begin_offd)

2045:                        {

2046:                           S_marker_offd[index] = num_nonzeros_offd;

2047:                           C_offd_j[num_nonzeros_offd] = index;

2048:                           num_nonzeros_offd++;

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks	P2, P3, P11,
Function	hypre_BoomerAMGCreate2ndS.extracted.17
Source	par_strength.c:2011-2021,par_strength.c:2024-2024,par_strength.c:2038-2038
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.33
CQA cycles if no scalar integer	6.33
CQA cycles if FP arith vectorized	6.33
CQA cycles if fully vectorized	0.79
Front-end cycles	5.17
P0 cycles	1.50
P1 cycles	1.40
P2 cycles	6.33
P3 cycles	6.33
P4 cycles	1.50
P5 cycles	1.40
P6 cycles	1.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	1.20
P11 cycles	6.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	29.00
Nb loads	19.00
Nb stores	3.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.79
Bytes prefetched	0.00
Bytes loaded	152.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks	P2, P3, P11,
Function	hypre_BoomerAMGCreate2ndS.extracted.17
Source	par_strength.c:2011-2021,par_strength.c:2024-2024,par_strength.c:2038-2038
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.33
CQA cycles if no scalar integer	6.33
CQA cycles if FP arith vectorized	6.33
CQA cycles if fully vectorized	0.79
Front-end cycles	5.17
P0 cycles	1.50
P1 cycles	1.40
P2 cycles	6.33
P3 cycles	6.33
P4 cycles	1.50
P5 cycles	1.40
P6 cycles	1.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	1.20
P11 cycles	6.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	29.00
Nb loads	19.00
Nb stores	3.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.79
Bytes prefetched	0.00
Bytes loaded	152.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCreate2ndS.extracted.17
Source file and lines	par_strength.c:2011-2048
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:2011-2048.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:2011-2021,2024,2038.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=24
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 24 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.33 to 0.79 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by reading data from caches/RAM (load units are a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.33 to 5.17 cycles (1.23x speedup).

Workaround

Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

INC: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:2021

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 152 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	27
nb uops	29
loop length	105
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.17 cycles
front end	5.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.50	1.40	6.33	6.33	1.50	1.40	1.50	1.50	1.50	1.50	1.20	6.33
cycles	1.50	1.40	6.33	6.33	1.50	1.40	1.50	1.50	1.50	1.50	1.20	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	5.17
Dispatch	6.33
Overall L1	6.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.33 cycles. At this rate:

12% of peak load performance is reached (24.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.79 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4901f2

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x58(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP 0x8(%RDI,%RAX,8),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 4900c7 <hypre_BoomerAMGCreate2ndS.extracted.17+0x1077>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R15,%RSI,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0,(%R13,%RDI,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JLE 49022b <hypre_BoomerAMGCreate2ndS.extracted.17+0x11db>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x78(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R8,%RDI,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RCX,(%R9,%R8,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 49022b <hypre_BoomerAMGCreate2ndS.extracted.17+0x11db>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x30(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,(%R10,%R8,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R10),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,(%R10,%R9,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INCQ -0x30(%RBP)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	N/A
MOV -0x58(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R9,%RDI,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R9,%RDI,8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 490243 <hypre_BoomerAMGCreate2ndS.extracted.17+0x11f3>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV 0x10(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R9,%RDI,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R9,%RDI,8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 4902b3 <hypre_BoomerAMGCreate2ndS.extracted.17+0x1263>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Function	hypre_BoomerAMGCreate2ndS.extracted.17
Source file and lines	par_strength.c:2011-2048
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:2011-2048.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:2011-2021,2024,2038.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=24
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 24 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.33 to 0.79 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by reading data from caches/RAM (load units are a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.33 to 5.17 cycles (1.23x speedup).

Workaround

Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

INC: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:2021

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 152 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	27
nb uops	29
loop length	105
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.17 cycles
front end	5.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.50	1.40	6.33	6.33	1.50	1.40	1.50	1.50	1.50	1.50	1.20	6.33
cycles	1.50	1.40	6.33	6.33	1.50	1.40	1.50	1.50	1.50	1.50	1.20	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	5.17
Dispatch	6.33
Overall L1	6.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.33 cycles. At this rate:

12% of peak load performance is reached (24.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.79 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4901f2

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x58(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP 0x8(%RDI,%RAX,8),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 4900c7 <hypre_BoomerAMGCreate2ndS.extracted.17+0x1077>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R15,%RSI,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0,(%R13,%RDI,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JLE 49022b <hypre_BoomerAMGCreate2ndS.extracted.17+0x11db>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x78(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R8,%RDI,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RCX,(%R9,%R8,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 49022b <hypre_BoomerAMGCreate2ndS.extracted.17+0x11db>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x30(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,(%R10,%R8,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R10),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,(%R10,%R9,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INCQ -0x30(%RBP)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	N/A
MOV -0x58(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R9,%RDI,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R9,%RDI,8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 490243 <hypre_BoomerAMGCreate2ndS.extracted.17+0x11f3>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV 0x10(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R9,%RDI,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R9,%RDI,8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 4902b3 <hypre_BoomerAMGCreate2ndS.extracted.17+0x1263>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code