OV - exec - Function hypre_CSRMatrixMatvecT.extracted.49

	Function: hypre_CSRMatrixMatvecT.extracted.49	Module: exec	Source: csr_matvec.c:554-579 [...]	Coverage (incl. loops): 1.23% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 554 - 579

--------------------------------------------------------------------------------

554: #pragma omp parallel private(i,jj,j,my_thread_num,offset)

555: #endif

556:          {

557:             my_thread_num = hypre_GetThreadNum();

558:             offset =  y_size*my_thread_num;

559: #ifdef HYPRE_USING_OPENMP

560: #pragma omp for HYPRE_SMP_SCHEDULE

561: #endif

562:             for (i = 0; i < num_rows; i++)

563:             {

564:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

565:                {

566:                   j = A_j[jj];

567:                   y_data_expand[offset + j] += A_data[jj] * x_data[i];

[...]

573: #pragma omp for HYPRE_SMP_SCHEDULE

574: #endif

575:             for (i = 0; i < y_size; i++)

576:             {

577:                for (j = 0; j < num_threads; j++)

578:                {

579:                   y_data[i] += y_data_expand[j*y_size + i];

0x4df950 PUSH	%RBP

0x4df951 MOV	%RSP,%RBP

0x4df954 PUSH	%R15

0x4df956 PUSH	%R14

0x4df958 PUSH	%R13

0x4df95a PUSH	%R12

0x4df95c PUSH	%RBX

0x4df95d SUB	$0x78,%RSP

0x4df961 MOV	%R9,-0x30(%RBP)

0x4df965 MOV	%R8,%R14

0x4df968 MOV	%RCX,-0x88(%RBP)

0x4df96f MOV	%RDX,%R12

0x4df972 MOV	%RDI,%R13

0x4df975 MOV	0x30(%RBP),%RAX

0x4df979 MOV	%RAX,-0x80(%RBP)

0x4df97d MOV	0x28(%RBP),%RBX

0x4df981 MOV	0x20(%RBP),%RAX

0x4df985 MOV	%RAX,-0x38(%RBP)

0x4df989 MOV	0x18(%RBP),%RAX

0x4df98d MOV	%RAX,-0x50(%RBP)

0x4df991 MOV	0x10(%RBP),%R15

0x4df995 CALL	4e8ff0 <hypre_GetThreadNum>

0x4df99a MOV	-0x30(%RBP),%RDX

0x4df99e MOV	%R13,%RCX

0x4df9a1 TEST	%RDX,%RDX

0x4df9a4 JLE	4dfa24

0x4df9a6 MOV	%RAX,%R13

0x4df9a9 DEC	%RDX

0x4df9ac MOVL	$0,-0x44(%RBP)

0x4df9b3 MOV	%RCX,-0x78(%RBP)

0x4df9b7 MOV	(%RCX),%ESI

0x4df9b9 MOVQ	$0,-0x70(%RBP)

0x4df9c1 MOV	%RDX,-0x68(%RBP)

0x4df9c5 MOVQ	$0x1,-0x98(%RBP)

0x4df9d0 SUB	$0x8,%RSP

0x4df9d4 LEA	-0x98(%RBP),%RAX

0x4df9db LEA	-0x44(%RBP),%RCX

0x4df9df LEA	-0x70(%RBP),%R8

0x4df9e3 LEA	-0x68(%RBP),%R9

0x4df9e7 MOV	$0x536fb0,%EDI

0x4df9ec MOV	%ESI,-0x3c(%RBP)

0x4df9ef MOV	$0x22,%EDX

0x4df9f4 PUSH	$0x1

0x4df9f6 PUSH	$0x1

0x4df9f8 PUSH	%RAX

0x4df9f9 CALL	410420 <__kmpc_for_static_init_8@plt>

0x4df9fe ADD	$0x20,%RSP

0x4dfa02 MOV	-0x70(%RBP),%RCX

0x4dfa06 MOV	-0x68(%RBP),%R11

0x4dfa0a SUB	%RCX,%R11

0x4dfa0d JAE	4dfb6f

0x4dfa13 MOV	$0x536fd0,%EDI

0x4dfa18 MOV	-0x3c(%RBP),%ESI

0x4dfa1b CALL	410170 <__kmpc_for_static_fini@plt>

0x4dfa20 MOV	-0x78(%RBP),%RCX

0x4dfa24 MOV	(%RCX),%ESI

0x4dfa26 MOV	%RCX,%R12

0x4dfa29 MOV	$0x536ff0,%EDI

0x4dfa2e CALL	410560 <__kmpc_barrier@plt>

0x4dfa33 MOV	-0x38(%RBP),%R15

0x4dfa37 TEST	%R15,%R15

0x4dfa3a JLE	4dfb53

0x4dfa40 LEA	-0x1(%R15),%RAX

0x4dfa44 MOVL	$0,-0x40(%RBP)

0x4dfa4b MOV	(%R12),%R14D

0x4dfa4f MOVQ	$0,-0x60(%RBP)

0x4dfa57 MOV	%RAX,-0x58(%RBP)

0x4dfa5b MOVQ	$0x1,-0x90(%RBP)

0x4dfa66 SUB	$0x8,%RSP

0x4dfa6a LEA	-0x90(%RBP),%RAX

0x4dfa71 LEA	-0x40(%RBP),%RCX

0x4dfa75 LEA	-0x60(%RBP),%R8

0x4dfa79 LEA	-0x58(%RBP),%R9

0x4dfa7d MOV	$0x536f50,%EDI

0x4dfa82 MOV	%R14D,%ESI

0x4dfa85 MOV	$0x22,%EDX

0x4dfa8a PUSH	$0x1

0x4dfa8c PUSH	$0x1

0x4dfa8e PUSH	%RAX

0x4dfa8f CALL	410420 <__kmpc_for_static_init_8@plt>

0x4dfa94 ADD	$0x20,%RSP

0x4dfa98 MOV	-0x60(%RBP),%RAX

0x4dfa9c MOV	-0x58(%RBP),%RDX

0x4dfaa0 MOV	%RDX,%RCX

0x4dfaa3 SUB	%RAX,%RCX

0x4dfaa6 MOV	-0x80(%RBP),%R13

0x4dfaaa MOV	-0x50(%RBP),%R11

0x4dfaae JB	4dfb43

0x4dfab4 LEA	(%R11,%RDX,8),%RDI

0x4dfab8 MOV	%R15,%R8

0x4dfabb SAR	$0x3f,%R8

0x4dfabf AND	%R15,%R8

0x4dfac2 MOV	%RAX,%RSI

0x4dfac5 SUB	%R8,%RSI

0x4dfac8 IMUL	%R13,%R8

0x4dfacc ADD	%RSI,%R8

0x4dfacf XOR	%ESI,%ESI

0x4dfad1 TEST	%R15,%R15

0x4dfad4 LEA	(%RBX,%R8,8),%R8

0x4dfad8 CMOVG	%R15,%RSI

0x4dfadc CMP	%R8,%RDI

0x4dfadf JB	4dfcab

0x4dfae5 SUB	%RSI,%RDX

0x4dfae8 IMUL	%R13,%RSI

0x4dfaec ADD	%RDX,%RSI

0x4dfaef LEA	(%RBX,%RSI,8),%RDX

0x4dfaf3 LEA	(%R11,%RAX,8),%RSI

0x4dfaf7 CMP	%RSI,%RDX

0x4dfafa JB	4dfcab

0x4dfb00 LEA	(%RBX,%RAX,8),%RDX

0x4dfb04 SAL	$0x3,%R15

0x4dfb08 XOR	%ESI,%ESI

0x4dfb0a NOPW	(%RAX,%RAX,1)

(4340) 0x4dfb10 LEA	(%RAX,%RSI,1),%RDI

(4340) 0x4dfb14 VMOVSD	(%R11,%RDI,8),%XMM0

(4340) 0x4dfb1a MOV	%RDX,%R8

(4340) 0x4dfb1d MOV	%R13,%R9

  (4339) 0x4dfb20 VADDSD	(%R8),%XMM0,%XMM0

  (4339) 0x4dfb25 VMOVSD	%XMM0,(%R11,%RDI,8)

  (4339) 0x4dfb2b ADD	%R15,%R8

  (4339) 0x4dfb2e DEC	%R9

  (4339) 0x4dfb31 JNE	4dfb20

(4340) 0x4dfb33 LEA	0x1(%RSI),%RDI

(4340) 0x4dfb37 ADD	$0x8,%RDX

(4340) 0x4dfb3b CMP	%RCX,%RSI

(4340) 0x4dfb3e MOV	%RDI,%RSI

(4340) 0x4dfb41 JNE	4dfb10

0x4dfb43 MOV	$0x536f70,%EDI

0x4dfb48 MOV	%R14D,%ESI

0x4dfb4b VZEROUPPER

0x4dfb4e CALL	410170 <__kmpc_for_static_fini@plt>

0x4dfb53 MOV	(%R12),%ESI

0x4dfb57 MOV	$0x536f90,%EDI

0x4dfb5c ADD	$0x78,%RSP

0x4dfb60 POP	%RBX

0x4dfb61 POP	%R12

0x4dfb63 POP	%R13

0x4dfb65 POP	%R14

0x4dfb67 POP	%R15

0x4dfb69 POP	%RBP

0x4dfb6a JMP	410560

0x4dfb6f IMUL	-0x38(%RBP),%R13

0x4dfb74 XOR	%EDX,%EDX

0x4dfb76 MOV	%R11,-0x30(%RBP)

0x4dfb7a JMP	4dfb90

0x4dfb7c NOPL	(%RAX)

(4341) 0x4dfb80 LEA	0x1(%RDX),%RAX

(4341) 0x4dfb84 CMP	%R11,%RDX

(4341) 0x4dfb87 MOV	%RAX,%RDX

(4341) 0x4dfb8a JE	4dfa13

(4341) 0x4dfb90 LEA	(%RCX,%RDX,1),%RSI

(4341) 0x4dfb94 MOV	-0x88(%RBP),%RAX

(4341) 0x4dfb9b MOV	(%RAX,%RSI,8),%RDI

(4341) 0x4dfb9f MOV	0x8(%RAX,%RSI,8),%R8

(4341) 0x4dfba4 MOV	%R8,%R9

(4341) 0x4dfba7 SUB	%RDI,%R9

(4341) 0x4dfbaa JLE	4dfb80

(4341) 0x4dfbac CMP	$0x4,%R9

(4341) 0x4dfbb0 JB	4dfc5b

(4341) 0x4dfbb6 MOV	%R9,%R10

(4341) 0x4dfbb9 SHR	$0x2,%R10

(4341) 0x4dfbbd LEA	0x18(,%RDI,8),%R11

(4341) 0x4dfbc5 NOPW	%CS:(%RAX,%RAX,1)

  (4343) 0x4dfbd0 VMOVSD	(%R15,%RSI,8),%XMM0

  (4343) 0x4dfbd6 VMOVSD	-0x18(%R12,%R11,1),%XMM1

  (4343) 0x4dfbdd MOV	-0x18(%R14,%R11,1),%RAX

  (4343) 0x4dfbe2 ADD	%R13,%RAX

  (4343) 0x4dfbe5 VFMADD213SD	(%RBX,%RAX,8),%XMM0,%XMM1

  (4343) 0x4dfbeb VMOVSD	%XMM1,(%RBX,%RAX,8)

  (4343) 0x4dfbf0 VMOVSD	(%R15,%RSI,8),%XMM0

  (4343) 0x4dfbf6 VMOVSD	-0x10(%R12,%R11,1),%XMM1

  (4343) 0x4dfbfd MOV	-0x10(%R14,%R11,1),%RAX

  (4343) 0x4dfc02 ADD	%R13,%RAX

  (4343) 0x4dfc05 VFMADD213SD	(%RBX,%RAX,8),%XMM0,%XMM1

  (4343) 0x4dfc0b VMOVSD	%XMM1,(%RBX,%RAX,8)

  (4343) 0x4dfc10 VMOVSD	(%R15,%RSI,8),%XMM0

  (4343) 0x4dfc16 VMOVSD	-0x8(%R12,%R11,1),%XMM1

  (4343) 0x4dfc1d MOV	-0x8(%R14,%R11,1),%RAX

  (4343) 0x4dfc22 ADD	%R13,%RAX

  (4343) 0x4dfc25 VFMADD213SD	(%RBX,%RAX,8),%XMM0,%XMM1

  (4343) 0x4dfc2b VMOVSD	%XMM1,(%RBX,%RAX,8)

  (4343) 0x4dfc30 VMOVSD	(%R15,%RSI,8),%XMM0

  (4343) 0x4dfc36 VMOVSD	(%R12,%R11,1),%XMM1

  (4343) 0x4dfc3c MOV	(%R14,%R11,1),%RAX

  (4343) 0x4dfc40 ADD	%R13,%RAX

  (4343) 0x4dfc43 VFMADD213SD	(%RBX,%RAX,8),%XMM0,%XMM1

  (4343) 0x4dfc49 VMOVSD	%XMM1,(%RBX,%RAX,8)

  (4343) 0x4dfc4e ADD	$0x20,%R11

  (4343) 0x4dfc52 DEC	%R10

  (4343) 0x4dfc55 JNE	4dfbd0

(4341) 0x4dfc5b MOV	%R9,%R10

(4341) 0x4dfc5e AND	$-0x4,%R10

(4341) 0x4dfc62 CMP	%R9,%R10

(4341) 0x4dfc65 MOV	-0x30(%RBP),%R11

(4341) 0x4dfc69 JAE	4dfb80

(4341) 0x4dfc6f ADD	%R10,%RDI

(4341) 0x4dfc72 NOPW	%CS:(%RAX,%RAX,1)

  (4342) 0x4dfc80 VMOVSD	(%R15,%RSI,8),%XMM0

  (4342) 0x4dfc86 VMOVSD	(%R12,%RDI,8),%XMM1

  (4342) 0x4dfc8c MOV	(%R14,%RDI,8),%RAX

  (4342) 0x4dfc90 ADD	%R13,%RAX

  (4342) 0x4dfc93 VFMADD213SD	(%RBX,%RAX,8),%XMM0,%XMM1

  (4342) 0x4dfc99 VMOVSD	%XMM1,(%RBX,%RAX,8)

  (4342) 0x4dfc9e INC	%RDI

  (4342) 0x4dfca1 CMP	%RDI,%R8

  (4342) 0x4dfca4 JNE	4dfc80

(4341) 0x4dfca6 JMP	4dfb80

0x4dfcab MOV	%R13,%RDX

0x4dfcae AND	$-0x4,%RDX

0x4dfcb2 LEA	-0x1(%RDX),%RSI

0x4dfcb6 VPBROADCASTQ	%R15,%YMM0

0x4dfcbc LEA	(,%R15,8),%RDI

0x4dfcc4 XOR	%R8D,%R8D

0x4dfcc7 VMOVDQU	0x1f3b1(%RIP),%YMM1

0x4dfccf MOV	%RAX,%R9

0x4dfcd2 JMP	4dfcfd

0x4dfcd4 NOPW	%CS:(%RAX,%RAX,1)

(4337) 0x4dfce0 MOV	-0x50(%RBP),%R11

(4337) 0x4dfce4 VMOVSD	%XMM2,(%R11,%R10,8)

(4337) 0x4dfcea LEA	0x1(%R8),%R10

(4337) 0x4dfcee INC	%R9

(4337) 0x4dfcf1 CMP	%RCX,%R8

(4337) 0x4dfcf4 MOV	%R10,%R8

(4337) 0x4dfcf7 JE	4dfb43

(4337) 0x4dfcfd LEA	(%RAX,%R8,1),%R10

(4337) 0x4dfd01 VMOVSD	(%R11,%R10,8),%XMM2

(4337) 0x4dfd07 TEST	%RDX,%RDX

(4337) 0x4dfd0a JE	4dfd80

(4337) 0x4dfd0c VPBROADCASTQ	%R10,%YMM4

(4337) 0x4dfd12 VXORPD	%XMM3,%XMM3,%XMM3

(4337) 0x4dfd16 XOR	%R11D,%R11D

(4337) 0x4dfd19 NOPL	(%RAX)

  (4338) 0x4dfd20 VPBROADCASTQ	%R11,%YMM5

  (4338) 0x4dfd26 VPADDQ	%YMM1,%YMM5,%YMM5

  (4338) 0x4dfd2a VPMULLQ	%YMM5,%YMM0,%YMM5

  (4338) 0x4dfd30 VPADDQ	%YMM5,%YMM4,%YMM5

  (4338) 0x4dfd34 VXORPD	%XMM6,%XMM6,%XMM6

  (4338) 0x4dfd38 KXNORW	%K0,%K0,%K1

  (4338) 0x4dfd3c VGATHERQPD	(%RBX,%YMM5,8),%YMM6{%K1}

  (4338) 0x4dfd43 VADDPD	%YMM6,%YMM3,%YMM3

  (4338) 0x4dfd47 ADD	$0x4,%R11

  (4338) 0x4dfd4b CMP	%RSI,%R11

  (4338) 0x4dfd4e JLE	4dfd20

(4337) 0x4dfd50 VEXTRACTF128	$0x1,%YMM3,%XMM4

(4337) 0x4dfd56 VADDPD	%XMM4,%XMM3,%XMM3

(4337) 0x4dfd5a VSHUFPD	$0x1,%XMM3,%XMM3,%XMM4

(4337) 0x4dfd5f VADDSD	%XMM4,%XMM3,%XMM3

(4337) 0x4dfd63 VADDSD	%XMM3,%XMM2,%XMM2

(4337) 0x4dfd67 MOV	%RDX,%R15

(4337) 0x4dfd6a CMP	%R13,%RDX

(4337) 0x4dfd6d JE	4dfce0

(4337) 0x4dfd73 JMP	4dfd83

0x4dfd75 NOPW	%CS:(%RAX,%RAX,1)

(4337) 0x4dfd80 XOR	%R15D,%R15D

(4337) 0x4dfd83 MOV	%R13,%R11

(4337) 0x4dfd86 SUB	%R15,%R11

(4337) 0x4dfd89 IMUL	-0x38(%RBP),%R15

(4337) 0x4dfd8e ADD	%R9,%R15

(4337) 0x4dfd91 LEA	(%RBX,%R15,8),%R15

(4337) 0x4dfd95 NOPW	%CS:(%RAX,%RAX,1)

  (4336) 0x4dfda0 VADDSD	(%R15),%XMM2,%XMM2

  (4336) 0x4dfda5 ADD	%RDI,%R15

  (4336) 0x4dfda8 DEC	%R11

  (4336) 0x4dfdab JNE	4dfda0

(4337) 0x4dfdad JMP	4dfce0

0x4dfdb2 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	csr_matvec.c:554-579
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:554-567,573-579.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.17 to 3.00 cycles (8.39x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_barrier@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560
__kmpc_for_static_fini@plt: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:573
__kmpc_for_static_init_8@plt: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:573
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:557

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:573

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 172 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	144
nb uops	151
loop length	587
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	0
nb stack references	20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.17 cycles
front end	25.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.90	6.80	9.00	9.00	17.00	6.80	6.70	17.00	17.00	17.00	6.80	9.00
cycles	6.90	7.20	9.00	9.00	17.00	6.80	6.70	17.00	17.00	17.00	6.80	9.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	25.17
Dispatch	17.00
Overall L1	25.17

Vectorization ratios

all	5%
load	25%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Vector efficiency ratios

all	11%
load	20%
store	9%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.17 cycles. At this rate:

3% of peak load performance is reached (6.83 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.61 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 25.17 to 17.00 cycles (1.48x speedup).

ASM code

In the binary file, the address of the function is: 4df950

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 4e8ff0 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R13,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 4dfa24 <hypre_CSRMatrixMatvecT.extracted.49+0xd4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
DEC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVL $0,-0x44(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RCX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RCX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVQ $0,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RDX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x98(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x44(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x70(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x68(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x536fb0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 410420 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x70(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JAE 4dfb6f <hypre_CSRMatrixMatvecT.extracted.49+0x21f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x536fd0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV -0x3c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 410170 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x78(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x536ff0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 410560 <__kmpc_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %R15,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 4dfb53 <hypre_CSRMatrixMatvecT.extracted.49+0x203>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%R15),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%R12),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x90(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x60(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x58(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x536f50,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 410420 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x58(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x80(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x50(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JB 4dfb43 <hypre_CSRMatrixMatvecT.extracted.49+0x1f3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%R11,%RDX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAR $0x3f,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND %R15,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R8,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %R13,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RSI,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %R15,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
LEA (%RBX,%R8,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMOVG %R15,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
CMP %R8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 4dfcab <hypre_CSRMatrixMatvecT.extracted.49+0x35b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %R13,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RBX,%RSI,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R11,%RAX,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 4dfcab <hypre_CSRMatrixMatvecT.extracted.49+0x35b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%RBX,%RAX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x536f70,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 410170 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV (%R12),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x536f90,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 410560 <__kmpc_barrier@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
IMUL -0x38(%RBP),%R13	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 4dfb90 <hypre_CSRMatrixMatvecT.extracted.49+0x240>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R13,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA -0x1(%RDX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %R15,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA (,%R15,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVDQU 0x1f3b1(%RIP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 4dfcfd <hypre_CSRMatrixMatvecT.extracted.49+0x3ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	csr_matvec.c:554-579
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:554-567,573-579.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.17 to 3.00 cycles (8.39x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

__kmpc_barrier@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560
__kmpc_for_static_fini@plt: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:573
__kmpc_for_static_init_8@plt: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:573
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:557

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:573

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 172 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	144
nb uops	151
loop length	587
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	0
nb stack references	20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.17 cycles
front end	25.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.90	6.80	9.00	9.00	17.00	6.80	6.70	17.00	17.00	17.00	6.80	9.00
cycles	6.90	7.20	9.00	9.00	17.00	6.80	6.70	17.00	17.00	17.00	6.80	9.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	25.17
Dispatch	17.00
Overall L1	25.17

Vectorization ratios

all	5%
load	25%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Vector efficiency ratios

all	11%
load	20%
store	9%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.17 cycles. At this rate:

3% of peak load performance is reached (6.83 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.61 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4df950

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 4e8ff0 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R13,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 4dfa24 <hypre_CSRMatrixMatvecT.extracted.49+0xd4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
DEC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVL $0,-0x44(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RCX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RCX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVQ $0,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RDX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x98(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x44(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x70(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x68(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x536fb0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 410420 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x70(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JAE 4dfb6f <hypre_CSRMatrixMatvecT.extracted.49+0x21f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x536fd0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV -0x3c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 410170 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x78(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x536ff0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 410560 <__kmpc_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %R15,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 4dfb53 <hypre_CSRMatrixMatvecT.extracted.49+0x203>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%R15),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%R12),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x90(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x60(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x58(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x536f50,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 410420 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x58(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x80(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x50(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JB 4dfb43 <hypre_CSRMatrixMatvecT.extracted.49+0x1f3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%R11,%RDX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAR $0x3f,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND %R15,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R8,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %R13,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RSI,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %R15,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
LEA (%RBX,%R8,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMOVG %R15,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
CMP %R8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 4dfcab <hypre_CSRMatrixMatvecT.extracted.49+0x35b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %R13,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RBX,%RSI,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R11,%RAX,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 4dfcab <hypre_CSRMatrixMatvecT.extracted.49+0x35b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%RBX,%RAX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x536f70,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 410170 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV (%R12),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x536f90,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 410560 <__kmpc_barrier@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
IMUL -0x38(%RBP),%R13	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 4dfb90 <hypre_CSRMatrixMatvecT.extracted.49+0x240>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R13,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA -0x1(%RDX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %R15,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA (,%R15,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVDQU 0x1f3b1(%RIP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 4dfcfd <hypre_CSRMatrixMatvecT.extracted.49+0x3ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMatvecT.extracted.49–	1.23	0.66
▼Loop 4341 - csr_matvec.c:560-567 - exec–	0.56	0.24
○Loop 4342 - csr_matvec.c:564-567 - exec	0.53	0.23
○Loop 4343 - csr_matvec.c:564-567 - exec	0.11	0.05
▼Loop 4337 - csr_matvec.c:560-579 - exec–	0.00	0.01
○Loop 4338 - csr_matvec.c:577-579 - exec	0.03	0.01
○Loop 4336 - csr_matvec.c:577-579 - exec	0.00	0.00
▼Loop 4340 - csr_matvec.c:573-579 - exec–	0.00	0.00
○Loop 4339 - csr_matvec.c:577-579 - exec	0.00	0.00

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Execution units bottlenecks

512-bits vectorization

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CALL instructions

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Complex instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code