OV - exec - Function hypre_IJMatrixSetValuesOMPParCSR.extracted.28

	Function: hypre_IJMatrixSetValuesOMPParCSR.extracted.28	Module: exec	Source: IJMatrix_parcsr.c:3240-3484 [...]	Coverage (incl. loops): 1.16% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 3240 - 3484

--------------------------------------------------------------------------------

3240: #pragma omp parallel

[...]

3256:          num_threads = hypre_NumActiveThreads();

3257:          my_thread_num = hypre_GetThreadNum();

3258:

3259:          len = nrows/num_threads;

3260:          rest = nrows - len*num_threads;

3261:

3262:          if (my_thread_num < rest)

3263:          {

3264:             ns = my_thread_num*(len+1);

3265:             ne = (my_thread_num+1)*(len+1);

3266:          }

3267:          else

3268:          {

3269:             ns = my_thread_num*len+rest;

3270:             ne = (my_thread_num+1)*len+rest;

3271:          }

3272:

3273:          value_start[my_thread_num] = 0;

3274:          for (ii=ns; ii < ne; ii++)

3275:             value_start[my_thread_num] += ncols[ii];

3276:

3277: #ifdef HYPRE_USING_OPENMP

3278: #pragma omp barrier

3279: #endif

3280:          if (my_thread_num == 0)

3281:          {

3282:             for (i=0; i < max_num_threads; i++)

3283:                value_start[i+1] += value_start[i];

[...]

3289:          if (my_thread_num)

3290:             indx = value_start[my_thread_num-1];

3291:          for (ii=ns; ii < ne; ii++)

3292:          {

3293:             row = rows[ii];

3294:             n = ncols[ii];

3295:             /* processor owns the row */

3296:             if (row >= row_partitioning[pstart] && row < row_partitioning[pstart+1])

3297:             {

3298:                row_local = row - row_partitioning[pstart];

3299:                /* compute local row number */

3300:                if (need_aux)

3301:                {

3302:                   local_j = aux_j[row_local];

3303:                   local_data = aux_data[row_local];

3304:    	          space = row_space[row_local];

3305:    	          old_size = row_length[row_local];

3306:    	          size = space - old_size;

3307:    	          if (size < n)

3308:       	          {

3309:       	             size = n - size;

3310:       	             tmp_j = hypre_CTAlloc(HYPRE_Int,size);

3311:       	             tmp_data = hypre_CTAlloc(HYPRE_Complex,size);

3312:       	          }

3313:       	          tmp_indx = 0;

3314:       	          not_found = 1;

3315:       	          size = old_size;

3316:                   for (i=0; i < n; i++)

3317:       	          {

3318:       	             for (j=0; j < old_size; j++)

3319:       	             {

3320:       	                if (local_j[j] == cols[indx])

3321:       	                {

3322:                            local_data[j] = values[indx];

[...]

3329:       	                if (size < space)

3330:       	                {

3331:       	                   local_j[size] = cols[indx];

3332:       	                   local_data[size++] = values[indx];

3333:       	                }

3334:       	                else

3335:       	                {

3336:       	                   tmp_j[tmp_indx] = cols[indx];

3337:       	                   tmp_data[tmp_indx++] = values[indx];

[...]

3344:                   row_length[row_local] = size+tmp_indx;

3345:

3346:                   if (tmp_indx)

3347:                   {

3348:    	             aux_j[row_local] = hypre_TReAlloc(aux_j[row_local],HYPRE_Int,

3349:                                                     size+tmp_indx);

3350:    	             aux_data[row_local] = hypre_TReAlloc(aux_data[row_local],

3351:                                                        HYPRE_Complex,size+tmp_indx);

3352:                      row_space[row_local] = size+tmp_indx;

3353:                      local_j = aux_j[row_local];

[...]

3359:    	          for (i=0; i < tmp_indx; i++)

3360:    	          {

3361:    	             local_j[cnt] = tmp_j[i];

3362:    	             local_data[cnt++] = tmp_data[i];

3363: 	          }

3364:

3365: 	          if (tmp_j)

3366: 	          {

3367: 	             hypre_TFree(tmp_j);

3368: 	             hypre_TFree(tmp_data);

[...]

3376: 	          offd_indx = hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local];

3377: 	          diag_indx = hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local];

3378: 	          cnt_diag = diag_indx;

3379: 	          cnt_offd = offd_indx;

3380: 	          diag_space = diag_i[row_local+1];

3381: 	          offd_space = offd_i[row_local+1];

3382: 	          not_found = 1;

3383:   	          for (i=0; i < n; i++)

3384: 	          {

3385: 	             if (cols[indx] < col_0 || cols[indx] > col_n)

3386:                      /* insert into offd */

3387: 	             {

3388: 	                for (j=offd_i[row_local]; j < offd_indx; j++)

3389: 	                {

3390: 		           if (offd_j[j] == cols[indx])

3391: 		           {

3392:                               offd_data[j] = values[indx];

[...]

3399: 	                   if (cnt_offd < offd_space)

3400: 	                   {

3401: 	                      offd_j[cnt_offd] = cols[indx];

3402: 	                      offd_data[cnt_offd++] = values[indx];

3403: 	                   }

3404: 	                   else

3405: 	 	           {

3406:                               hypre_error(HYPRE_ERROR_GENERIC);

3407: #ifdef HYPRE_USING_OPENMP

3408: #pragma omp atomic

3409: #endif

3410:                               error_flag++;

[...]

3422: 	                for (j=diag_i[row_local]; j < diag_indx; j++)

3423: 	                {

3424: 		           if (diag_j[j] == cols[indx])

3425: 		           {

3426:                               diag_data[j] = values[indx];

[...]

3433: 	                   if (cnt_diag < diag_space)

3434: 	                   {

3435: 	                      diag_j[cnt_diag] = cols[indx];

3436: 	                      diag_data[cnt_diag++] = values[indx];

3437: 	                   }

3438: 	                   else

3439: 	 	           {

3440:                               hypre_error(HYPRE_ERROR_GENERIC);

3441: #ifdef HYPRE_USING_OPENMP

3442: #pragma omp atomic

3443: #endif

3444:                               error_flag++;

3445: 	    	              if (print_level)

[...]

3454: 	             indx++;

3455: 	          }

3456:

3457:                   hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local] = cnt_diag;

3458:                   hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local] = cnt_offd;

[...]

3466:                indx +=  n;

3467:    	       if (aux_matrix)

3468:                {

3469:                   col_indx = 0;

3470:                   for (i=0; i < off_proc_i_indx; i=i+2)

3471:                   {

3472: 	             row_len = off_proc_i[i+1];

3473: 	             if (off_proc_i[i] == row)

3474: 		     {

3475: 		        for (j=0; j < n; j++)

3476: 		        {

3477: 			   cnt1 = col_indx;

3478: 			   for (k=0; k < row_len; k++)

3479: 			   {

3480: 			      if (off_proc_j[cnt1] == cols[j])

3481: 			      {

3482:                                  off_proc_j[cnt1++] = -1;

3483:                		         /*cancel_indx++;*/

3484: 	                         offproc_cnt[my_thread_num]++;

0x4d3d20 PUSH	%RBP

0x4d3d21 MOV	%RSP,%RBP

0x4d3d24 PUSH	%R15

0x4d3d26 PUSH	%R14

0x4d3d28 PUSH	%R13

0x4d3d2a PUSH	%R12

0x4d3d2c PUSH	%RBX

0x4d3d2d SUB	$0x98,%RSP

0x4d3d34 MOV	%R9,%RBX

0x4d3d37 MOV	%R8,-0x60(%RBP)

0x4d3d3b MOV	%RCX,-0x48(%RBP)

0x4d3d3f MOV	%RDX,%R15

0x4d3d42 MOV	%RDI,%R12

0x4d3d45 CALL	4e8fe0 <hypre_NumActiveThreads>

0x4d3d4a MOV	%RAX,%R13

0x4d3d4d CALL	4e8ff0 <hypre_GetThreadNum>

0x4d3d52 MOV	%RAX,%R14

0x4d3d55 MOV	%R13,%RAX

0x4d3d58 OR	%R15,%RAX

0x4d3d5b SHR	$0x20,%RAX

0x4d3d5f JE	4d3d6b

0x4d3d61 MOV	%R15,%RAX

0x4d3d64 CQTO

0x4d3d66 IDIV	%R13

0x4d3d69 JMP	4d3d73

0x4d3d6b MOV	%R15D,%EAX

0x4d3d6e XOR	%EDX,%EDX

0x4d3d70 DIV	%R13D

0x4d3d73 MOV	%R12,%R13

0x4d3d76 MOV	0xb8(%RBP),%R15

0x4d3d7d LEA	0x1(%R14),%RCX

0x4d3d81 CMP	%RDX,%R14

0x4d3d84 JGE	4d3d97

0x4d3d86 LEA	0x1(%RAX),%RSI

0x4d3d8a MOV	%RSI,%R8

0x4d3d8d IMUL	%R14,%R8

0x4d3d91 IMUL	%RCX,%RSI

0x4d3d95 JMP	4d3dab

0x4d3d97 MOV	%RAX,%R8

0x4d3d9a IMUL	%R14,%R8

0x4d3d9e ADD	%RDX,%R8

0x4d3da1 IMUL	%RAX,%RCX

0x4d3da5 ADD	%RDX,%RCX

0x4d3da8 MOV	%RCX,%RSI

0x4d3dab MOVQ	$0,(%R15,%R14,8)

0x4d3db3 MOV	%RSI,-0x50(%RBP)

0x4d3db7 CMP	%RSI,%R8

0x4d3dba MOV	%R8,%R12

0x4d3dbd JGE	4d3e60

0x4d3dc3 CMP	%RDX,%R14

0x4d3dc6 CMOVL	%R14,%RDX

0x4d3dca IMUL	%R14,%RAX

0x4d3dce MOV	-0x50(%RBP),%RDI

0x4d3dd2 SUB	%RDX,%RDI

0x4d3dd5 SUB	%RAX,%RDI

0x4d3dd8 MOV	%RDI,%RCX

0x4d3ddb AND	$-0x4,%RCX

0x4d3ddf JE	4d3e36

0x4d3de1 LEA	-0x1(%RCX),%RSI

0x4d3de5 MOV	%R8,%R9

0x4d3de8 MOV	-0x48(%RBP),%R8

0x4d3dec LEA	(%R8,%R9,8),%R8

0x4d3df0 VPXOR	%XMM0,%XMM0,%XMM0

0x4d3df4 XOR	%R9D,%R9D

0x4d3df7 NOPW	(%RAX,%RAX,1)

(4059) 0x4d3e00 VPADDQ	(%R8,%R9,8),%YMM0,%YMM0

(4059) 0x4d3e06 ADD	$0x4,%R9

(4059) 0x4d3e0a CMP	%RSI,%R9

(4059) 0x4d3e0d JBE	4d3e00

0x4d3e0f VEXTRACTI128	$0x1,%YMM0,%XMM1

0x4d3e15 VPADDQ	%XMM1,%XMM0,%XMM0

0x4d3e19 VPSHUFD	$-0x12,%XMM0,%XMM1

0x4d3e1e VPADDQ	%XMM1,%XMM0,%XMM0

0x4d3e22 VMOVQ	%XMM0,%RSI

0x4d3e27 CMP	%RCX,%RDI

0x4d3e2a MOV	-0x48(%RBP),%RDI

0x4d3e2e MOV	-0x50(%RBP),%R8

0x4d3e32 JNE	4d3e42

0x4d3e34 JMP	4d3e5c

0x4d3e36 XOR	%ECX,%ECX

0x4d3e38 XOR	%ESI,%ESI

0x4d3e3a MOV	-0x48(%RBP),%RDI

0x4d3e3e MOV	-0x50(%RBP),%R8

0x4d3e42 ADD	%RDX,%RCX

0x4d3e45 ADD	%RAX,%RCX

0x4d3e48 NOPL	(%RAX,%RAX,1)

(4058) 0x4d3e50 ADD	(%RDI,%RCX,8),%RSI

(4058) 0x4d3e54 INC	%RCX

(4058) 0x4d3e57 CMP	%RCX,%R8

(4058) 0x4d3e5a JNE	4d3e50

0x4d3e5c MOV	%RSI,(%R15,%R14,8)

0x4d3e60 MOV	(%R13),%ESI

0x4d3e64 MOV	$0x536530,%EDI

0x4d3e69 VZEROUPPER

0x4d3e6c CALL	410560 <__kmpc_barrier@plt>

0x4d3e71 TEST	%R14,%R14

0x4d3e74 JNE	4d3f14

0x4d3e7a MOV	0xc8(%RBP),%RAX

0x4d3e81 TEST	%RAX,%RAX

0x4d3e84 JLE	4d3f14

0x4d3e8a CMP	$0x8,%RAX

0x4d3e8e JB	4d3ee7

0x4d3e90 MOV	%RAX,%RCX

0x4d3e93 SHR	$0x3,%RCX

0x4d3e97 MOV	(%R15),%RDX

0x4d3e9a LEA	0x40(%R15),%RSI

0x4d3e9e XCHG	%AX,%AX

(4057) 0x4d3ea0 ADD	-0x38(%RSI),%RDX

(4057) 0x4d3ea4 MOV	%RDX,-0x38(%RSI)

(4057) 0x4d3ea8 ADD	-0x30(%RSI),%RDX

(4057) 0x4d3eac MOV	%RDX,-0x30(%RSI)

(4057) 0x4d3eb0 ADD	-0x28(%RSI),%RDX

(4057) 0x4d3eb4 MOV	%RDX,-0x28(%RSI)

(4057) 0x4d3eb8 ADD	-0x20(%RSI),%RDX

(4057) 0x4d3ebc MOV	%RDX,-0x20(%RSI)

(4057) 0x4d3ec0 ADD	-0x18(%RSI),%RDX

(4057) 0x4d3ec4 MOV	%RDX,-0x18(%RSI)

(4057) 0x4d3ec8 ADD	-0x10(%RSI),%RDX

(4057) 0x4d3ecc MOV	%RDX,-0x10(%RSI)

(4057) 0x4d3ed0 ADD	-0x8(%RSI),%RDX

(4057) 0x4d3ed4 MOV	%RDX,-0x8(%RSI)

(4057) 0x4d3ed8 ADD	(%RSI),%RDX

(4057) 0x4d3edb MOV	%RDX,(%RSI)

(4057) 0x4d3ede ADD	$0x40,%RSI

(4057) 0x4d3ee2 DEC	%RCX

(4057) 0x4d3ee5 JNE	4d3ea0

0x4d3ee7 MOV	%RAX,%RCX

0x4d3eea AND	$-0x8,%RCX

0x4d3eee CMP	%RAX,%RCX

0x4d3ef1 JAE	4d3f14

0x4d3ef3 MOV	(%R15,%RCX,8),%RDX

0x4d3ef7 NOPW	(%RAX,%RAX,1)

(4056) 0x4d3f00 LEA	(%R15,%RCX,8),%RSI

(4056) 0x4d3f04 INC	%RCX

(4056) 0x4d3f07 ADD	0x8(%RSI),%RDX

(4056) 0x4d3f0b MOV	%RDX,0x8(%RSI)

(4056) 0x4d3f0f CMP	%RCX,%RAX

(4056) 0x4d3f12 JNE	4d3f00

0x4d3f14 MOV	(%R13),%ESI

0x4d3f18 MOV	$0x536550,%EDI

0x4d3f1d CALL	410560 <__kmpc_barrier@plt>

0x4d3f22 TEST	%R14,%R14

0x4d3f25 JE	4d3f2e

0x4d3f27 MOV	-0x8(%R15,%R14,8),%RAX

0x4d3f2c JMP	4d3f30

0x4d3f2e XOR	%EAX,%EAX

0x4d3f30 MOV	%RAX,-0x30(%RBP)

0x4d3f34 MOV	-0x60(%RBP),%RDX

0x4d3f38 MOV	-0x48(%RBP),%RSI

0x4d3f3c MOV	%R12,%R9

0x4d3f3f MOV	-0x50(%RBP),%R8

0x4d3f43 CMP	%R8,%R12

0x4d3f46 JGE	4d4a73

0x4d3f4c MOV	0xb0(%RBP),%RAX

0x4d3f53 MOV	0xa8(%RBP),%RDI

0x4d3f5a MOV	0x98(%RBP),%R10

0x4d3f61 MOV	0x18(%RBP),%RCX

0x4d3f65 TEST	%RCX,%RCX

0x4d3f68 SETE	%CL

0x4d3f6b LEA	(%RAX,%R14,8),%R15

0x4d3f6f TEST	%R10,%R10

0x4d3f72 SETLE	%AL

0x4d3f75 OR	%CL,%AL

0x4d3f77 MOV	%AL,-0x39(%RBP)

0x4d3f7a DEC	%R10

0x4d3f7d SHR	$0x1,%R10

0x4d3f80 MOV	%R10,-0xb8(%RBP)

0x4d3f87 MOV	0x20(%RBP),%RAX

0x4d3f8b LEA	0x18(%RDI),%RCX

0x4d3f8f MOV	%RCX,-0xb0(%RBP)

0x4d3f96 XOR	%ECX,%ECX

0x4d3f98 MOV	%RCX,-0x88(%RBP)

0x4d3f9f JMP	4d4009

(4035) 0x4d3fa1 SAL	$0x3,%RDX

(4035) 0x4d3fa5 MOV	%R12,-0x88(%RBP)

(4035) 0x4d3fac MOV	%R13,%RSI

(4035) 0x4d3faf MOV	%RDX,%R12

(4035) 0x4d3fb2 CALL	4f02d0 <_intel_fast_memcpy>

(4035) 0x4d3fb7 MOV	%R14,%RDI

(4035) 0x4d3fba MOV	-0x88(%RBP),%RSI

(4035) 0x4d3fc1 MOV	%R12,%RDX

(4035) 0x4d3fc4 CALL	4f02d0 <_intel_fast_memcpy>

(4035) 0x4d3fc9 MOV	%R13,%RDI

(4035) 0x4d3fcc VZEROUPPER

(4035) 0x4d3fcf CALL	4e7390 <hypre_Free>

(4035) 0x4d3fd4 MOV	-0x88(%RBP),%RDI

(4035) 0x4d3fdb CALL	4e7390 <hypre_Free>

(4035) 0x4d3fe0 XOR	%EAX,%EAX

(4035) 0x4d3fe2 MOV	%RAX,-0x88(%RBP)

(4035) 0x4d3fe9 MOV	-0x60(%RBP),%RDX

(4035) 0x4d3fed MOV	-0x48(%RBP),%RSI

(4035) 0x4d3ff1 MOV	-0x68(%RBP),%R9

(4035) 0x4d3ff5 MOV	-0x50(%RBP),%R8

(4035) 0x4d3ff9 MOV	0x20(%RBP),%RAX

(4035) 0x4d3ffd INC	%R9

(4035) 0x4d4000 CMP	%R8,%R9

(4035) 0x4d4003 JGE	4d4a73

(4035) 0x4d4009 MOV	(%RDX,%R9,8),%R13

(4035) 0x4d400d MOV	(%RSI,%R9,8),%R14

(4035) 0x4d4011 MOV	%R13,-0x58(%RBP)

(4035) 0x4d4015 SUB	(%RAX),%R13

(4035) 0x4d4018 JL	4d40d0

(4035) 0x4d401e MOV	-0x58(%RBP),%RCX

(4035) 0x4d4022 CMP	0x8(%RAX),%RCX

(4035) 0x4d4026 JGE	4d40d0

(4035) 0x4d402c CMPQ	$0,0x58(%RBP)

(4035) 0x4d4031 MOV	%R13,-0x38(%RBP)

(4035) 0x4d4035 JE	4d4288

(4035) 0x4d403b MOV	0x38(%RBP),%RAX

(4035) 0x4d403f MOV	(%RAX,%R13,8),%R12

(4035) 0x4d4043 MOV	0x40(%RBP),%RAX

(4035) 0x4d4047 MOV	(%RAX,%R13,8),%RAX

(4035) 0x4d404b MOV	%RAX,-0x70(%RBP)

(4035) 0x4d404f MOV	0x50(%RBP),%RAX

(4035) 0x4d4053 MOV	(%RAX,%R13,8),%RCX

(4035) 0x4d4057 MOV	0x48(%RBP),%RAX

(4035) 0x4d405b MOV	(%RAX,%R13,8),%R13

(4035) 0x4d405f MOV	%RCX,-0x80(%RBP)

(4035) 0x4d4063 MOV	%RCX,%RAX

(4035) 0x4d4066 SUB	%R13,%RAX

(4035) 0x4d4069 MOV	%R14,%RDI

(4035) 0x4d406c SUB	%RAX,%RDI

(4035) 0x4d406f MOV	%R9,-0x68(%RBP)

(4035) 0x4d4073 JLE	4d4632

(4035) 0x4d4079 MOV	$0x8,%ESI

(4035) 0x4d407e MOV	%RDI,-0x58(%RBP)

(4035) 0x4d4082 VZEROUPPER

(4035) 0x4d4085 CALL	4e72c0 <hypre_CAlloc>

(4035) 0x4d408a MOV	%RAX,-0x78(%RBP)

(4035) 0x4d408e MOV	$0x8,%ESI

(4035) 0x4d4093 MOV	-0x58(%RBP),%RDI

(4035) 0x4d4097 CALL	4e72c0 <hypre_CAlloc>

(4035) 0x4d409c MOV	%RAX,-0x88(%RBP)

(4035) 0x4d40a3 MOV	-0x30(%RBP),%RDI

(4035) 0x4d40a7 TEST	%R14,%R14

(4035) 0x4d40aa JG	4d4645

(4035) 0x4d40b0 MOV	0x48(%RBP),%RAX

(4035) 0x4d40b4 MOV	-0x38(%RBP),%RCX

(4035) 0x4d40b8 MOV	%R13,(%RAX,%RCX,8)

(4035) 0x4d40bc JMP	4d4936

0x4d40c1 NOPW	%CS:(%RAX,%RAX,1)

(4035) 0x4d40d0 ADD	%R14,-0x30(%RBP)

(4035) 0x4d40d4 CMPB	$0,-0x39(%RBP)

(4035) 0x4d40d8 JNE	4d3ffd

(4035) 0x4d40de TEST	%R14,%R14

(4035) 0x4d40e1 JLE	4d3ffd

(4035) 0x4d40e7 MOV	%R9,-0x68(%RBP)

(4035) 0x4d40eb DEC	%R14

(4035) 0x4d40ee XOR	%ECX,%ECX

(4035) 0x4d40f0 XOR	%EAX,%EAX

(4035) 0x4d40f2 JMP	4d4114

0x4d40f4 NOPW	%CS:(%RAX,%RAX,1)

  (4036) 0x4d4100 LEA	0x1(%RAX),%RDX

  (4036) 0x4d4104 CMP	-0xb8(%RBP),%RAX

  (4036) 0x4d410b MOV	%RDX,%RAX

  (4036) 0x4d410e JE	4d3fe9

  (4036) 0x4d4114 MOV	%RCX,%R9

  (4036) 0x4d4117 MOV	%RAX,%RSI

  (4036) 0x4d411a SAL	$0x4,%RSI

  (4036) 0x4d411e MOV	0xa0(%RBP),%RDI

  (4036) 0x4d4125 MOV	0x8(%RDI,%RSI,1),%RDX

  (4036) 0x4d412a ADD	%RDX,%RCX

  (4036) 0x4d412d MOV	-0x58(%RBP),%R8

  (4036) 0x4d4131 CMP	%R8,(%RDI,%RSI,1)

  (4036) 0x4d4135 JNE	4d4100

  (4036) 0x4d4137 TEST	%RDX,%RDX

  (4036) 0x4d413a JLE	4d4100

  (4036) 0x4d413c MOV	0xa8(%RBP),%RSI

  (4036) 0x4d4143 LEA	-0x8(%RSI,%RCX,8),%RDI

  (4036) 0x4d4148 LEA	(%RSI,%R9,8),%RSI

  (4036) 0x4d414c CMP	%R15,%RDI

  (4036) 0x4d414f JB	4d41a0

  (4036) 0x4d4151 CMP	%RSI,%R15

  (4036) 0x4d4154 JB	4d41a0

  (4036) 0x4d4156 XOR	%EDI,%EDI

  (4036) 0x4d4158 JMP	4d416c

0x4d415a NOPW	(%RAX,%RAX,1)

    (4040) 0x4d4160 LEA	0x1(%RDI),%R8

    (4040) 0x4d4164 CMP	%R14,%RDI

    (4040) 0x4d4167 MOV	%R8,%RDI

    (4040) 0x4d416a JE	4d4100

    (4040) 0x4d416c MOV	(%RBX,%RDI,8),%R8

    (4040) 0x4d4170 XOR	%R9D,%R9D

    (4040) 0x4d4173 JMP	4d4188

0x4d4175 NOPW	%CS:(%RAX,%RAX,1)

      (4041) 0x4d4180 INC	%R9

      (4041) 0x4d4183 CMP	%R9,%RDX

      (4041) 0x4d4186 JE	4d4160

      (4041) 0x4d4188 CMP	%R8,(%RSI,%R9,8)

      (4041) 0x4d418c JNE	4d4180

      (4041) 0x4d418e MOVQ	$-0x1,(%RSI,%R9,8)

      (4041) 0x4d4196 INCQ	(%R15)

      (4041) 0x4d4199 JMP	4d4180

0x4d419b NOPL	(%RAX,%RAX,1)

  (4036) 0x4d41a0 MOV	%RDX,%RDI

  (4036) 0x4d41a3 SHR	$0x2,%RDI

  (4036) 0x4d41a7 MOV	%RDX,%R8

  (4036) 0x4d41aa AND	$-0x4,%R8

  (4036) 0x4d41ae MOV	-0xb0(%RBP),%R10

  (4036) 0x4d41b5 LEA	(%R10,%R9,8),%R13

  (4036) 0x4d41b9 XOR	%R10D,%R10D

  (4036) 0x4d41bc JMP	4d41d0

0x4d41be XCHG	%AX,%AX

    (4037) 0x4d41c0 LEA	0x1(%R10),%R9

    (4037) 0x4d41c4 CMP	%R14,%R10

    (4037) 0x4d41c7 MOV	%R9,%R10

    (4037) 0x4d41ca JE	4d4100

    (4037) 0x4d41d0 MOV	(%RBX,%R10,8),%R11

    (4037) 0x4d41d4 CMP	$0x4,%RDX

    (4037) 0x4d41d8 JAE	4d4210

    (4037) 0x4d41da CMP	%RDX,%R8

    (4037) 0x4d41dd JAE	4d41c0

    (4037) 0x4d41df MOV	%R8,%R9

    (4037) 0x4d41e2 JMP	4d41f8

0x4d41e4 NOPW	%CS:(%RAX,%RAX,1)

      (4038) 0x4d41f0 INC	%R9

      (4038) 0x4d41f3 CMP	%R9,%RDX

      (4038) 0x4d41f6 JE	4d41c0

      (4038) 0x4d41f8 CMP	%R11,(%RSI,%R9,8)

      (4038) 0x4d41fc JNE	4d41f0

      (4038) 0x4d41fe MOVQ	$-0x1,(%RSI,%R9,8)

      (4038) 0x4d4206 INCQ	(%R15)

      (4038) 0x4d4209 JMP	4d41f0

0x4d420b NOPL	(%RAX,%RAX,1)

    (4037) 0x4d4210 MOV	%RDI,%R12

    (4037) 0x4d4213 MOV	%R13,%R9

    (4037) 0x4d4216 JMP	4d4229

0x4d4218 NOPL	(%RAX,%RAX,1)

      (4039) 0x4d4220 ADD	$0x20,%R9

      (4039) 0x4d4224 DEC	%R12

      (4039) 0x4d4227 JE	4d41da

      (4039) 0x4d4229 CMP	%R11,-0x18(%R9)

      (4039) 0x4d422d JNE	4d4260

      (4039) 0x4d422f MOVQ	$-0x1,-0x18(%R9)

      (4039) 0x4d4237 INCQ	(%R15)

      (4039) 0x4d423a CMP	%R11,-0x10(%R9)

      (4039) 0x4d423e JE	4d4266

      (4039) 0x4d4240 CMP	%R11,-0x8(%R9)

      (4039) 0x4d4244 JNE	4d4277

      (4039) 0x4d4246 MOVQ	$-0x1,-0x8(%R9)

      (4039) 0x4d424e INCQ	(%R15)

      (4039) 0x4d4251 CMP	%R11,(%R9)

      (4039) 0x4d4254 JNE	4d4220

      (4039) 0x4d4256 JMP	4d427c

0x4d4258 NOPL	(%RAX,%RAX,1)

      (4039) 0x4d4260 CMP	%R11,-0x10(%R9)

      (4039) 0x4d4264 JNE	4d4240

      (4039) 0x4d4266 MOVQ	$-0x1,-0x10(%R9)

      (4039) 0x4d426e INCQ	(%R15)

      (4039) 0x4d4271 CMP	%R11,-0x8(%R9)

      (4039) 0x4d4275 JE	4d4246

      (4039) 0x4d4277 CMP	%R11,(%R9)

      (4039) 0x4d427a JNE	4d4220

      (4039) 0x4d427c MOVQ	$-0x1,(%R9)

      (4039) 0x4d4283 INCQ	(%R15)

      (4039) 0x4d4286 JMP	4d4220

(4035) 0x4d4288 MOV	0x18(%RBP),%RCX

(4035) 0x4d428c MOV	0x38(%RCX),%RAX

(4035) 0x4d4290 MOV	0x40(%RCX),%RCX

(4035) 0x4d4294 MOV	(%RCX,%R13,8),%R11

(4035) 0x4d4298 MOV	(%RAX,%R13,8),%R10

(4035) 0x4d429c TEST	%R14,%R14

(4035) 0x4d429f JLE	4d4948

(4035) 0x4d42a5 MOV	%R9,-0x68(%RBP)

(4035) 0x4d42a9 MOV	0x60(%RBP),%RAX

(4035) 0x4d42ad MOV	0x8(%RAX,%R13,8),%RAX

(4035) 0x4d42b2 MOV	%RAX,-0x78(%RBP)

(4035) 0x4d42b6 MOV	0x78(%RBP),%RAX

(4035) 0x4d42ba MOV	0x8(%RAX,%R13,8),%RAX

(4035) 0x4d42bf MOV	%RAX,-0x98(%RBP)

(4035) 0x4d42c6 MOV	-0x30(%RBP),%RDI

(4035) 0x4d42ca LEA	(%RDI,%R14,1),%RAX

(4035) 0x4d42ce MOV	%RAX,-0xa0(%RBP)

(4035) 0x4d42d5 XOR	%R8D,%R8D

(4035) 0x4d42d8 MOV	%R11,-0x80(%RBP)

(4035) 0x4d42dc MOV	%R10,-0x90(%RBP)

(4035) 0x4d42e3 MOV	%R10,-0x70(%RBP)

(4035) 0x4d42e7 MOV	%R11,%RCX

(4035) 0x4d42ea JMP	4d4306

0x4d42ec NOPL	(%RAX)

  (4042) 0x4d42f0 MOV	-0x38(%RBP),%R13

  (4042) 0x4d42f4 MOV	%RCX,%R11

  (4042) 0x4d42f7 INC	%RDI

  (4042) 0x4d42fa INC	%R8

  (4042) 0x4d42fd CMP	%R14,%R8

  (4042) 0x4d4300 JE	4d4950

  (4042) 0x4d4306 MOV	(%RBX,%RDI,8),%R9

  (4042) 0x4d430a CMP	0x28(%RBP),%R9

  (4042) 0x4d430e JL	4d4460

  (4042) 0x4d4314 CMP	0x30(%RBP),%R9

  (4042) 0x4d4318 JG	4d4460

  (4042) 0x4d431e MOV	0x60(%RBP),%RAX

  (4042) 0x4d4322 MOV	(%RAX,%R13,8),%R10

  (4042) 0x4d4326 MOV	-0x90(%RBP),%R11

  (4042) 0x4d432d SUB	%R10,%R11

  (4042) 0x4d4330 JLE	4d4420

  (4042) 0x4d4336 MOV	0x68(%RBP),%RAX

  (4042) 0x4d433a LEA	(%RAX,%R10,8),%EAX

  (4042) 0x4d433e AND	$0x7f,%EAX

  (4042) 0x4d4341 MOV	$0x80,%EDX

  (4042) 0x4d4346 SUB	%EAX,%EDX

  (4042) 0x4d4348 SHR	$0x3,%EDX

  (4042) 0x4d434b CMP	%RDX,%R11

  (4042) 0x4d434e MOV	%RDX,%RSI

  (4042) 0x4d4351 CMOVB	%R11,%RSI

  (4042) 0x4d4355 TEST	%RSI,%RSI

  (4042) 0x4d4358 JE	4d4377

  (4042) 0x4d435a MOV	%R10,%R12

  (4042) 0x4d435d MOV	%RSI,%RAX

    (4048) 0x4d4360 MOV	0x68(%RBP),%R13

    (4048) 0x4d4364 CMP	%R9,(%R13,%R12,8)

    (4048) 0x4d4369 JE	4d45c7

    (4048) 0x4d436f INC	%R12

    (4048) 0x4d4372 DEC	%RAX

    (4048) 0x4d4375 JNE	4d4360

  (4042) 0x4d4377 CMP	%RDX,%R11

  (4042) 0x4d437a JBE	4d4420

  (4042) 0x4d4380 MOV	%RDI,-0x30(%RBP)

  (4042) 0x4d4384 SUB	%RSI,%R11

  (4042) 0x4d4387 MOV	%R11,%R13

  (4042) 0x4d438a AND	$-0x10,%R13

  (4042) 0x4d438e JE	4d43ea

  (4042) 0x4d4390 LEA	-0x1(%R13),%RDI

  (4042) 0x4d4394 LEA	(%R10,%RSI,1),%R12

  (4042) 0x4d4398 VPBROADCASTQ	%R9,%YMM0

  (4042) 0x4d439e MOV	0x68(%RBP),%RAX

  (4042) 0x4d43a2 LEA	(%RAX,%R12,8),%RAX

  (4042) 0x4d43a6 XOR	%EDX,%EDX

  (4042) 0x4d43a8 NOPL	(%RAX,%RAX,1)

    (4047) 0x4d43b0 VPCMPEQQ	0x20(%RAX,%RDX,8),%YMM0,%K0

    (4047) 0x4d43b8 VPCMPEQQ	(%RAX,%RDX,8),%YMM0,%K1

    (4047) 0x4d43bf VPCMPEQQ	0x60(%RAX,%RDX,8),%YMM0,%K2

    (4047) 0x4d43c7 VPCMPEQQ	0x40(%RAX,%RDX,8),%YMM0,%K3

    (4047) 0x4d43cf KORB	%K0,%K1,%K4

    (4047) 0x4d43d3 KORB	%K2,%K3,%K5

    (4047) 0x4d43d7 KORTESTB	%K5,%K4

    (4047) 0x4d43db JNE	4d459d

    (4047) 0x4d43e1 ADD	$0x10,%RDX

    (4047) 0x4d43e5 CMP	%RDI,%RDX

    (4047) 0x4d43e8 JBE	4d43b0

  (4042) 0x4d43ea CMP	%R11,%R13

  (4042) 0x4d43ed MOV	-0x30(%RBP),%RDI

  (4042) 0x4d43f1 JAE	4d4420

  (4042) 0x4d43f3 ADD	%RSI,%R10

  (4042) 0x4d43f6 ADD	%R13,%R10

  (4042) 0x4d43f9 MOV	%R10,%R12

  (4042) 0x4d43fc NOPL	(%RAX)

    (4046) 0x4d4400 MOV	0x68(%RBP),%RAX

    (4046) 0x4d4404 CMP	%R9,(%RAX,%R12,8)

    (4046) 0x4d4408 JE	4d45c7

    (4046) 0x4d440e INC	%R12

    (4046) 0x4d4411 CMP	%R12,-0x90(%RBP)

    (4046) 0x4d4418 JNE	4d4400

  (4042) 0x4d441a NOPW	(%RAX,%RAX,1)

  (4042) 0x4d4420 MOV	-0x70(%RBP),%RDX

  (4042) 0x4d4424 CMP	-0x78(%RBP),%RDX

  (4042) 0x4d4428 JGE	4d4992

  (4042) 0x4d442e MOV	0x68(%RBP),%RAX

  (4042) 0x4d4432 MOV	%R9,(%RAX,%RDX,8)

  (4042) 0x4d4436 MOV	0x10(%RBP),%RAX

  (4042) 0x4d443a VMOVQ	(%RAX,%RDI,8),%XMM0

  (4042) 0x4d443f MOV	0x70(%RBP),%RAX

  (4042) 0x4d4443 VMOVQ	%XMM0,(%RAX,%RDX,8)

  (4042) 0x4d4448 INC	%RDX

  (4042) 0x4d444b MOV	%RDX,-0x70(%RBP)

  (4042) 0x4d444f JMP	4d42f0

0x4d4454 NOPW	%CS:(%RAX,%RAX,1)

  (4042) 0x4d4460 MOV	0x78(%RBP),%RAX

  (4042) 0x4d4464 MOV	(%RAX,%R13,8),%R10

  (4042) 0x4d4468 SUB	%R10,%R11

  (4042) 0x4d446b JLE	4d4560

  (4042) 0x4d4471 MOV	0x80(%RBP),%RAX

  (4042) 0x4d4478 LEA	(%RAX,%R10,8),%EAX

  (4042) 0x4d447c AND	$0x7f,%EAX

  (4042) 0x4d447f MOV	$0x80,%EDX

  (4042) 0x4d4484 SUB	%EAX,%EDX

  (4042) 0x4d4486 SHR	$0x3,%EDX

  (4042) 0x4d4489 CMP	%RDX,%R11

  (4042) 0x4d448c MOV	%RDX,%RSI

  (4042) 0x4d448f CMOVB	%R11,%RSI

  (4042) 0x4d4493 TEST	%RSI,%RSI

  (4042) 0x4d4496 JE	4d44ba

  (4042) 0x4d4498 MOV	%R10,%R12

  (4042) 0x4d449b MOV	%RSI,%RAX

  (4042) 0x4d449e XCHG	%AX,%AX

    (4045) 0x4d44a0 MOV	0x80(%RBP),%R13

    (4045) 0x4d44a7 CMP	%R9,(%R13,%R12,8)

    (4045) 0x4d44ac JE	4d4610

    (4045) 0x4d44b2 INC	%R12

    (4045) 0x4d44b5 DEC	%RAX

    (4045) 0x4d44b8 JNE	4d44a0

  (4042) 0x4d44ba CMP	%RDX,%R11

  (4042) 0x4d44bd JBE	4d4560

  (4042) 0x4d44c3 MOV	%RDI,-0x30(%RBP)

  (4042) 0x4d44c7 SUB	%RSI,%R11

  (4042) 0x4d44ca MOV	%R11,%R13

  (4042) 0x4d44cd AND	$-0x10,%R13

  (4042) 0x4d44d1 JE	4d452a

  (4042) 0x4d44d3 LEA	-0x1(%R13),%RDI

  (4042) 0x4d44d7 LEA	(%R10,%RSI,1),%R12

  (4042) 0x4d44db VPBROADCASTQ	%R9,%YMM0

  (4042) 0x4d44e1 MOV	0x80(%RBP),%RAX

  (4042) 0x4d44e8 LEA	(%RAX,%R12,8),%RAX

  (4042) 0x4d44ec XOR	%EDX,%EDX

  (4042) 0x4d44ee XCHG	%AX,%AX

    (4044) 0x4d44f0 VPCMPEQQ	0x20(%RAX,%RDX,8),%YMM0,%K0

    (4044) 0x4d44f8 VPCMPEQQ	(%RAX,%RDX,8),%YMM0,%K1

    (4044) 0x4d44ff VPCMPEQQ	0x60(%RAX,%RDX,8),%YMM0,%K2

    (4044) 0x4d4507 VPCMPEQQ	0x40(%RAX,%RDX,8),%YMM0,%K3

    (4044) 0x4d450f KORB	%K0,%K1,%K4

    (4044) 0x4d4513 KORB	%K2,%K3,%K5

    (4044) 0x4d4517 KORTESTB	%K5,%K4

    (4044) 0x4d451b JNE	4d45e6

    (4044) 0x4d4521 ADD	$0x10,%RDX

    (4044) 0x4d4525 CMP	%RDI,%RDX

    (4044) 0x4d4528 JBE	4d44f0

  (4042) 0x4d452a CMP	%R11,%R13

  (4042) 0x4d452d MOV	-0x30(%RBP),%RDI

  (4042) 0x4d4531 JAE	4d4560

  (4042) 0x4d4533 ADD	%RSI,%R10

  (4042) 0x4d4536 ADD	%R13,%R10

  (4042) 0x4d4539 MOV	%R10,%R12

  (4042) 0x4d453c NOPL	(%RAX)

    (4043) 0x4d4540 MOV	0x80(%RBP),%RAX

    (4043) 0x4d4547 CMP	%R9,(%RAX,%R12,8)

    (4043) 0x4d454b JE	4d4610

    (4043) 0x4d4551 INC	%R12

    (4043) 0x4d4554 CMP	%R12,%RCX

    (4043) 0x4d4557 JNE	4d4540

  (4042) 0x4d4559 NOPL	(%RAX)

  (4042) 0x4d4560 MOV	-0x80(%RBP),%RDX

  (4042) 0x4d4564 CMP	-0x98(%RBP),%RDX

  (4042) 0x4d456b JGE	4d49cf

  (4042) 0x4d4571 MOV	0x80(%RBP),%RAX

  (4042) 0x4d4578 MOV	%R9,(%RAX,%RDX,8)

  (4042) 0x4d457c MOV	0x10(%RBP),%RAX

  (4042) 0x4d4580 VMOVQ	(%RAX,%RDI,8),%XMM0

  (4042) 0x4d4585 MOV	0x88(%RBP),%RAX

  (4042) 0x4d458c VMOVQ	%XMM0,(%RAX,%RDX,8)

  (4042) 0x4d4591 INC	%RDX

  (4042) 0x4d4594 MOV	%RDX,-0x80(%RBP)

  (4042) 0x4d4598 JMP	4d42f0

  (4042) 0x4d459d KSHIFTLB	$0x4,%K0,%K0

  (4042) 0x4d45a3 KORB	%K0,%K1,%K0

  (4042) 0x4d45a7 KSHIFTLB	$0x4,%K2,%K1

  (4042) 0x4d45ad KORB	%K1,%K3,%K1

  (4042) 0x4d45b1 KUNPCKBW	%K0,%K1,%K0

  (4042) 0x4d45b5 KMOVD	%K0,%EAX

  (4042) 0x4d45b9 TZCNT	%EAX,%EAX

  (4042) 0x4d45bd ADD	%RDX,%R12

  (4042) 0x4d45c0 ADD	%RAX,%R12

  (4042) 0x4d45c3 MOV	-0x30(%RBP),%RDI

  (4042) 0x4d45c7 MOV	-0x38(%RBP),%R13

  (4042) 0x4d45cb MOV	%RCX,%R11

  (4042) 0x4d45ce MOV	0x10(%RBP),%RAX

  (4042) 0x4d45d2 VMOVQ	(%RAX,%RDI,8),%XMM0

  (4042) 0x4d45d7 MOV	0x70(%RBP),%RAX

  (4042) 0x4d45db VMOVQ	%XMM0,(%RAX,%R12,8)

  (4042) 0x4d45e1 JMP	4d42f7

  (4042) 0x4d45e6 KSHIFTLB	$0x4,%K0,%K0

  (4042) 0x4d45ec KORB	%K0,%K1,%K0

  (4042) 0x4d45f0 KSHIFTLB	$0x4,%K2,%K1

  (4042) 0x4d45f6 KORB	%K1,%K3,%K1

  (4042) 0x4d45fa KUNPCKBW	%K0,%K1,%K0

  (4042) 0x4d45fe KMOVD	%K0,%EAX

  (4042) 0x4d4602 TZCNT	%EAX,%EAX

  (4042) 0x4d4606 ADD	%RDX,%R12

  (4042) 0x4d4609 ADD	%RAX,%R12

  (4042) 0x4d460c MOV	-0x30(%RBP),%RDI

  (4042) 0x4d4610 MOV	-0x38(%RBP),%R13

  (4042) 0x4d4614 MOV	%RCX,%R11

  (4042) 0x4d4617 MOV	0x10(%RBP),%RAX

  (4042) 0x4d461b VMOVQ	(%RAX,%RDI,8),%XMM0

  (4042) 0x4d4620 MOV	0x88(%RBP),%RAX

  (4042) 0x4d4627 VMOVQ	%XMM0,(%RAX,%R12,8)

  (4042) 0x4d462d JMP	4d42f7

(4035) 0x4d4632 XOR	%EAX,%EAX

(4035) 0x4d4634 MOV	%RAX,-0x78(%RBP)

(4035) 0x4d4638 MOV	-0x30(%RBP),%RDI

(4035) 0x4d463c TEST	%R14,%R14

(4035) 0x4d463f JLE	4d40b0

(4035) 0x4d4645 LEA	-0x1(%R14),%RAX

(4035) 0x4d4649 MOV	%R12D,%EDX

(4035) 0x4d464c AND	$0x7f,%EDX

(4035) 0x4d464f MOV	$0x80,%ECX

(4035) 0x4d4654 SUB	%EDX,%ECX

(4035) 0x4d4656 SHR	$0x3,%ECX

(4035) 0x4d4659 CMP	%RCX,%R13

(4035) 0x4d465c MOV	%RCX,%RDX

(4035) 0x4d465f CMOVB	%R13,%RDX

(4035) 0x4d4663 MOV	%R13,%RSI

(4035) 0x4d4666 SUB	%RDX,%RSI

(4035) 0x4d4669 MOV	%RSI,-0xa0(%RBP)

(4035) 0x4d4670 AND	$-0x10,%RSI

(4035) 0x4d4674 LEA	-0x1(%RSI),%R8

(4035) 0x4d4678 LEA	(%R12,%RDX,8),%R9

(4035) 0x4d467c MOV	%RSI,-0x98(%RBP)

(4035) 0x4d4683 ADD	%RDX,%RSI

(4035) 0x4d4686 MOV	%RSI,-0xa8(%RBP)

(4035) 0x4d468d XOR	%ESI,%ESI

(4035) 0x4d468f MOV	%RSI,-0x90(%RBP)

(4035) 0x4d4696 MOV	%R13,-0x58(%RBP)

(4035) 0x4d469a XOR	%R11D,%R11D

(4035) 0x4d469d JMP	4d46da

0x4d469f NOP

  (4052) 0x4d46a0 MOV	-0x78(%RBP),%RDI

  (4052) 0x4d46a4 MOV	-0x90(%RBP),%R10

  (4052) 0x4d46ab MOV	%RSI,(%RDI,%R10,8)

  (4052) 0x4d46af MOV	-0x88(%RBP),%RSI

  (4052) 0x4d46b6 VMOVQ	%XMM0,(%RSI,%R10,8)

  (4052) 0x4d46bc INC	%R10

  (4052) 0x4d46bf MOV	%R10,-0x90(%RBP)

  (4052) 0x4d46c6 MOV	-0x30(%RBP),%RDI

  (4052) 0x4d46ca LEA	0x1(%R11),%RSI

  (4052) 0x4d46ce CMP	%RAX,%R11

  (4052) 0x4d46d1 MOV	%RSI,%R11

  (4052) 0x4d46d4 JE	4d4803

  (4052) 0x4d46da LEA	(%RDI,%R11,1),%R10

  (4052) 0x4d46de TEST	%R13,%R13

  (4052) 0x4d46e1 JLE	4d4790

  (4052) 0x4d46e7 MOV	(%RBX,%R10,8),%RDI

  (4052) 0x4d46eb TEST	%RDX,%RDX

  (4052) 0x4d46ee JE	4d4712

  (4052) 0x4d46f0 XOR	%ESI,%ESI

  (4052) 0x4d46f2 NOPW	%CS:(%RAX,%RAX,1)

    (4055) 0x4d4700 CMP	%RDI,(%R12,%RSI,8)

    (4055) 0x4d4704 JE	4d47eb

    (4055) 0x4d470a INC	%RSI

    (4055) 0x4d470d CMP	%RSI,%RDX

    (4055) 0x4d4710 JNE	4d4700

  (4052) 0x4d4712 CMP	%RCX,%R13

  (4052) 0x4d4715 JBE	4d4790

  (4052) 0x4d4717 CMPQ	$0,-0x98(%RBP)

  (4052) 0x4d471f JE	4d4766

  (4052) 0x4d4721 VPBROADCASTQ	%RDI,%YMM0

  (4052) 0x4d4727 XOR	%ESI,%ESI

  (4052) 0x4d4729 NOPL	(%RAX)

    (4054) 0x4d4730 VPCMPEQQ	0x20(%R9,%RSI,8),%YMM0,%K0

    (4054) 0x4d4738 VPCMPEQQ	(%R9,%RSI,8),%YMM0,%K1

    (4054) 0x4d473f VPCMPEQQ	0x60(%R9,%RSI,8),%YMM0,%K2

    (4054) 0x4d4747 VPCMPEQQ	0x40(%R9,%RSI,8),%YMM0,%K3

    (4054) 0x4d474f KORB	%K0,%K1,%K4

    (4054) 0x4d4753 KORB	%K2,%K3,%K5

    (4054) 0x4d4757 KORTESTB	%K5,%K4

    (4054) 0x4d475b JNE	4d47c5

    (4054) 0x4d475d ADD	$0x10,%RSI

    (4054) 0x4d4761 CMP	%R8,%RSI

    (4054) 0x4d4764 JBE	4d4730

  (4052) 0x4d4766 MOV	-0x98(%RBP),%RSI

  (4052) 0x4d476d CMP	-0xa0(%RBP),%RSI

  (4052) 0x4d4774 JAE	4d4790

  (4052) 0x4d4776 MOV	-0xa8(%RBP),%RSI

  (4052) 0x4d477d NOPL	(%RAX)

    (4053) 0x4d4780 CMP	%RDI,(%R12,%RSI,8)

    (4053) 0x4d4784 JE	4d47eb

    (4053) 0x4d4786 INC	%RSI

    (4053) 0x4d4789 CMP	%RSI,%R13

    (4053) 0x4d478c JNE	4d4780

  (4052) 0x4d478e XCHG	%AX,%AX

  (4052) 0x4d4790 MOV	(%RBX,%R10,8),%RSI

  (4052) 0x4d4794 MOV	0x10(%RBP),%RDI

  (4052) 0x4d4798 VMOVQ	(%RDI,%R10,8),%XMM0

  (4052) 0x4d479e MOV	-0x58(%RBP),%RDI

  (4052) 0x4d47a2 CMP	-0x80(%RBP),%RDI

  (4052) 0x4d47a6 JGE	4d46a0

  (4052) 0x4d47ac MOV	%RSI,(%R12,%RDI,8)

  (4052) 0x4d47b0 MOV	-0x70(%RBP),%RSI

  (4052) 0x4d47b4 VMOVQ	%XMM0,(%RSI,%RDI,8)

  (4052) 0x4d47b9 INC	%RDI

  (4052) 0x4d47bc MOV	%RDI,-0x58(%RBP)

  (4052) 0x4d47c0 JMP	4d46c6

  (4052) 0x4d47c5 KSHIFTLB	$0x4,%K0,%K0

  (4052) 0x4d47cb KORB	%K0,%K1,%K0

  (4052) 0x4d47cf KSHIFTLB	$0x4,%K2,%K1

  (4052) 0x4d47d5 KORB	%K1,%K3,%K1

  (4052) 0x4d47d9 KUNPCKBW	%K0,%K1,%K0

  (4052) 0x4d47dd KMOVD	%K0,%EDI

  (4052) 0x4d47e1 TZCNT	%EDI,%EDI

  (4052) 0x4d47e5 ADD	%RDX,%RSI

  (4052) 0x4d47e8 ADD	%RDI,%RSI

  (4052) 0x4d47eb MOV	0x10(%RBP),%RDI

  (4052) 0x4d47ef VMOVQ	(%RDI,%R10,8),%XMM0

  (4052) 0x4d47f5 MOV	-0x70(%RBP),%RDI

  (4052) 0x4d47f9 VMOVQ	%XMM0,(%RDI,%RSI,8)

  (4052) 0x4d47fe JMP	4d46c6

(4035) 0x4d4803 ADD	%R14,%RDI

(4035) 0x4d4806 MOV	-0x90(%RBP),%RCX

(4035) 0x4d480d MOV	-0x58(%RBP),%RAX

(4035) 0x4d4811 LEA	(%RAX,%RCX,1),%R12

(4035) 0x4d4815 MOV	0x48(%RBP),%RAX

(4035) 0x4d4819 MOV	-0x38(%RBP),%R13

(4035) 0x4d481d MOV	%R12,(%RAX,%R13,8)

(4035) 0x4d4821 TEST	%RCX,%RCX

(4035) 0x4d4824 MOV	%RDI,-0x30(%RBP)

(4035) 0x4d4828 JE	4d4936

(4035) 0x4d482e MOV	0x38(%RBP),%RAX

(4035) 0x4d4832 MOV	(%RAX,%R13,8),%RDI

(4035) 0x4d4836 LEA	(,%R12,8),%R14

(4035) 0x4d483e MOV	%R14,%RSI

(4035) 0x4d4841 VZEROUPPER

(4035) 0x4d4844 CALL	4e7320 <hypre_ReAlloc>

(4035) 0x4d4849 MOV	0x38(%RBP),%RCX

(4035) 0x4d484d MOV	%RAX,(%RCX,%R13,8)

(4035) 0x4d4851 MOV	0x40(%RBP),%R13

(4035) 0x4d4855 MOV	-0x38(%RBP),%RAX

(4035) 0x4d4859 MOV	(%R13,%RAX,8),%RDI

(4035) 0x4d485e MOV	%R14,%RSI

(4035) 0x4d4861 CALL	4e7320 <hypre_ReAlloc>

(4035) 0x4d4866 MOV	-0x90(%RBP),%RDX

(4035) 0x4d486d MOV	-0x38(%RBP),%RCX

(4035) 0x4d4871 MOV	%RAX,(%R13,%RCX,8)

(4035) 0x4d4876 MOV	-0x38(%RBP),%RSI

(4035) 0x4d487a MOV	0x50(%RBP),%RCX

(4035) 0x4d487e MOV	%R12,(%RCX,%RSI,8)

(4035) 0x4d4882 TEST	%RDX,%RDX

(4035) 0x4d4885 JLE	4d4936

(4035) 0x4d488b MOV	0x38(%RBP),%RCX

(4035) 0x4d488f MOV	(%RCX,%RSI,8),%RCX

(4035) 0x4d4893 MOV	-0x78(%RBP),%R13

(4035) 0x4d4897 LEA	-0x8(%R13,%RDX,8),%RSI

(4035) 0x4d489c MOV	-0x58(%RBP),%R10

(4035) 0x4d48a0 LEA	(%RCX,%R10,8),%RDI

(4035) 0x4d48a4 CMP	%RDI,%RSI

(4035) 0x4d48a7 SETAE	%R9B

(4035) 0x4d48ab LEA	-0x1(%RDX,%R10,1),%RSI

(4035) 0x4d48b0 LEA	(%RCX,%RSI,8),%RCX

(4035) 0x4d48b4 CMP	%R13,%RCX

(4035) 0x4d48b7 SETAE	%R8B

(4035) 0x4d48bb MOV	-0x88(%RBP),%R12

(4035) 0x4d48c2 LEA	-0x8(%R12,%RDX,8),%RCX

(4035) 0x4d48c7 LEA	(%RAX,%R10,8),%R14

(4035) 0x4d48cb CMP	%R14,%RCX

(4035) 0x4d48ce SETB	%CL

(4035) 0x4d48d1 LEA	(%RAX,%RSI,8),%RAX

(4035) 0x4d48d5 CMP	%R12,%RAX

(4035) 0x4d48d8 SETB	%AL

(4035) 0x4d48db TEST	%R8B,%R9B

(4035) 0x4d48de JNE	4d4960

(4035) 0x4d48e4 OR	%AL,%CL

(4035) 0x4d48e6 JE	4d4960

(4035) 0x4d48e8 CMP	$0xd,%RDX

(4035) 0x4d48ec JAE	4d3fa1

(4035) 0x4d48f2 MOV	%RDX,%RAX

(4035) 0x4d48f5 AND	$-0x4,%RAX

(4035) 0x4d48f9 JE	4d4a46

(4035) 0x4d48ff LEA	-0x1(%RAX),%RCX

(4035) 0x4d4903 XOR	%ESI,%ESI

(4035) 0x4d4905 NOPW	%CS:(%RAX,%RAX,1)

  (4051) 0x4d4910 VMOVUPS	(%R13,%RSI,8),%YMM0

  (4051) 0x4d4917 VMOVUPS	%YMM0,(%RDI,%RSI,8)

  (4051) 0x4d491c VMOVDQU	(%R12,%RSI,8),%YMM0

  (4051) 0x4d4922 VMOVDQU	%YMM0,(%R14,%RSI,8)

  (4051) 0x4d4928 ADD	$0x4,%RSI

  (4051) 0x4d492c CMP	%RCX,%RSI

  (4051) 0x4d492f JLE	4d4910

(4035) 0x4d4931 JMP	4d4a50

(4035) 0x4d4936 MOV	-0x78(%RBP),%R13

(4035) 0x4d493a TEST	%R13,%R13

(4035) 0x4d493d JNE	4d3fc9

(4035) 0x4d4943 JMP	4d3fe9

(4035) 0x4d4948 MOV	%R11,%RDI

(4035) 0x4d494b JMP	4d4a2d

(4035) 0x4d4950 MOV	-0xa0(%RBP),%RAX

(4035) 0x4d4957 MOV	%RAX,-0x30(%RBP)

(4035) 0x4d495b JMP	4d4a15

(4035) 0x4d4960 XOR	%EAX,%EAX

(4035) 0x4d4962 NOPW	%CS:(%RAX,%RAX,1)

  (4049) 0x4d4970 MOV	(%R13,%RAX,8),%RCX

  (4049) 0x4d4975 MOV	%RCX,(%RDI,%RAX,8)

  (4049) 0x4d4979 VMOVQ	(%R12,%RAX,8),%XMM0

  (4049) 0x4d497f VMOVQ	%XMM0,(%R14,%RAX,8)

  (4049) 0x4d4985 INC	%RAX

  (4049) 0x4d4988 CMP	%RAX,%RDX

  (4049) 0x4d498b JNE	4d4970

(4035) 0x4d498d JMP	4d3fc9

(4035) 0x4d4992 MOV	%RDI,-0x30(%RBP)

(4035) 0x4d4996 MOV	$0x510def,%EDI

(4035) 0x4d499b MOV	$0xd70,%ESI

(4035) 0x4d49a0 MOV	$0x1,%EDX

(4035) 0x4d49a5 XOR	%ECX,%ECX

(4035) 0x4d49a7 VZEROUPPER

(4035) 0x4d49aa CALL	4e9c60 <hypre_error_handler>

(4035) 0x4d49af MOV	0xd0(%RBP),%RAX

(4035) 0x4d49b6 LOCK INCQ	(%RAX)

(4035) 0x4d49ba MOV	$0x510f68,%EDI

(4035) 0x4d49bf CMPQ	$0,0xc0(%RBP)

(4035) 0x4d49c7 MOV	-0x38(%RBP),%R13

(4035) 0x4d49cb JNE	4d4a0a

(4035) 0x4d49cd JMP	4d4a15

(4035) 0x4d49cf MOV	%RDI,-0x30(%RBP)

(4035) 0x4d49d3 MOV	$0x510def,%EDI

(4035) 0x4d49d8 MOV	$0xd4e,%ESI

(4035) 0x4d49dd MOV	$0x1,%EDX

(4035) 0x4d49e2 XOR	%ECX,%ECX

(4035) 0x4d49e4 VZEROUPPER

(4035) 0x4d49e7 CALL	4e9c60 <hypre_error_handler>

(4035) 0x4d49ec MOV	0xd0(%RBP),%RAX

(4035) 0x4d49f3 LOCK INCQ	(%RAX)

(4035) 0x4d49f7 MOV	$0x510f42,%EDI

(4035) 0x4d49fc CMPQ	$0,0xc0(%RBP)

(4035) 0x4d4a04 MOV	-0x38(%RBP),%R13

(4035) 0x4d4a08 JE	4d4a15

(4035) 0x4d4a0a MOV	-0x58(%RBP),%RSI

(4035) 0x4d4a0e XOR	%EAX,%EAX

(4035) 0x4d4a10 CALL	4e7470 <hypre_printf>

(4035) 0x4d4a15 MOV	-0x60(%RBP),%RDX

(4035) 0x4d4a19 MOV	-0x48(%RBP),%RSI

(4035) 0x4d4a1d MOV	-0x68(%RBP),%R9

(4035) 0x4d4a21 MOV	-0x50(%RBP),%R8

(4035) 0x4d4a25 MOV	-0x80(%RBP),%RDI

(4035) 0x4d4a29 MOV	-0x70(%RBP),%R10

(4035) 0x4d4a2d MOV	0x18(%RBP),%RCX

(4035) 0x4d4a31 MOV	0x38(%RCX),%RAX

(4035) 0x4d4a35 MOV	%R10,(%RAX,%R13,8)

(4035) 0x4d4a39 MOV	0x40(%RCX),%RAX

(4035) 0x4d4a3d MOV	%RDI,(%RAX,%R13,8)

(4035) 0x4d4a41 JMP	4d3ff9

(4035) 0x4d4a46 XOR	%EAX,%EAX

(4035) 0x4d4a48 JMP	4d4a59

0x4d4a4a NOPW	(%RAX,%RAX,1)

  (4050) 0x4d4a50 CMP	%RAX,%RDX

  (4050) 0x4d4a53 JE	4d3fc9

  (4050) 0x4d4a59 MOV	(%R13,%RAX,8),%RCX

  (4050) 0x4d4a5e MOV	%RCX,(%RDI,%RAX,8)

  (4050) 0x4d4a62 VMOVQ	(%R12,%RAX,8),%XMM0

  (4050) 0x4d4a68 VMOVQ	%XMM0,(%R14,%RAX,8)

  (4050) 0x4d4a6e INC	%RAX

  (4050) 0x4d4a71 JMP	4d4a50

0x4d4a73 ADD	$0x98,%RSP

0x4d4a7a POP	%RBX

0x4d4a7b POP	%R12

0x4d4a7d POP	%R13

0x4d4a7f POP	%R14

0x4d4a81 POP	%R15

0x4d4a83 POP	%RBP

0x4d4a84 VZEROUPPER

0x4d4a87 RET

0x4d4a88 NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	IJMatrix_parcsr.c:3240-3484
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3240,3256-3283,3289-3322,3329-3337,3344-3353,3359-3368,3376-3392,3399-3410,3422-3426,3433-3445,3454-3458,3466-3484.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 29.50 to 6.00 cycles (4.92x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

14% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
18% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_barrier@plt: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3275
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3282
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3257
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3256

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3259
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3259
VZEROUPPER: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3275
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3359

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3259

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 160 bytes. The binary function is storing 73 bytes.

General properties

nb instructions	164
nb uops	177
loop length	659
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	0
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	29.50 cycles
front end	29.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	12.20	12.20	9.33	9.33	10.00	12.20	12.20	10.00	10.00	10.00	12.20	9.33
cycles	12.20	16.20	9.33	9.33	10.00	12.20	12.20	10.00	10.00	10.00	12.20	9.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

16.00

Cycles summary

Front-end	29.50
Dispatch	16.20
DIV/SQRT	16.00
Overall L1	29.50

Vectorization ratios

all	14%
load	0%
store	0%
mul	0%
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	18%

Vector efficiency ratios

all	13%
load	10%
store	11%
mul	12%
add-sub	20%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	9%
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 29.50 cycles. At this rate:

2% of peak load performance is reached (5.42 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.47 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 29.50 to 16.20 cycles (1.82x speedup).

ASM code

In the binary file, the address of the function is: 4d3d20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x98,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 4e8fe0 <hypre_NumActiveThreads>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4e8ff0 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR %R15,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x20,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JE 4d3d6b <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x4b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %R13	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
JMP 4d3d73 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x53>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %R12,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xb8(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%R14),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RDX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4d3d97 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x77>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%RAX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R14,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %RCX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JMP 4d3dab <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x8b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %RAX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R14,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOVQ $0,(%R15,%R14,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RSI,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RSI,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 4d3e60 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x140>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %RDX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVL %R14,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IMUL %R14,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x50(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RDX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4d3e36 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x116>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RCX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x48(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R8,%R9,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VEXTRACTI128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VPSHUFD $-0x12,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVQ %XMM0,%RSI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
CMP %RCX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x48(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 4d3e42 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x122>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 4d3e5c <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x13c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV -0x48(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,(%R15,%R14,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%R13),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x536530,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 410560 <__kmpc_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %R14,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 4d3f14 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x1f4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0xc8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 4d3f14 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x1f4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 4d3ee7 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x1c7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV (%R15),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x40(%R15),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 4d3f14 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x1f4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R15,%RCX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R13),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x536550,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 410560 <__kmpc_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %R14,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 4d3f2e <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x20e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x8(%R15,%R14,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 4d3f30 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x210>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x60(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x48(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R12,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x50(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R8,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4d4a73 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0xd53>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xa8(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x98(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
SETE %CL	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
LEA (%RAX,%R14,8),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %R10,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
SETLE %AL	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
OR %CL,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %AL,-0x39(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	N/A
DEC %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x1,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %R10,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x18(%RDI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 4d4009 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x2e9>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x98,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	IJMatrix_parcsr.c:3240-3484
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 29.50 to 6.00 cycles (4.92x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

14% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
18% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

__kmpc_barrier@plt: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3275
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3282
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3257
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3256

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3259
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3259
VZEROUPPER: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3275
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3359

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3259

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 160 bytes. The binary function is storing 73 bytes.

General properties

nb instructions	164
nb uops	177
loop length	659
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	0
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	29.50 cycles
front end	29.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	12.20	12.20	9.33	9.33	10.00	12.20	12.20	10.00	10.00	10.00	12.20	9.33
cycles	12.20	16.20	9.33	9.33	10.00	12.20	12.20	10.00	10.00	10.00	12.20	9.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

16.00

Cycles summary

Front-end	29.50
Dispatch	16.20
DIV/SQRT	16.00
Overall L1	29.50

Vectorization ratios

all	14%
load	0%
store	0%
mul	0%
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	18%

Vector efficiency ratios

all	13%
load	10%
store	11%
mul	12%
add-sub	20%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	9%
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 29.50 cycles. At this rate:

2% of peak load performance is reached (5.42 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.47 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4d3d20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x98,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 4e8fe0 <hypre_NumActiveThreads>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4e8ff0 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR %R15,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x20,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JE 4d3d6b <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x4b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %R13	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
JMP 4d3d73 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x53>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %R12,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xb8(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%R14),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RDX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4d3d97 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x77>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%RAX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R14,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %RCX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JMP 4d3dab <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x8b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %RAX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R14,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOVQ $0,(%R15,%R14,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RSI,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RSI,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 4d3e60 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x140>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %RDX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVL %R14,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IMUL %R14,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x50(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RDX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4d3e36 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x116>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RCX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x48(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R8,%R9,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VEXTRACTI128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VPSHUFD $-0x12,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVQ %XMM0,%RSI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
CMP %RCX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x48(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 4d3e42 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x122>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 4d3e5c <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x13c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV -0x48(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,(%R15,%R14,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%R13),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x536530,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 410560 <__kmpc_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %R14,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 4d3f14 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x1f4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0xc8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 4d3f14 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x1f4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 4d3ee7 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x1c7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV (%R15),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x40(%R15),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 4d3f14 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x1f4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R15,%RCX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R13),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x536550,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 410560 <__kmpc_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %R14,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 4d3f2e <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x20e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x8(%R15,%R14,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 4d3f30 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x210>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x60(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x48(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R12,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x50(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R8,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4d4a73 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0xd53>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xa8(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x98(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
SETE %CL	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
LEA (%RAX,%R14,8),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %R10,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
SETLE %AL	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
OR %CL,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %AL,-0x39(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	N/A
DEC %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x1,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %R10,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x18(%RDI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 4d4009 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x2e9>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x98,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼hypre_IJMatrixSetValuesOMPParCSR.extracted.28–	1.16	0.62
▼Loop 4035 - IJMatrix_parcsr.c:3262-3484 - exec–	0.08	0.04
▼Loop 4042 - IJMatrix_parcsr.c:3262-3454 - exec–	1.07	0.46
○Loop 4043 - IJMatrix_parcsr.c:3388-3390 - exec	0.00	0.00
○Loop 4047 - IJMatrix_parcsr.c:3422-3424 - exec	0.00	0.00
○Loop 4044 - IJMatrix_parcsr.c:3388-3424 - exec	0.00	0.00
○Loop 4048 - IJMatrix_parcsr.c:3422-3424 - exec	0.00	0.00
○Loop 4046 - IJMatrix_parcsr.c:3422-3424 - exec	0.00	0.00
○Loop 4045 - IJMatrix_parcsr.c:3388-3390 - exec	0.00	0.00
▼Loop 4036 - IJMatrix_parcsr.c:3262-3484 - exec–	0.00	0.00
▼Loop 4037 - IJMatrix_parcsr.c:3473-3484 - exec–	0.00	0.00
○Loop 4039 - IJMatrix_parcsr.c:3478-3484 - exec	0.00	0.00
○Loop 4038 - IJMatrix_parcsr.c:3478-3484 - exec	0.00	0.00
▼Loop 4040 - IJMatrix_parcsr.c:3475-3484 - exec–	0.00	0.00
○Loop 4041 - IJMatrix_parcsr.c:3478-3484 - exec	0.00	0.00
○Loop 4049 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
○Loop 4050 - IJMatrix_parcsr.c:3359-3458 - exec	0.00	0.00
▼Loop 4052 - IJMatrix_parcsr.c:3262-3337 - exec–	0.00	0.00
○Loop 4053 - IJMatrix_parcsr.c:3318-3320 - exec	0.00	0.00
○Loop 4054 - IJMatrix_parcsr.c:3318-3320 - exec	0.00	0.00
○Loop 4055 - IJMatrix_parcsr.c:3318-3320 - exec	0.00	0.00
○Loop 4051 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
○Loop 4059 - IJMatrix_parcsr.c:3274-3275 - exec	0.01	0.00
○Loop 4056 - IJMatrix_parcsr.c:3282-3283 - exec	0.00	0.00
○Loop 4057 - IJMatrix_parcsr.c:3282-3283 - exec	0.00	0.00
○Loop 4058 - IJMatrix_parcsr.c:3274-3275 - exec	0.00	0.00

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512-bits vectorization

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

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ASM code