OV - exec - Function hypre_IJMatrixAssembleParCSR.extracted.25

	Function: hypre_IJMatrixAssembleParCSR.extracted.25	Module: exec	Source: IJMatrix_parcsr.c:2798-2812	Coverage (incl. loops): 0.60% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 2798 - 2812

--------------------------------------------------------------------------------

2798: #pragma omp parallel for private (i,j,j0,temp)

2799: #endif

2800:          for (i=0; i < num_rows; i++)

2801:          {

2802:    	    j0 = diag_i[i];

2803:    	    for (j=j0; j < diag_i[i+1]; j++)

2804:    	    {

2805:    	       diag_j[j] -= col_0;

2806:    	       if (diag_j[j] == i)

2807:    	       {

2808:    	          temp = diag_data[j0];

2809:    	          diag_data[j0] = diag_data[j];

2810:    	          diag_data[j] = temp;

2811:    	          diag_j[j] = diag_j[j0];

2812:    	          diag_j[j0] = i;

0x4d2f70 PUSH	%RBP

0x4d2f71 MOV	%RSP,%RBP

0x4d2f74 PUSH	%R15

0x4d2f76 PUSH	%R14

0x4d2f78 PUSH	%R13

0x4d2f7a PUSH	%R12

0x4d2f7c PUSH	%RBX

0x4d2f7d SUB	$0x18,%RSP

0x4d2f81 MOVL	$0,-0x2c(%RBP)

0x4d2f88 MOV	%R9,%R14

0x4d2f8b MOV	%R8,%R15

0x4d2f8e MOV	%RCX,%R12

0x4d2f91 MOV	%RDX,%R13

0x4d2f94 MOV	(%RDI),%EBX

0x4d2f96 MOVQ	$0,-0x38(%RBP)

0x4d2f9e MOVQ	$0x1,-0x40(%RBP)

0x4d2fa6 SUB	$0x8,%RSP

0x4d2faa LEA	-0x40(%RBP),%RAX

0x4d2fae LEA	-0x2c(%RBP),%RCX

0x4d2fb2 LEA	-0x38(%RBP),%R8

0x4d2fb6 LEA	0x18(%RBP),%R9

0x4d2fba MOV	$0x536770,%EDI

0x4d2fbf MOV	%EBX,%ESI

0x4d2fc1 MOV	$0x22,%EDX

0x4d2fc6 PUSH	$0x1

0x4d2fc8 PUSH	$0x1

0x4d2fca PUSH	%RAX

0x4d2fcb CALL	410420 <__kmpc_for_static_init_8@plt>

0x4d2fd0 ADD	$0x20,%RSP

0x4d2fd4 MOV	-0x38(%RBP),%RSI

0x4d2fd8 MOV	0x18(%RBP),%RAX

0x4d2fdc CMP	%RAX,%RSI

0x4d2fdf JA	4d3075

0x4d2fe5 MOV	(%R13,%RSI,8),%RDX

0x4d2fea MOV	%EAX,%ECX

0x4d2fec SUB	%ESI,%ECX

0x4d2fee INC	%ECX

0x4d2ff0 TEST	$0x1,%CL

0x4d2ff3 JNE	4d3003

0x4d2ff5 MOV	%RSI,%RCX

0x4d2ff8 CMP	%RSI,%RAX

0x4d2ffb JNE	4d3095

0x4d3001 JMP	4d3075

0x4d3003 LEA	0x1(%RSI),%RCX

0x4d3007 MOV	0x8(%R13,%RSI,8),%RDI

0x4d300c CMP	%RDI,%RDX

0x4d300f JGE	4d3063

0x4d3011 MOV	%RDX,%RDI

0x4d3014 JMP	4d302d

0x4d3016 NOPW	%CS:(%RAX,%RAX,1)

(4016) 0x4d3020 INC	%RDI

(4016) 0x4d3023 MOV	0x8(%R13,%RSI,8),%R8

(4016) 0x4d3028 CMP	%R8,%RDI

(4016) 0x4d302b JGE	4d306d

(4016) 0x4d302d MOV	(%R12,%RDI,8),%R8

(4016) 0x4d3031 SUB	%R14,%R8

(4016) 0x4d3034 MOV	%R8,(%R12,%RDI,8)

(4016) 0x4d3038 CMP	%RSI,%R8

(4016) 0x4d303b JNE	4d3020

(4016) 0x4d303d VMOVSD	(%R15,%RDX,8),%XMM0

(4016) 0x4d3043 VMOVSD	(%R15,%RDI,8),%XMM1

(4016) 0x4d3049 VMOVSD	%XMM1,(%R15,%RDX,8)

(4016) 0x4d304f VMOVSD	%XMM0,(%R15,%RDI,8)

(4016) 0x4d3055 MOV	(%R12,%RDX,8),%R8

(4016) 0x4d3059 MOV	%R8,(%R12,%RDI,8)

(4016) 0x4d305d MOV	%RSI,(%R12,%RDX,8)

(4016) 0x4d3061 JMP	4d3020

0x4d3063 MOV	%RDI,%RDX

0x4d3066 CMP	%RSI,%RAX

0x4d3069 JNE	4d3095

0x4d306b JMP	4d3075

0x4d306d MOV	%R8,%RDX

0x4d3070 CMP	%RSI,%RAX

0x4d3073 JNE	4d3095

0x4d3075 MOV	$0x536790,%EDI

0x4d307a MOV	%EBX,%ESI

0x4d307c ADD	$0x18,%RSP

0x4d3080 POP	%RBX

0x4d3081 POP	%R12

0x4d3083 POP	%R13

0x4d3085 POP	%R14

0x4d3087 POP	%R15

0x4d3089 POP	%RBP

0x4d308a JMP	410170

0x4d308f NOP

(4013) 0x4d3090 CMP	%RAX,%RDI

(4013) 0x4d3093 JE	4d3075

(4013) 0x4d3095 MOV	0x8(%R13,%RCX,8),%RSI

(4013) 0x4d309a CMP	%RSI,%RDX

(4013) 0x4d309d JGE	4d3100

(4013) 0x4d309f MOV	%RDX,%RDI

(4013) 0x4d30a2 JMP	4d30bd

0x4d30a4 NOPW	%CS:(%RAX,%RAX,1)

  (4015) 0x4d30b0 INC	%RDI

  (4015) 0x4d30b3 MOV	0x8(%R13,%RCX,8),%RSI

  (4015) 0x4d30b8 CMP	%RSI,%RDI

  (4015) 0x4d30bb JGE	4d3100

  (4015) 0x4d30bd MOV	(%R12,%RDI,8),%RSI

  (4015) 0x4d30c1 SUB	%R14,%RSI

  (4015) 0x4d30c4 MOV	%RSI,(%R12,%RDI,8)

  (4015) 0x4d30c8 CMP	%RCX,%RSI

  (4015) 0x4d30cb JNE	4d30b0

  (4015) 0x4d30cd VMOVSD	(%R15,%RDX,8),%XMM0

  (4015) 0x4d30d3 VMOVSD	(%R15,%RDI,8),%XMM1

  (4015) 0x4d30d9 VMOVSD	%XMM1,(%R15,%RDX,8)

  (4015) 0x4d30df VMOVSD	%XMM0,(%R15,%RDI,8)

  (4015) 0x4d30e5 MOV	(%R12,%RDX,8),%RSI

  (4015) 0x4d30e9 MOV	%RSI,(%R12,%RDI,8)

  (4015) 0x4d30ed MOV	%RCX,(%R12,%RDX,8)

  (4015) 0x4d30f1 JMP	4d30b0

0x4d30f3 NOPW	%CS:(%RAX,%RAX,1)

(4013) 0x4d3100 LEA	0x1(%RCX),%RDI

(4013) 0x4d3104 MOV	0x10(%R13,%RCX,8),%RDX

(4013) 0x4d3109 ADD	$0x2,%RCX

(4013) 0x4d310d CMP	%RDX,%RSI

(4013) 0x4d3110 JGE	4d3090

(4013) 0x4d3116 MOV	%RSI,%R8

(4013) 0x4d3119 JMP	4d3131

0x4d311b NOPL	(%RAX,%RAX,1)

  (4014) 0x4d3120 INC	%R8

  (4014) 0x4d3123 MOV	(%R13,%RCX,8),%RDX

  (4014) 0x4d3128 CMP	%RDX,%R8

  (4014) 0x4d312b JGE	4d3090

  (4014) 0x4d3131 MOV	(%R12,%R8,8),%RDX

  (4014) 0x4d3135 SUB	%R14,%RDX

  (4014) 0x4d3138 MOV	%RDX,(%R12,%R8,8)

  (4014) 0x4d313c CMP	%RDI,%RDX

  (4014) 0x4d313f JNE	4d3120

  (4014) 0x4d3141 VMOVSD	(%R15,%RSI,8),%XMM0

  (4014) 0x4d3147 VMOVSD	(%R15,%R8,8),%XMM1

  (4014) 0x4d314d VMOVSD	%XMM1,(%R15,%RSI,8)

  (4014) 0x4d3153 VMOVSD	%XMM0,(%R15,%R8,8)

  (4014) 0x4d3159 MOV	(%R12,%RSI,8),%RDX

  (4014) 0x4d315d MOV	%RDX,(%R12,%R8,8)

  (4014) 0x4d3161 MOV	%RDI,(%R12,%RSI,8)

  (4014) 0x4d3165 JMP	4d3120

0x4d3167 NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	IJMatrix_parcsr.c:2798-2812
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2798-2812.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.17 to 0.82 cycles (14.77x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2798

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	72
nb uops	73
loop length	260
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.17 cycles
front end	12.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.40	3.40	3.67	3.67	6.50	3.40	3.40	6.50	6.50	6.50	3.40	3.67
cycles	3.40	3.40	3.67	3.67	6.50	3.40	3.40	6.50	6.50	6.50	3.40	3.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.17
Dispatch	6.50
Overall L1	12.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	9%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.17 cycles. At this rate:

1% of peak load performance is reached (2.96 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.64 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.17 to 6.50 cycles (1.87x speedup).

ASM code

In the binary file, the address of the function is: 4d2f70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVL $0,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x1,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2c(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x38(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x18(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x536770,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 410420 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 4d3075 <hypre_IJMatrixAssembleParCSR.extracted.25+0x105>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R13,%RSI,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %ESI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
TEST $0x1,%CL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 4d3003 <hypre_IJMatrixAssembleParCSR.extracted.25+0x93>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 4d3095 <hypre_IJMatrixAssembleParCSR.extracted.25+0x125>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 4d3075 <hypre_IJMatrixAssembleParCSR.extracted.25+0x105>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
LEA 0x1(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x8(%R13,%RSI,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4d3063 <hypre_IJMatrixAssembleParCSR.extracted.25+0xf3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 4d302d <hypre_IJMatrixAssembleParCSR.extracted.25+0xbd>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 4d3095 <hypre_IJMatrixAssembleParCSR.extracted.25+0x125>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 4d3075 <hypre_IJMatrixAssembleParCSR.extracted.25+0x105>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %R8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 4d3095 <hypre_IJMatrixAssembleParCSR.extracted.25+0x125>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x536790,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 410170 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	IJMatrix_parcsr.c:2798-2812
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2798-2812.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2798

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	72
nb uops	73
loop length	260
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.17 cycles
front end	12.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.40	3.40	3.67	3.67	6.50	3.40	3.40	6.50	6.50	6.50	3.40	3.67
cycles	3.40	3.40	3.67	3.67	6.50	3.40	3.40	6.50	6.50	6.50	3.40	3.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.17
Dispatch	6.50
Overall L1	12.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	9%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.17 cycles. At this rate:

1% of peak load performance is reached (2.96 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.64 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4d2f70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVL $0,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x1,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2c(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x38(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x18(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x536770,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 410420 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 4d3075 <hypre_IJMatrixAssembleParCSR.extracted.25+0x105>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R13,%RSI,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %ESI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
TEST $0x1,%CL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 4d3003 <hypre_IJMatrixAssembleParCSR.extracted.25+0x93>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 4d3095 <hypre_IJMatrixAssembleParCSR.extracted.25+0x125>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 4d3075 <hypre_IJMatrixAssembleParCSR.extracted.25+0x105>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
LEA 0x1(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x8(%R13,%RSI,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4d3063 <hypre_IJMatrixAssembleParCSR.extracted.25+0xf3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 4d302d <hypre_IJMatrixAssembleParCSR.extracted.25+0xbd>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 4d3095 <hypre_IJMatrixAssembleParCSR.extracted.25+0x125>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 4d3075 <hypre_IJMatrixAssembleParCSR.extracted.25+0x105>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %R8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 4d3095 <hypre_IJMatrixAssembleParCSR.extracted.25+0x125>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x536790,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 410170 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼hypre_IJMatrixAssembleParCSR.extracted.25–	0.60	0.32
▼Loop 4013 - IJMatrix_parcsr.c:2798-2812 - exec–	0.00	0.01
○Loop 4014 - IJMatrix_parcsr.c:2803-2812 - exec	0.30	0.13
○Loop 4015 - IJMatrix_parcsr.c:2803-2812 - exec	0.29	0.13
○Loop 4016 - IJMatrix_parcsr.c:2803-2812 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code