OV - exec - Function hypre_BoomerAMGBuildMultipass.extracted.28

	Function: hypre_BoomerAMGBuildMultipass.extracted.28	Module: exec	Source: par_multi_interp.c:1737-1881 [...]	Coverage (incl. loops): 1.40% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1737 - 1881

--------------------------------------------------------------------------------

1737: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa,tmp_array,tmp_array_offd)

[...]

1747:              if (n_fine)

1748:              {    tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); }

1749:              tmp_marker_offd = NULL;

1750:              if (num_cols_offd)

1751:              {    tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1752:              tmp_array = NULL;

1753:              if (n_coarse)

1754:              {    tmp_array = hypre_CTAlloc(HYPRE_Int,n_coarse); }

[...]

1760:              for (i=0; i < n_fine; i++)

1761:              {    tmp_marker[i] = -1; }

1762:              for (i=0; i < num_cols_offd; i++)

1763:              {    tmp_marker_offd[i] = -1; }

1764:

1765:              /* Compute this thread's range of pass_length */

1766:              my_thread_num = hypre_GetThreadNum();

1767:              num_threads = hypre_NumActiveThreads();

1768:              thread_start = pass_pointer[pass] + (pass_length/num_threads)*my_thread_num;

1769:              if (my_thread_num == num_threads-1)

1770:              {  thread_stop = pass_pointer[pass] + pass_length; }

1771:              else

1772:              {  thread_stop = pass_pointer[pass] + (pass_length/num_threads)*(my_thread_num+1); }

1773:

1774:              for (i=thread_start; i < thread_stop; i++)

1775:              {

1776:                 i1 = pass_array[i];

1777:                 sum_C = 0;

1778:                 sum_N = 0;

1779:                 j_start = P_diag_start[i1];

1780:                 j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1781:                 cnt = P_diag_i[i1];

1782:                 for (j=j_start; j < j_end; j++)

1783:                 {

1784:                    k1 = P_diag_pass[pass][j];

1785:                tmp_array[k1] = cnt;

1786:                P_diag_data[cnt] = 0;

1787:                P_diag_j[cnt++] = k1;

1788:                 }

1789:                 j_start = P_offd_start[i1];

1790:                 j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1791:                 cnt_offd = P_offd_i[i1];

1792:                 for (j=j_start; j < j_end; j++)

1793:                 {

1794:                    k1 = P_offd_pass[pass][j];

1795:                tmp_array_offd[k1] = cnt_offd;

1796:                P_offd_data[cnt_offd] = 0;

1797:                P_offd_j[cnt_offd++] = k1;

1798:                 }

1799:                 for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1800:                 {

1801:                j1 = S_diag_j[j];

1802:                if (assigned[j1] == pass-1)

1803:                   tmp_marker[j1] = i1;

1804:                 }

1805:                 for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1806:                 {

1807:                j1 = S_offd_j[j];

1808:                if (assigned_offd[j1] == pass-1)

1809:                   tmp_marker_offd[j1] = i1;

1810:                 }

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

1838:                    }

1839:                 }

1840:                 for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1841:                 {

1842:                if (col_offd_S_to_A)

1843:                   j1 = map_A_to_S[A_offd_j[j]];

1844:                else

1845:                   j1 = A_offd_j[j];

1846:

1847:                if (j1 > -1 && tmp_marker_offd[j1] == i1)

1848:                {

1849:                   j_start = Pext_start[j1];

1850:                   j_end = j_start+Pext_i[j1+1];

1851:                   for (k=j_start; k < j_end; k++)

1852:                   {

1853:                  k1 = Pext_pass[pass][k];

1854:                      alfa = A_offd_data[j]*Pext_data[k];

1855:                  if (k1 < 0)

1856:                         P_diag_data[tmp_array[-k1-1]] += alfa;

1857:                  else

1858:                         P_offd_data[tmp_array_offd[k1]] += alfa;

1859:                      sum_C += alfa;

1860:                      sum_N += alfa;

1861:                       }

1862:                    }

1863:                    else

1864:                    {

1865:                       if (CF_marker_offd[j1] != -3 &&

1866:                 (num_functions == 1 || dof_func_offd[j1] == dof_func[i1]))

1867:                  sum_N += A_offd_data[j];

1868:                    }

1869:                 }

1870:                 diagonal = A_diag_data[A_diag_i[i1]];

1871:                 if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1872:

1873:                 for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++)

1874:                P_diag_data[j] *= alfa;

1875:                 for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++)

1876:                P_offd_data[j] *= alfa;

1877:              }

1878:              hypre_TFree(tmp_marker);

1879:              hypre_TFree(tmp_marker_offd);

1880:              hypre_TFree(tmp_array);

1881:              hypre_TFree(tmp_array_offd);

0x4438d0 PUSH	%RBP

0x4438d1 MOV	%RSP,%RBP

0x4438d4 PUSH	%R15

0x4438d6 PUSH	%R14

0x4438d8 PUSH	%R13

0x4438da PUSH	%R12

0x4438dc PUSH	%RBX

0x4438dd SUB	$0x178,%RSP

0x4438e4 MOV	%R9,-0x1a0(%RBP)

0x4438eb MOV	%R8,-0xd0(%RBP)

0x4438f2 MOV	%RCX,-0xf0(%RBP)

0x4438f9 MOV	%RDX,-0x158(%RBP)

0x443900 MOV	0x138(%RBP),%RAX

0x443907 MOV	%RAX,-0x80(%RBP)

0x44390b MOV	0x130(%RBP),%RAX

0x443912 MOV	%RAX,-0x38(%RBP)

0x443916 MOV	0x128(%RBP),%RAX

0x44391d MOV	%RAX,-0x148(%RBP)

0x443924 MOV	0x120(%RBP),%RAX

0x44392b MOV	%RAX,-0x198(%RBP)

0x443932 MOV	0x118(%RBP),%RAX

0x443939 MOV	%RAX,-0x190(%RBP)

0x443940 MOV	0x110(%RBP),%R15

0x443947 MOV	0x108(%RBP),%R12

0x44394e MOV	0x100(%RBP),%RDI

0x443955 MOV	0xf8(%RBP),%RAX

0x44395c MOV	%RAX,-0x58(%RBP)

0x443960 MOV	0xf0(%RBP),%RAX

0x443967 MOV	%RAX,-0x160(%RBP)

0x44396e MOV	0xe8(%RBP),%RAX

0x443975 MOV	%RAX,-0x150(%RBP)

0x44397c MOV	0xe0(%RBP),%RAX

0x443983 MOV	%RAX,-0x140(%RBP)

0x44398a MOV	0xd8(%RBP),%RAX

0x443991 MOV	%RAX,-0xc8(%RBP)

0x443998 MOV	0xd0(%RBP),%RAX

0x44399f MOV	%RAX,-0xc0(%RBP)

0x4439a6 MOV	0xc8(%RBP),%RAX

0x4439ad MOV	%RAX,-0x128(%RBP)

0x4439b4 MOV	0xc0(%RBP),%RAX

0x4439bb MOV	%RAX,-0x120(%RBP)

0x4439c2 MOV	0xb8(%RBP),%RAX

0x4439c9 MOV	%RAX,-0x48(%RBP)

0x4439cd MOV	0xb0(%RBP),%RAX

0x4439d4 MOV	%RAX,-0x118(%RBP)

0x4439db MOV	0xa8(%RBP),%RAX

0x4439e2 MOV	%RAX,-0x130(%RBP)

0x4439e9 MOV	0xa0(%RBP),%RAX

0x4439f0 MOV	%RAX,-0x168(%RBP)

0x4439f7 MOV	0x98(%RBP),%RAX

0x4439fe MOV	%RAX,-0x138(%RBP)

0x443a05 MOV	0x90(%RBP),%RAX

0x443a0c MOV	%RAX,-0x40(%RBP)

0x443a10 MOV	0x88(%RBP),%RAX

0x443a17 MOV	%RAX,-0xb8(%RBP)

0x443a1e MOV	0x80(%RBP),%R13

0x443a25 MOV	0x78(%RBP),%RAX

0x443a29 MOV	%RAX,-0x50(%RBP)

0x443a2d MOV	0x70(%RBP),%RAX

0x443a31 MOV	%RAX,-0xb0(%RBP)

0x443a38 MOV	0x68(%RBP),%R14

0x443a3c MOV	0x60(%RBP),%RCX

0x443a40 MOV	0x58(%RBP),%RAX

0x443a44 MOV	%RAX,-0x188(%RBP)

0x443a4b MOV	0x50(%RBP),%RAX

0x443a4f MOV	%RAX,-0xe8(%RBP)

0x443a56 MOV	0x48(%RBP),%RAX

0x443a5a MOV	%RAX,-0x180(%RBP)

0x443a61 MOV	0x40(%RBP),%RAX

0x443a65 MOV	%RAX,-0xe0(%RBP)

0x443a6c MOV	0x38(%RBP),%RAX

0x443a70 MOV	%RAX,-0x178(%RBP)

0x443a77 MOV	0x30(%RBP),%RAX

0x443a7b MOV	%RAX,-0x110(%RBP)

0x443a82 MOV	0x28(%RBP),%RAX

0x443a86 MOV	%RAX,-0xd8(%RBP)

0x443a8d MOV	0x20(%RBP),%RAX

0x443a91 MOV	%RAX,-0x170(%RBP)

0x443a98 MOV	0x18(%RBP),%RAX

0x443a9c MOV	%RAX,-0x108(%RBP)

0x443aa3 MOV	0x10(%RBP),%RBX

0x443aa7 TEST	%RDI,%RDI

0x443aaa MOV	%RCX,-0x30(%RBP)

0x443aae MOV	%RDI,-0xa8(%RBP)

0x443ab5 JE	443af6

0x443ab7 MOV	$0x8,%ESI

0x443abc CALL	4e72c0 <hypre_CAlloc>

0x443ac1 MOV	-0x30(%RBP),%RCX

0x443ac5 MOV	%RAX,-0x68(%RBP)

0x443ac9 TEST	%RCX,%RCX

0x443acc JE	443b01

0x443ace MOV	$0x8,%ESI

0x443ad3 MOV	%RCX,%RDI

0x443ad6 CALL	4e72c0 <hypre_CAlloc>

0x443adb MOV	%RAX,-0x60(%RBP)

0x443adf TEST	%R12,%R12

0x443ae2 JE	443b0c

0x443ae4 MOV	$0x8,%ESI

0x443ae9 MOV	%R12,%RDI

0x443aec CALL	4e72c0 <hypre_CAlloc>

0x443af1 MOV	%RAX,%R12

0x443af4 JMP	443b0f

0x443af6 XOR	%EAX,%EAX

0x443af8 MOV	%RAX,-0x68(%RBP)

0x443afc TEST	%RCX,%RCX

0x443aff JNE	443ace

0x443b01 XOR	%EAX,%EAX

0x443b03 MOV	%RAX,-0x60(%RBP)

0x443b07 TEST	%R12,%R12

0x443b0a JNE	443ae4

0x443b0c XOR	%R12D,%R12D

0x443b0f MOV	-0x38(%RBP),%RAX

0x443b13 CMP	%R15,%RAX

0x443b16 CMOVG	%RAX,%R15

0x443b1a MOV	$0x8,%ESI

0x443b1f MOV	%R15,%RDI

0x443b22 CALL	4e72c0 <hypre_CAlloc>

0x443b27 MOV	%RAX,%R15

0x443b2a MOV	-0xa8(%RBP),%RDX

0x443b31 TEST	%RDX,%RDX

0x443b34 JLE	443b48

0x443b36 SAL	$0x3,%RDX

0x443b3a MOV	-0x68(%RBP),%RDI

0x443b3e MOV	$0xff,%ESI

0x443b43 CALL	4f03c0 <_intel_fast_memset>

0x443b48 MOV	-0x30(%RBP),%RDX

0x443b4c TEST	%RDX,%RDX

0x443b4f JLE	443b63

0x443b51 SAL	$0x3,%RDX

0x443b55 MOV	-0x60(%RBP),%RDI

0x443b59 MOV	$0xff,%ESI

0x443b5e CALL	4f03c0 <_intel_fast_memset>

0x443b63 CALL	4e8ff0 <hypre_GetThreadNum>

0x443b68 MOV	%RAX,-0x30(%RBP)

0x443b6c CALL	4e8fe0 <hypre_NumActiveThreads>

0x443b71 MOV	%RAX,%RCX

0x443b74 MOV	-0x58(%RBP),%RAX

0x443b78 MOV	(%RAX),%RAX

0x443b7b MOV	-0x48(%RBP),%RDX

0x443b7f MOV	(%RDX,%RAX,8),%RSI

0x443b83 MOV	-0x80(%RBP),%R8

0x443b87 MOV	%R8,%RAX

0x443b8a OR	%RCX,%RAX

0x443b8d SHR	$0x20,%RAX

0x443b91 JE	443b9d

0x443b93 MOV	%R8,%RAX

0x443b96 CQTO

0x443b98 IDIV	%RCX

0x443b9b JMP	443ba4

0x443b9d MOV	%R8D,%EAX

0x443ba0 XOR	%EDX,%EDX

0x443ba2 DIV	%ECX

0x443ba4 MOV	-0x40(%RBP),%R10

0x443ba8 MOV	%RAX,%RDX

0x443bab MOV	-0x30(%RBP),%R9

0x443baf IMUL	%R9,%RDX

0x443bb3 DEC	%RCX

0x443bb6 LEA	0x1(%R9),%RDI

0x443bba IMUL	%RAX,%RDI

0x443bbe CMP	%RCX,%R9

0x443bc1 CMOVE	%R8,%RDI

0x443bc5 MOV	%RDI,-0xa0(%RBP)

0x443bcc CMP	%RDI,%RDX

0x443bcf JGE	4446db

0x443bd5 MOV	-0xa0(%RBP),%RAX

0x443bdc ADD	%RSI,%RAX

0x443bdf MOV	%RAX,-0xa0(%RBP)

0x443be6 ADD	%RSI,%RDX

0x443be9 MOV	-0x50(%RBP),%RAX

0x443bed ADD	$0x38,%RAX

0x443bf1 MOV	%RAX,-0x100(%RBP)

0x443bf8 LEA	0x38(%R10),%RAX

0x443bfc MOV	%RAX,-0xf8(%RBP)

0x443c03 VXORPD	%XMM9,%XMM9,%XMM9

0x443c08 MOV	%R12,-0x48(%RBP)

0x443c0c JMP	443c27

0x443c0e XCHG	%AX,%AX

(966) 0x443c10 MOV	-0xa8(%RBP),%RDX

(966) 0x443c17 INC	%RDX

(966) 0x443c1a CMP	-0xa0(%RBP),%RDX

(966) 0x443c21 JGE	4446db

(966) 0x443c27 MOV	-0x118(%RBP),%RAX

(966) 0x443c2e MOV	%RDX,-0xa8(%RBP)

(966) 0x443c35 MOV	(%RAX,%RDX,8),%R9

(966) 0x443c39 MOV	-0x120(%RBP),%RAX

(966) 0x443c40 MOV	(%RAX,%R9,8),%R8

(966) 0x443c44 MOV	-0xb0(%RBP),%RAX

(966) 0x443c4b MOV	(%RAX,%R9,8),%R12

(966) 0x443c4f MOV	0x8(%RAX,%R9,8),%RSI

(966) 0x443c54 LEA	(%RSI,%R8,1),%RAX

(966) 0x443c58 SUB	%R12,%RAX

(966) 0x443c5b CMP	%RAX,%R8

(966) 0x443c5e MOV	%R9,-0x30(%RBP)

(966) 0x443c62 JGE	443e3f

(966) 0x443c68 MOV	-0x58(%RBP),%RAX

(966) 0x443c6c MOV	(%RAX),%RCX

(966) 0x443c6f MOV	%RSI,%RAX

(966) 0x443c72 SUB	%R12,%RAX

(966) 0x443c75 CMP	$0xd,%RAX

(966) 0x443c79 JB	443e00

(966) 0x443c7f MOV	%RSI,-0x98(%RBP)

(966) 0x443c86 VMOVUPD	%XMM10,-0x80(%RBP)

(966) 0x443c8b LEA	(%R14,%R12,8),%RDI

(966) 0x443c8f LEA	(,%RAX,8),%RDX

(966) 0x443c97 XOR	%ESI,%ESI

(966) 0x443c99 MOV	%R8,-0x38(%RBP)

(966) 0x443c9d MOV	%RAX,-0x88(%RBP)

(966) 0x443ca4 MOV	%RCX,-0x90(%RBP)

(966) 0x443cab VZEROUPPER

(966) 0x443cae CALL	4f03c0 <_intel_fast_memset>

(966) 0x443cb3 MOV	-0xc0(%RBP),%RAX

(966) 0x443cba MOV	-0x90(%RBP),%RCX

(966) 0x443cc1 MOV	(%RAX,%RCX,8),%RAX

(966) 0x443cc5 MOV	-0x88(%RBP),%RCX

(966) 0x443ccc SHR	$0x3,%RCX

(966) 0x443cd0 MOV	-0x38(%RBP),%RDX

(966) 0x443cd4 LEA	0x38(%RAX,%RDX,8),%RDX

(966) 0x443cd9 MOV	-0x100(%RBP),%RSI

(966) 0x443ce0 LEA	(%RSI,%R12,8),%RSI

(966) 0x443ce4 MOV	%RCX,%RDI

(966) 0x443ce7 XOR	%R8D,%R8D

(966) 0x443cea MOV	-0x48(%RBP),%R11

(966) 0x443cee XCHG	%AX,%AX

  (984) 0x443cf0 MOV	-0x38(%RDX,%R8,8),%R9

  (984) 0x443cf5 LEA	(%R12,%R8,1),%R10

  (984) 0x443cf9 MOV	%R10,(%R11,%R9,8)

  (984) 0x443cfd MOV	%R9,-0x38(%RSI,%R8,8)

  (984) 0x443d02 MOV	-0x30(%RDX,%R8,8),%R9

  (984) 0x443d07 LEA	0x1(%R12,%R8,1),%R10

  (984) 0x443d0c MOV	%R10,(%R11,%R9,8)

  (984) 0x443d10 MOV	%R9,-0x30(%RSI,%R8,8)

  (984) 0x443d15 MOV	-0x28(%RDX,%R8,8),%R9

  (984) 0x443d1a LEA	0x2(%R12,%R8,1),%R10

  (984) 0x443d1f MOV	%R10,(%R11,%R9,8)

  (984) 0x443d23 MOV	%R9,-0x28(%RSI,%R8,8)

  (984) 0x443d28 MOV	-0x20(%RDX,%R8,8),%R9

  (984) 0x443d2d LEA	0x3(%R12,%R8,1),%R10

  (984) 0x443d32 MOV	%R10,(%R11,%R9,8)

  (984) 0x443d36 MOV	%R9,-0x20(%RSI,%R8,8)

  (984) 0x443d3b MOV	-0x18(%RDX,%R8,8),%R9

  (984) 0x443d40 LEA	0x4(%R12,%R8,1),%R10

  (984) 0x443d45 MOV	%R10,(%R11,%R9,8)

  (984) 0x443d49 MOV	%R9,-0x18(%RSI,%R8,8)

  (984) 0x443d4e MOV	-0x10(%RDX,%R8,8),%R9

  (984) 0x443d53 LEA	0x5(%R12,%R8,1),%R10

  (984) 0x443d58 MOV	%R10,(%R11,%R9,8)

  (984) 0x443d5c MOV	%R9,-0x10(%RSI,%R8,8)

  (984) 0x443d61 MOV	-0x8(%RDX,%R8,8),%R9

  (984) 0x443d66 LEA	0x6(%R12,%R8,1),%R10

  (984) 0x443d6b MOV	%R10,(%R11,%R9,8)

  (984) 0x443d6f MOV	%R9,-0x8(%RSI,%R8,8)

  (984) 0x443d74 MOV	(%RDX,%R8,8),%R9

  (984) 0x443d78 LEA	0x7(%R12,%R8,1),%R10

  (984) 0x443d7d MOV	%R10,(%R11,%R9,8)

  (984) 0x443d81 MOV	%R9,(%RSI,%R8,8)

  (984) 0x443d85 ADD	$0x8,%R8

  (984) 0x443d89 DEC	%RDI

  (984) 0x443d8c JNE	443cf0

(966) 0x443d92 MOV	-0x88(%RBP),%RSI

(966) 0x443d99 MOV	%RSI,%RDX

(966) 0x443d9c AND	$-0x8,%RDX

(966) 0x443da0 CMP	%RSI,%RDX

(966) 0x443da3 MOV	-0x40(%RBP),%R10

(966) 0x443da7 MOV	-0x50(%RBP),%RSI

(966) 0x443dab VXORPD	%XMM9,%XMM9,%XMM9

(966) 0x443db0 MOV	-0x30(%RBP),%R9

(966) 0x443db4 VMOVUPD	-0x80(%RBP),%XMM10

(966) 0x443db9 MOV	-0x98(%RBP),%RDI

(966) 0x443dc0 MOV	-0x38(%RBP),%R8

(966) 0x443dc4 JAE	443e3f

(966) 0x443dc6 ADD	%RDX,%R12

(966) 0x443dc9 SAL	$0x6,%RCX

(966) 0x443dcd LEA	(%RCX,%R8,8),%RCX

(966) 0x443dd1 ADD	%RCX,%RAX

(966) 0x443dd4 NOPW	%CS:(%RAX,%RAX,1)

  (985) 0x443de0 MOV	(%RAX),%RCX

  (985) 0x443de3 MOV	%R12,(%R11,%RCX,8)

  (985) 0x443de7 MOV	%RCX,(%RSI,%R12,8)

  (985) 0x443deb INC	%R12

  (985) 0x443dee ADD	$0x8,%RAX

  (985) 0x443df2 CMP	%R12,%RDI

  (985) 0x443df5 JNE	443de0

(966) 0x443df7 JMP	443e3f

0x443df9 NOPL	(%RAX)

(966) 0x443e00 SAL	$0x3,%R8

(966) 0x443e04 MOV	-0xc0(%RBP),%RAX

(966) 0x443e0b ADD	(%RAX,%RCX,8),%R8

(966) 0x443e0f MOV	-0x50(%RBP),%RCX

(966) 0x443e13 MOV	-0x48(%RBP),%RDX

(966) 0x443e17 NOPW	(%RAX,%RAX,1)

  (983) 0x443e20 MOV	(%R8),%RAX

  (983) 0x443e23 MOV	%R12,(%RDX,%RAX,8)

  (983) 0x443e27 MOVQ	$0,(%R14,%R12,8)

  (983) 0x443e2f MOV	%RAX,(%RCX,%R12,8)

  (983) 0x443e33 INC	%R12

  (983) 0x443e36 ADD	$0x8,%R8

  (983) 0x443e3a CMP	%R12,%RSI

  (983) 0x443e3d JNE	443e20

(966) 0x443e3f MOV	-0x128(%RBP),%RAX

(966) 0x443e46 MOV	(%RAX,%R9,8),%R8

(966) 0x443e4a MOV	-0xb8(%RBP),%RAX

(966) 0x443e51 MOV	(%RAX,%R9,8),%R12

(966) 0x443e55 MOV	0x8(%RAX,%R9,8),%RCX

(966) 0x443e5a LEA	(%RCX,%R8,1),%RAX

(966) 0x443e5e SUB	%R12,%RAX

(966) 0x443e61 CMP	%RAX,%R8

(966) 0x443e64 JGE	444020

(966) 0x443e6a MOV	-0x58(%RBP),%RAX

(966) 0x443e6e MOV	(%RAX),%RDX

(966) 0x443e71 MOV	%RCX,%RAX

(966) 0x443e74 SUB	%R12,%RAX

(966) 0x443e77 CMP	$0xd,%RAX

(966) 0x443e7b JB	443ff0

(966) 0x443e81 MOV	%RCX,-0x88(%RBP)

(966) 0x443e88 VMOVUPD	%XMM10,-0x80(%RBP)

(966) 0x443e8d LEA	(%R13,%R12,8),%RDI

(966) 0x443e92 MOV	%RDX,-0x90(%RBP)

(966) 0x443e99 LEA	(,%RAX,8),%RDX

(966) 0x443ea1 XOR	%ESI,%ESI

(966) 0x443ea3 MOV	%R8,-0x98(%RBP)

(966) 0x443eaa MOV	%RAX,-0x38(%RBP)

(966) 0x443eae VZEROUPPER

(966) 0x443eb1 CALL	4f03c0 <_intel_fast_memset>

(966) 0x443eb6 MOV	-0x98(%RBP),%R11

(966) 0x443ebd MOV	-0xc8(%RBP),%RAX

(966) 0x443ec4 MOV	-0x90(%RBP),%RCX

(966) 0x443ecb MOV	(%RAX,%RCX,8),%RAX

(966) 0x443ecf MOV	-0x38(%RBP),%RCX

(966) 0x443ed3 SHR	$0x3,%RCX

(966) 0x443ed7 LEA	0x38(%RAX,%R11,8),%RDX

(966) 0x443edc MOV	-0xf8(%RBP),%RSI

(966) 0x443ee3 LEA	(%RSI,%R12,8),%RSI

(966) 0x443ee7 MOV	%RCX,%RDI

(966) 0x443eea XOR	%R8D,%R8D

(966) 0x443eed NOPL	(%RAX)

  (981) 0x443ef0 MOV	-0x38(%RDX,%R8,8),%R9

  (981) 0x443ef5 LEA	(%R12,%R8,1),%R10

  (981) 0x443ef9 MOV	%R10,(%R15,%R9,8)

  (981) 0x443efd MOV	%R9,-0x38(%RSI,%R8,8)

  (981) 0x443f02 MOV	-0x30(%RDX,%R8,8),%R9

  (981) 0x443f07 LEA	0x1(%R12,%R8,1),%R10

  (981) 0x443f0c MOV	%R10,(%R15,%R9,8)

  (981) 0x443f10 MOV	%R9,-0x30(%RSI,%R8,8)

  (981) 0x443f15 MOV	-0x28(%RDX,%R8,8),%R9

  (981) 0x443f1a LEA	0x2(%R12,%R8,1),%R10

  (981) 0x443f1f MOV	%R10,(%R15,%R9,8)

  (981) 0x443f23 MOV	%R9,-0x28(%RSI,%R8,8)

  (981) 0x443f28 MOV	-0x20(%RDX,%R8,8),%R9

  (981) 0x443f2d LEA	0x3(%R12,%R8,1),%R10

  (981) 0x443f32 MOV	%R10,(%R15,%R9,8)

  (981) 0x443f36 MOV	%R9,-0x20(%RSI,%R8,8)

  (981) 0x443f3b MOV	-0x18(%RDX,%R8,8),%R9

  (981) 0x443f40 LEA	0x4(%R12,%R8,1),%R10

  (981) 0x443f45 MOV	%R10,(%R15,%R9,8)

  (981) 0x443f49 MOV	%R9,-0x18(%RSI,%R8,8)

  (981) 0x443f4e MOV	-0x10(%RDX,%R8,8),%R9

  (981) 0x443f53 LEA	0x5(%R12,%R8,1),%R10

  (981) 0x443f58 MOV	%R10,(%R15,%R9,8)

  (981) 0x443f5c MOV	%R9,-0x10(%RSI,%R8,8)

  (981) 0x443f61 MOV	-0x8(%RDX,%R8,8),%R9

  (981) 0x443f66 LEA	0x6(%R12,%R8,1),%R10

  (981) 0x443f6b MOV	%R10,(%R15,%R9,8)

  (981) 0x443f6f MOV	%R9,-0x8(%RSI,%R8,8)

  (981) 0x443f74 MOV	(%RDX,%R8,8),%R9

  (981) 0x443f78 LEA	0x7(%R12,%R8,1),%R10

  (981) 0x443f7d MOV	%R10,(%R15,%R9,8)

  (981) 0x443f81 MOV	%R9,(%RSI,%R8,8)

  (981) 0x443f85 ADD	$0x8,%R8

  (981) 0x443f89 DEC	%RDI

  (981) 0x443f8c JNE	443ef0

(966) 0x443f92 MOV	-0x38(%RBP),%RSI

(966) 0x443f96 MOV	%RSI,%RDX

(966) 0x443f99 AND	$-0x8,%RDX

(966) 0x443f9d CMP	%RSI,%RDX

(966) 0x443fa0 MOV	-0x40(%RBP),%R10

(966) 0x443fa4 VXORPD	%XMM9,%XMM9,%XMM9

(966) 0x443fa9 MOV	-0x30(%RBP),%R9

(966) 0x443fad VMOVUPD	-0x80(%RBP),%XMM10

(966) 0x443fb2 MOV	-0x88(%RBP),%RSI

(966) 0x443fb9 JAE	444020

(966) 0x443fbb ADD	%RDX,%R12

(966) 0x443fbe SAL	$0x6,%RCX

(966) 0x443fc2 LEA	(%RCX,%R11,8),%RCX

(966) 0x443fc6 ADD	%RCX,%RAX

(966) 0x443fc9 NOPL	(%RAX)

  (982) 0x443fd0 MOV	(%RAX),%RCX

  (982) 0x443fd3 MOV	%R12,(%R15,%RCX,8)

  (982) 0x443fd7 MOV	%RCX,(%R10,%R12,8)

  (982) 0x443fdb INC	%R12

  (982) 0x443fde ADD	$0x8,%RAX

  (982) 0x443fe2 CMP	%R12,%RSI

  (982) 0x443fe5 JNE	443fd0

(966) 0x443fe7 JMP	444020

0x443fe9 NOPL	(%RAX)

(966) 0x443ff0 SAL	$0x3,%R8

(966) 0x443ff4 MOV	-0xc8(%RBP),%RAX

(966) 0x443ffb ADD	(%RAX,%RDX,8),%R8

(966) 0x443fff NOP

  (980) 0x444000 MOV	(%R8),%RAX

  (980) 0x444003 MOV	%R12,(%R15,%RAX,8)

  (980) 0x444007 MOVQ	$0,(%R13,%R12,8)

  (980) 0x444010 MOV	%RAX,(%R10,%R12,8)

  (980) 0x444014 INC	%R12

  (980) 0x444017 ADD	$0x8,%R8

  (980) 0x44401b CMP	%R12,%RCX

  (980) 0x44401e JNE	444000

(966) 0x444020 MOV	-0xe0(%RBP),%RCX

(966) 0x444027 MOV	(%RCX,%R9,8),%RAX

(966) 0x44402b MOV	0x8(%RCX,%R9,8),%RCX

(966) 0x444030 CMP	%RCX,%RAX

(966) 0x444033 MOV	-0x48(%RBP),%R12

(966) 0x444037 JGE	444090

(966) 0x444039 MOV	-0x58(%RBP),%RDX

(966) 0x44403d MOV	(%RDX),%RDX

(966) 0x444040 DEC	%RDX

(966) 0x444043 JMP	444058

0x444045 NOPW	%CS:(%RAX,%RAX,1)

  (979) 0x444050 INC	%RAX

  (979) 0x444053 CMP	%RCX,%RAX

  (979) 0x444056 JGE	444090

  (979) 0x444058 MOV	-0x180(%RBP),%RSI

  (979) 0x44405f MOV	(%RSI,%RAX,8),%RSI

  (979) 0x444063 MOV	-0x190(%RBP),%RDI

  (979) 0x44406a CMP	%RDX,(%RDI,%RSI,8)

  (979) 0x44406e JNE	444050

  (979) 0x444070 MOV	-0x68(%RBP),%RCX

  (979) 0x444074 MOV	%R9,(%RCX,%RSI,8)

  (979) 0x444078 MOV	-0xe0(%RBP),%RCX

  (979) 0x44407f MOV	0x8(%RCX,%R9,8),%RCX

  (979) 0x444084 JMP	444050

0x444086 NOPW	%CS:(%RAX,%RAX,1)

(966) 0x444090 MOV	-0xe8(%RBP),%RCX

(966) 0x444097 MOV	(%RCX,%R9,8),%RAX

(966) 0x44409b MOV	0x8(%RCX,%R9,8),%RCX

(966) 0x4440a0 CMP	%RCX,%RAX

(966) 0x4440a3 JGE	444100

(966) 0x4440a5 MOV	-0x58(%RBP),%RDX

(966) 0x4440a9 MOV	(%RDX),%RDX

(966) 0x4440ac DEC	%RDX

(966) 0x4440af JMP	4440c8

0x4440b1 NOPW	%CS:(%RAX,%RAX,1)

  (978) 0x4440c0 INC	%RAX

  (978) 0x4440c3 CMP	%RCX,%RAX

  (978) 0x4440c6 JGE	444100

  (978) 0x4440c8 MOV	-0x188(%RBP),%RSI

  (978) 0x4440cf MOV	(%RSI,%RAX,8),%RSI

  (978) 0x4440d3 MOV	-0x198(%RBP),%RDI

  (978) 0x4440da CMP	%RDX,(%RDI,%RSI,8)

  (978) 0x4440de JNE	4440c0

  (978) 0x4440e0 MOV	-0x60(%RBP),%RCX

  (978) 0x4440e4 MOV	%R9,(%RCX,%RSI,8)

  (978) 0x4440e8 MOV	-0xe8(%RBP),%RCX

  (978) 0x4440ef MOV	0x8(%RCX,%R9,8),%RCX

  (978) 0x4440f4 JMP	4440c0

0x4440f6 NOPW	%CS:(%RAX,%RAX,1)

(966) 0x444100 MOV	-0x108(%RBP),%RAX

(966) 0x444107 MOV	(%RAX,%R9,8),%RCX

(966) 0x44410b MOV	0x8(%RAX,%R9,8),%R11

(966) 0x444110 LEA	0x1(%RCX),%RDX

(966) 0x444114 VXORPD	%XMM1,%XMM1,%XMM1

(966) 0x444118 CMP	%R11,%RDX

(966) 0x44411b MOV	%RCX,-0x38(%RBP)

(966) 0x44411f VXORPD	%XMM0,%XMM0,%XMM0

(966) 0x444123 JGE	444460

(966) 0x444129 MOV	-0x50(%RBP),%RAX

(966) 0x44412d MOV	%R11,-0x80(%RBP)

(966) 0x444131 JMP	444154

0x444133 NOPW	%CS:(%RAX,%RAX,1)

  (973) 0x444140 MOV	-0x50(%RBP),%RAX

  (973) 0x444144 MOV	-0x30(%RBP),%R9

  (973) 0x444148 INC	%RDX

  (973) 0x44414b CMP	%R11,%RDX

  (973) 0x44414e JE	444460

  (973) 0x444154 MOV	-0x170(%RBP),%RSI

  (973) 0x44415b MOV	(%RSI,%RDX,8),%RSI

  (973) 0x44415f MOV	-0x68(%RBP),%RDI

  (973) 0x444163 CMP	%R9,(%RDI,%RSI,8)

  (973) 0x444167 JNE	444190

  (973) 0x444169 MOV	-0xb0(%RBP),%R8

  (973) 0x444170 MOV	(%R8,%RSI,8),%RDI

  (973) 0x444174 MOV	0x8(%R8,%RSI,8),%R8

  (973) 0x444179 MOV	%R8,%R9

  (973) 0x44417c SUB	%RDI,%R9

  (973) 0x44417f JLE	4442e9

  (973) 0x444185 CMP	$0x4,%R9

  (973) 0x444189 JAE	4441c0

  (973) 0x44418b JMP	444295

  (973) 0x444190 MOV	-0x158(%RBP),%RDI

  (973) 0x444197 CMPQ	$-0x3,(%RDI,%RSI,8)

  (973) 0x44419c JE	444148

  (973) 0x44419e CMPQ	$0x1,-0xf0(%RBP)

  (973) 0x4441a6 JE	4441b9

  (973) 0x4441a8 MOV	-0xd0(%RBP),%R8

  (973) 0x4441af MOV	(%R8,%R9,8),%RDI

  (973) 0x4441b3 CMP	(%R8,%RSI,8),%RDI

  (973) 0x4441b7 JNE	444148

  (973) 0x4441b9 VADDSD	(%RBX,%RDX,8),%XMM0,%XMM0

  (973) 0x4441be JMP	444148

  (973) 0x4441c0 MOV	%R9,%R10

  (973) 0x4441c3 SHR	$0x2,%R10

  (973) 0x4441c7 LEA	0x18(,%RDI,8),%R11

  (973) 0x4441cf MOV	%R12,%RCX

  (973) 0x4441d2 NOPW	%CS:(%RAX,%RAX,1)

    (976) 0x4441e0 MOV	-0x18(%RAX,%R11,1),%R12

    (976) 0x4441e5 VMOVSD	-0x18(%R14,%R11,1),%XMM2

    (976) 0x4441ec VMOVSD	(%RBX,%RDX,8),%XMM3

    (976) 0x4441f1 MOV	(%RCX,%R12,8),%R12

    (976) 0x4441f5 VMOVSD	(%R14,%R12,8),%XMM4

    (976) 0x4441fb VFMADD231SD	%XMM2,%XMM3,%XMM4

    (976) 0x444200 VMOVSD	%XMM4,(%R14,%R12,8)

    (976) 0x444206 MOV	-0x10(%RAX,%R11,1),%R12

    (976) 0x44420b VMOVSD	-0x10(%R14,%R11,1),%XMM4

    (976) 0x444212 VMOVSD	(%RBX,%RDX,8),%XMM5

    (976) 0x444217 MOV	(%RCX,%R12,8),%R12

    (976) 0x44421b VMOVSD	(%R14,%R12,8),%XMM6

    (976) 0x444221 VFMADD231SD	%XMM4,%XMM5,%XMM6

    (976) 0x444226 VMOVSD	%XMM6,(%R14,%R12,8)

    (976) 0x44422c MOV	-0x8(%RAX,%R11,1),%R12

    (976) 0x444231 VMOVSD	-0x8(%R14,%R11,1),%XMM6

    (976) 0x444238 VMOVSD	(%RBX,%RDX,8),%XMM7

    (976) 0x44423d MOV	(%RCX,%R12,8),%R12

    (976) 0x444241 VMOVSD	(%R14,%R12,8),%XMM8

    (976) 0x444247 VFMADD231SD	%XMM6,%XMM7,%XMM8

    (976) 0x44424c VMOVSD	%XMM8,(%R14,%R12,8)

    (976) 0x444252 VMOVSD	(%R14,%R11,1),%XMM8

    (976) 0x444258 VMULSD	(%RBX,%RDX,8),%XMM8,%XMM10

    (976) 0x44425d MOV	(%RAX,%R11,1),%R12

    (976) 0x444261 MOV	(%RCX,%R12,8),%R12

    (976) 0x444265 VADDSD	(%R14,%R12,8),%XMM10,%XMM8

    (976) 0x44426b VMOVSD	%XMM8,(%R14,%R12,8)

    (976) 0x444271 VFMADD213SD	%XMM10,%XMM5,%XMM4

    (976) 0x444276 VFMADD231SD	%XMM2,%XMM3,%XMM4

    (976) 0x44427b VFMADD231SD	%XMM6,%XMM7,%XMM4

    (976) 0x444280 VADDSD	%XMM1,%XMM4,%XMM1

    (976) 0x444284 VADDSD	%XMM0,%XMM4,%XMM0

    (976) 0x444288 ADD	$0x20,%R11

    (976) 0x44428c DEC	%R10

    (976) 0x44428f JNE	4441e0

  (973) 0x444295 MOV	%R9,%R10

  (973) 0x444298 AND	$-0x4,%R10

  (973) 0x44429c CMP	%R9,%R10

  (973) 0x44429f MOV	-0x80(%RBP),%R11

  (973) 0x4442a3 JAE	4442e1

  (973) 0x4442a5 ADD	%R10,%RDI

  (973) 0x4442a8 MOV	-0x40(%RBP),%R10

  (973) 0x4442ac MOV	-0x48(%RBP),%R12

    (977) 0x4442b0 MOV	(%RAX,%RDI,8),%R9

    (977) 0x4442b4 VMOVSD	(%R14,%RDI,8),%XMM2

    (977) 0x4442ba VMULSD	(%RBX,%RDX,8),%XMM2,%XMM10

    (977) 0x4442bf MOV	(%R12,%R9,8),%R9

    (977) 0x4442c3 VADDSD	(%R14,%R9,8),%XMM10,%XMM2

    (977) 0x4442c9 VMOVSD	%XMM2,(%R14,%R9,8)

    (977) 0x4442cf VADDSD	%XMM1,%XMM10,%XMM1

    (977) 0x4442d3 VADDSD	%XMM0,%XMM10,%XMM0

    (977) 0x4442d7 INC	%RDI

    (977) 0x4442da CMP	%RDI,%R8

    (977) 0x4442dd JNE	4442b0

  (973) 0x4442df JMP	4442e9

  (973) 0x4442e1 MOV	-0x40(%RBP),%R10

  (973) 0x4442e5 MOV	-0x48(%RBP),%R12

  (973) 0x4442e9 MOV	-0xb8(%RBP),%RAX

  (973) 0x4442f0 MOV	(%RAX,%RSI,8),%RDI

  (973) 0x4442f4 MOV	0x8(%RAX,%RSI,8),%RSI

  (973) 0x4442f9 MOV	%RSI,%R8

  (973) 0x4442fc SUB	%RDI,%R8

  (973) 0x4442ff JLE	444140

  (973) 0x444305 CMP	$0x4,%R8

  (973) 0x444309 JAE	444310

  (973) 0x44430b JMP	4443ee

  (973) 0x444310 MOV	%R8,%R9

  (973) 0x444313 SHR	$0x2,%R9

  (973) 0x444317 MOV	%R10,%RAX

  (973) 0x44431a LEA	0x18(,%RDI,8),%R10

  (973) 0x444322 NOPW	%CS:(%RAX,%RAX,1)

    (974) 0x444330 MOV	-0x18(%RAX,%R10,1),%R11

    (974) 0x444335 VMOVSD	-0x18(%R13,%R10,1),%XMM2

    (974) 0x44433c VMOVSD	(%RBX,%RDX,8),%XMM3

    (974) 0x444341 MOV	(%R15,%R11,8),%R11

    (974) 0x444345 VMOVSD	(%R13,%R11,8),%XMM4

    (974) 0x44434c VFMADD231SD	%XMM2,%XMM3,%XMM4

    (974) 0x444351 VMOVSD	%XMM4,(%R13,%R11,8)

    (974) 0x444358 MOV	-0x10(%RAX,%R10,1),%R11

    (974) 0x44435d VMOVSD	-0x10(%R13,%R10,1),%XMM4

    (974) 0x444364 VMOVSD	(%RBX,%RDX,8),%XMM5

    (974) 0x444369 MOV	(%R15,%R11,8),%R11

    (974) 0x44436d VMOVSD	(%R13,%R11,8),%XMM6

    (974) 0x444374 VFMADD231SD	%XMM4,%XMM5,%XMM6

    (974) 0x444379 VMOVSD	%XMM6,(%R13,%R11,8)

    (974) 0x444380 MOV	-0x8(%RAX,%R10,1),%R11

    (974) 0x444385 VMOVSD	-0x8(%R13,%R10,1),%XMM6

    (974) 0x44438c VMOVSD	(%RBX,%RDX,8),%XMM7

    (974) 0x444391 MOV	(%R15,%R11,8),%R11

    (974) 0x444395 VMOVSD	(%R13,%R11,8),%XMM8

    (974) 0x44439c VFMADD231SD	%XMM6,%XMM7,%XMM8

    (974) 0x4443a1 VMOVSD	%XMM8,(%R13,%R11,8)

    (974) 0x4443a8 VMOVSD	(%R13,%R10,1),%XMM8

    (974) 0x4443af VMULSD	(%RBX,%RDX,8),%XMM8,%XMM10

    (974) 0x4443b4 MOV	(%RAX,%R10,1),%R11

    (974) 0x4443b8 MOV	(%R15,%R11,8),%R11

    (974) 0x4443bc VADDSD	(%R13,%R11,8),%XMM10,%XMM8

    (974) 0x4443c3 VMOVSD	%XMM8,(%R13,%R11,8)

    (974) 0x4443ca VFMADD213SD	%XMM10,%XMM5,%XMM4

    (974) 0x4443cf VFMADD231SD	%XMM2,%XMM3,%XMM4

    (974) 0x4443d4 VFMADD231SD	%XMM6,%XMM7,%XMM4

    (974) 0x4443d9 VADDSD	%XMM1,%XMM4,%XMM1

    (974) 0x4443dd VADDSD	%XMM0,%XMM4,%XMM0

    (974) 0x4443e1 ADD	$0x20,%R10

    (974) 0x4443e5 DEC	%R9

    (974) 0x4443e8 JNE	444330

  (973) 0x4443ee MOV	%R8,%R9

  (973) 0x4443f1 AND	$-0x4,%R9

  (973) 0x4443f5 CMP	%R8,%R9

  (973) 0x4443f8 JAE	444447

  (973) 0x4443fa ADD	%R9,%RDI

  (973) 0x4443fd MOV	-0x40(%RBP),%R10

  (973) 0x444401 MOV	-0x50(%RBP),%RAX

  (973) 0x444405 MOV	-0x30(%RBP),%R9

  (973) 0x444409 MOV	-0x80(%RBP),%R11

  (973) 0x44440d NOPL	(%RAX)

    (975) 0x444410 MOV	(%R10,%RDI,8),%R8

    (975) 0x444414 VMOVSD	(%R13,%RDI,8),%XMM2

    (975) 0x44441b VMULSD	(%RBX,%RDX,8),%XMM2,%XMM10

    (975) 0x444420 MOV	(%R15,%R8,8),%R8

    (975) 0x444424 VADDSD	(%R13,%R8,8),%XMM10,%XMM2

    (975) 0x44442b VMOVSD	%XMM2,(%R13,%R8,8)

    (975) 0x444432 VADDSD	%XMM1,%XMM10,%XMM1

    (975) 0x444436 VADDSD	%XMM0,%XMM10,%XMM0

    (975) 0x44443a INC	%RDI

    (975) 0x44443d CMP	%RDI,%RSI

    (975) 0x444440 JNE	444410

  (973) 0x444442 JMP	444148

  (973) 0x444447 MOV	-0x40(%RBP),%R10

  (973) 0x44444b MOV	-0x50(%RBP),%RAX

  (973) 0x44444f MOV	-0x30(%RBP),%R9

  (973) 0x444453 MOV	-0x80(%RBP),%R11

  (973) 0x444457 JMP	444148

0x44445c NOPL	(%RAX)

(966) 0x444460 MOV	-0x110(%RBP),%RAX

(966) 0x444467 MOV	(%RAX,%R9,8),%RCX

(966) 0x44446b MOV	0x8(%RAX,%R9,8),%RDX

(966) 0x444470 CMP	%RDX,%RCX

(966) 0x444473 JL	444520

(966) 0x444479 MOV	-0x38(%RBP),%RAX

(966) 0x44447d VMULSD	(%RBX,%RAX,8),%XMM1,%XMM1

(966) 0x444482 VUCOMISD	%XMM9,%XMM1

(966) 0x444487 JE	444497

(966) 0x444489 VXORPD	0xbb7ad(%RIP){1to2},%XMM0,%XMM0

(966) 0x444493 VDIVSD	%XMM1,%XMM0,%XMM10

(966) 0x444497 MOV	-0xb0(%RBP),%RAX

(966) 0x44449e MOV	(%RAX,%R9,8),%RDX

(966) 0x4444a2 MOV	0x8(%RAX,%R9,8),%RAX

(966) 0x4444a7 MOV	%RAX,%RSI

(966) 0x4444aa SUB	%RDX,%RSI

(966) 0x4444ad JLE	444654

(966) 0x4444b3 MOV	%RSI,%RCX

(966) 0x4444b6 AND	$-0x4,%RCX

(966) 0x4444ba JE	444638

(966) 0x4444c0 LEA	-0x1(%RCX),%RDI

(966) 0x4444c4 VBROADCASTSD	%XMM10,%YMM0

(966) 0x4444c9 LEA	(%R14,%RDX,8),%R8

(966) 0x4444cd XOR	%R9D,%R9D

  (970) 0x4444d0 VMULPD	(%R8,%R9,8),%YMM0,%YMM1

  (970) 0x4444d6 VMOVUPD	%YMM1,(%R8,%R9,8)

  (970) 0x4444dc ADD	$0x4,%R9

  (970) 0x4444e0 CMP	%RDI,%R9

  (970) 0x4444e3 JBE	4444d0

(966) 0x4444e5 CMP	%RCX,%RSI

(966) 0x4444e8 MOV	-0x30(%RBP),%R9

(966) 0x4444ec JNE	44463a

(966) 0x4444f2 JMP	444654

0x4444f7 NOPW	(%RAX,%RAX,1)

  (971) 0x444500 VADDSD	(%R8,%RCX,8),%XMM0,%XMM0

  (971) 0x444506 MOV	%R12,%R11

  (971) 0x444509 INC	%RCX

  (971) 0x44450c CMP	%RDX,%RCX

  (971) 0x44450f MOV	-0x40(%RBP),%R10

  (971) 0x444513 MOV	%R11,%R12

  (971) 0x444516 MOV	-0x30(%RBP),%R9

  (971) 0x44451a JE	444479

  (971) 0x444520 MOV	-0x178(%RBP),%RAX

  (971) 0x444527 LEA	(%RAX,%RCX,8),%RSI

  (971) 0x44452b CMPQ	$0,-0x1a0(%RBP)

  (971) 0x444533 JE	444543

  (971) 0x444535 MOV	(%RSI),%RSI

  (971) 0x444538 MOV	-0x160(%RBP),%RDI

  (971) 0x44453f LEA	(%RDI,%RSI,8),%RSI

  (971) 0x444543 MOV	(%RSI),%RDI

  (971) 0x444546 TEST	%RDI,%RDI

  (971) 0x444549 JS	4445f0

  (971) 0x44454f MOV	-0x60(%RBP),%RSI

  (971) 0x444553 CMP	%R9,(%RSI,%RDI,8)

  (971) 0x444557 JNE	4445f0

  (971) 0x44455d MOV	-0x150(%RBP),%RSI

  (971) 0x444564 MOV	0x8(%RSI,%RDI,8),%RSI

  (971) 0x444569 TEST	%RSI,%RSI

  (971) 0x44456c JLE	444506

  (971) 0x44456e MOV	-0x138(%RBP),%R8

  (971) 0x444575 MOV	(%R8,%RDI,8),%RDI

  (971) 0x444579 ADD	%RDI,%RSI

  (971) 0x44457c MOV	-0x58(%RBP),%R8

  (971) 0x444580 MOV	(%R8),%R8

  (971) 0x444583 MOV	-0x140(%RBP),%R9

  (971) 0x44458a MOV	(%R9,%R8,8),%R8

  (971) 0x44458e MOV	%R12,%R11

  (971) 0x444591 MOV	-0xd8(%RBP),%R12

  (971) 0x444598 MOV	-0x148(%RBP),%RAX

  (971) 0x44459f NOP

    (972) 0x4445a0 MOV	(%R8,%RDI,8),%R9

    (972) 0x4445a4 VMOVSD	(%RAX,%RDI,8),%XMM2

    (972) 0x4445a9 VMULSD	(%R12,%RCX,8),%XMM2,%XMM10

    (972) 0x4445af TEST	%R9,%R9

    (972) 0x4445b2 LEA	(%R15,%R9,8),%R10

    (972) 0x4445b6 NOT	%R9

    (972) 0x4445b9 LEA	(%R11,%R9,8),%R9

    (972) 0x4445bd CMOVNS	%R10,%R9

    (972) 0x4445c1 MOV	%R13,%R10

    (972) 0x4445c4 CMOVS	%R14,%R10

    (972) 0x4445c8 MOV	(%R9),%R9

    (972) 0x4445cb VADDSD	(%R10,%R9,8),%XMM10,%XMM2

    (972) 0x4445d1 VMOVSD	%XMM2,(%R10,%R9,8)

    (972) 0x4445d7 VADDSD	%XMM1,%XMM10,%XMM1

    (972) 0x4445db VADDSD	%XMM0,%XMM10,%XMM0

    (972) 0x4445df INC	%RDI

    (972) 0x4445e2 CMP	%RSI,%RDI

    (972) 0x4445e5 JL	4445a0

  (971) 0x4445e7 JMP	444509

0x4445ec NOPL	(%RAX)

  (971) 0x4445f0 MOV	-0x168(%RBP),%RSI

  (971) 0x4445f7 CMPQ	$-0x3,(%RSI,%RDI,8)

  (971) 0x4445fc JE	444506

  (971) 0x444602 CMPQ	$0x1,-0xf0(%RBP)

  (971) 0x44460a MOV	-0xd8(%RBP),%R8

  (971) 0x444611 JE	444500

  (971) 0x444617 MOV	-0x130(%RBP),%RSI

  (971) 0x44461e MOV	(%RSI,%RDI,8),%RSI

  (971) 0x444622 MOV	-0xd0(%RBP),%RDI

  (971) 0x444629 CMP	(%RDI,%R9,8),%RSI

  (971) 0x44462d JE	444500

  (971) 0x444633 JMP	444506

(966) 0x444638 XOR	%ECX,%ECX

(966) 0x44463a ADD	%RDX,%RCX

(966) 0x44463d NOPL	(%RAX)

  (969) 0x444640 VMULSD	(%R14,%RCX,8),%XMM10,%XMM0

  (969) 0x444646 VMOVSD	%XMM0,(%R14,%RCX,8)

  (969) 0x44464c INC	%RCX

  (969) 0x44464f CMP	%RCX,%RAX

  (969) 0x444652 JNE	444640

(966) 0x444654 MOV	-0xb8(%RBP),%RAX

(966) 0x44465b MOV	(%RAX,%R9,8),%RDX

(966) 0x44465f MOV	0x8(%RAX,%R9,8),%RAX

(966) 0x444664 MOV	%RAX,%RSI

(966) 0x444667 SUB	%RDX,%RSI

(966) 0x44466a JLE	443c10

(966) 0x444670 MOV	%RSI,%RCX

(966) 0x444673 AND	$-0x4,%RCX

(966) 0x444677 JE	4446b0

(966) 0x444679 LEA	-0x1(%RCX),%RDI

(966) 0x44467d VBROADCASTSD	%XMM10,%YMM0

(966) 0x444682 LEA	(%R13,%RDX,8),%R8

(966) 0x444687 XOR	%R9D,%R9D

(966) 0x44468a NOPW	(%RAX,%RAX,1)

  (968) 0x444690 VMULPD	(%R8,%R9,8),%YMM0,%YMM1

  (968) 0x444696 VMOVUPD	%YMM1,(%R8,%R9,8)

  (968) 0x44469c ADD	$0x4,%R9

  (968) 0x4446a0 CMP	%RDI,%R9

  (968) 0x4446a3 JBE	444690

(966) 0x4446a5 CMP	%RCX,%RSI

(966) 0x4446a8 JE	443c10

(966) 0x4446ae JMP	4446b2

(966) 0x4446b0 XOR	%ECX,%ECX

(966) 0x4446b2 ADD	%RDX,%RCX

(966) 0x4446b5 NOPW	%CS:(%RAX,%RAX,1)

  (967) 0x4446c0 VMULSD	(%R13,%RCX,8),%XMM10,%XMM0

  (967) 0x4446c7 VMOVSD	%XMM0,(%R13,%RCX,8)

  (967) 0x4446ce INC	%RCX

  (967) 0x4446d1 CMP	%RCX,%RAX

  (967) 0x4446d4 JNE	4446c0

(966) 0x4446d6 JMP	443c10

0x4446db MOV	-0x68(%RBP),%RDI

0x4446df VZEROUPPER

0x4446e2 CALL	4e7390 <hypre_Free>

0x4446e7 MOV	-0x60(%RBP),%RDI

0x4446eb CALL	4e7390 <hypre_Free>

0x4446f0 MOV	%R12,%RDI

0x4446f3 CALL	4e7390 <hypre_Free>

0x4446f8 MOV	%R15,%RDI

0x4446fb ADD	$0x178,%RSP

0x444702 POP	%RBX

0x444703 POP	%R12

0x444705 POP	%R13

0x444707 POP	%R14

0x444709 POP	%R15

0x44470b POP	%RBP

0x44470c JMP	4e7390

0x444711 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Module
►98.37+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○1.63	__kmp_invoke_microtask	libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1747-1754,1760-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 37.17 to 4.50 cycles (8.26x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 37.17 to 6.50 cycles (5.72x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

_intel_fast_memset: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1761
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1763
hypre_CAlloc: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1748
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1751
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1754
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1753
hypre_Free: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1878
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1879
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1880
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1766
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1767

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1768
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1768
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1878

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1768

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 440 bytes. The binary function is storing 376 bytes.

General properties

nb instructions	204
nb uops	223
loop length	991
used x86 registers	15
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	80

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	37.17 cycles
front end	37.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.90	8.80	20.33	20.33	32.00	8.80	8.70	32.00	32.00	32.00	8.80	20.33
cycles	8.90	12.20	20.33	20.33	32.00	8.80	8.70	32.00	32.00	32.00	8.80	20.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

16.00

Cycles summary

Front-end	37.17
Dispatch	32.00
DIV/SQRT	16.00
Overall L1	37.17

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	3%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	6%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	9%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 37.17 cycles. At this rate:

6% of peak load performance is reached (11.84 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (10.12 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 37.17 to 32.00 cycles (1.16x speedup).

ASM code

In the binary file, the address of the function is: 4438d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x178,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,-0x1a0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x158(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x138(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x130(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x128(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x148(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x120(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x198(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x118(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x190(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x110(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x108(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x100(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xf8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xf0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x160(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xe8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x150(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xe0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x140(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x128(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xb8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x118(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x168(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x98(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x138(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x90(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x88(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x80(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x78(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x70(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x68(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x60(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x188(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x180(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x178(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x170(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x108(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TEST %RDI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 443af6 <hypre_BoomerAMGBuildMultipass.extracted.28+0x226>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 4e72c0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 443b01 <hypre_BoomerAMGBuildMultipass.extracted.28+0x231>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 4e72c0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %R12,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 443b0c <hypre_BoomerAMGBuildMultipass.extracted.28+0x23c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 4e72c0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 443b0f <hypre_BoomerAMGBuildMultipass.extracted.28+0x23f>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 443ace <hypre_BoomerAMGBuildMultipass.extracted.28+0x1fe>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %R12,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 443ae4 <hypre_BoomerAMGBuildMultipass.extracted.28+0x214>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV -0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R15,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVG %RAX,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 4e72c0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0xa8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 443b48 <hypre_BoomerAMGBuildMultipass.extracted.28+0x278>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV -0x68(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 4f03c0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 443b63 <hypre_BoomerAMGBuildMultipass.extracted.28+0x293>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV -0x60(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 4f03c0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
CALL 4e8ff0 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4e8fe0 <hypre_NumActiveThreads>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RAX,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x80(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x20,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JE 443b9d <hypre_BoomerAMGBuildMultipass.extracted.28+0x2cd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RCX	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
JMP 443ba4 <hypre_BoomerAMGBuildMultipass.extracted.28+0x2d4>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %R8D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %ECX	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV -0x40(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R9,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DEC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA 0x1(%R9),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RAX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
CMP %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVE %R8,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4446db <hypre_BoomerAMGBuildMultipass.extracted.28+0xe0b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xa0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x38,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x38(%R10),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VXORPD %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R12,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 443c27 <hypre_BoomerAMGBuildMultipass.extracted.28+0x357>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x68(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4e7390 <hypre_Free>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x60(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CALL 4e7390 <hypre_Free>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 4e7390 <hypre_Free>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD $0x178,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 4e7390 <hypre_Free>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1747-1754,1760-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 37.17 to 4.50 cycles (8.26x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

_intel_fast_memset: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1761
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1763
hypre_CAlloc: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1748
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1751
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1754
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1753
hypre_Free: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1878
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1879
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1880
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1766
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1767

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1768
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1768
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1878

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1768

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 440 bytes. The binary function is storing 376 bytes.

General properties

nb instructions	204
nb uops	223
loop length	991
used x86 registers	15
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	80

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	37.17 cycles
front end	37.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.90	8.80	20.33	20.33	32.00	8.80	8.70	32.00	32.00	32.00	8.80	20.33
cycles	8.90	12.20	20.33	20.33	32.00	8.80	8.70	32.00	32.00	32.00	8.80	20.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

16.00

Cycles summary

Front-end	37.17
Dispatch	32.00
DIV/SQRT	16.00
Overall L1	37.17

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	3%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	6%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	9%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 37.17 cycles. At this rate:

6% of peak load performance is reached (11.84 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (10.12 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4438d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x178,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,-0x1a0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x158(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x138(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x130(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x128(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x148(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x120(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x198(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x118(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x190(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x110(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x108(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x100(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xf8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xf0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x160(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xe8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x150(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xe0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x140(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x128(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xb8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x118(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x168(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x98(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x138(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x90(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x88(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x80(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x78(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x70(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x68(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x60(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x188(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x180(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x178(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x170(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x108(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TEST %RDI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 443af6 <hypre_BoomerAMGBuildMultipass.extracted.28+0x226>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 4e72c0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 443b01 <hypre_BoomerAMGBuildMultipass.extracted.28+0x231>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 4e72c0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %R12,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 443b0c <hypre_BoomerAMGBuildMultipass.extracted.28+0x23c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 4e72c0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 443b0f <hypre_BoomerAMGBuildMultipass.extracted.28+0x23f>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 443ace <hypre_BoomerAMGBuildMultipass.extracted.28+0x1fe>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %R12,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 443ae4 <hypre_BoomerAMGBuildMultipass.extracted.28+0x214>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV -0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R15,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVG %RAX,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 4e72c0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0xa8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 443b48 <hypre_BoomerAMGBuildMultipass.extracted.28+0x278>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV -0x68(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 4f03c0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 443b63 <hypre_BoomerAMGBuildMultipass.extracted.28+0x293>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV -0x60(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 4f03c0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
CALL 4e8ff0 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4e8fe0 <hypre_NumActiveThreads>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RAX,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x80(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x20,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JE 443b9d <hypre_BoomerAMGBuildMultipass.extracted.28+0x2cd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RCX	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
JMP 443ba4 <hypre_BoomerAMGBuildMultipass.extracted.28+0x2d4>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %R8D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %ECX	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV -0x40(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R9,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DEC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA 0x1(%R9),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RAX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
CMP %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVE %R8,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4446db <hypre_BoomerAMGBuildMultipass.extracted.28+0xe0b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xa0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x38,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x38(%R10),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VXORPD %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R12,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 443c27 <hypre_BoomerAMGBuildMultipass.extracted.28+0x357>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x68(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4e7390 <hypre_Free>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x60(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CALL 4e7390 <hypre_Free>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 4e7390 <hypre_Free>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD $0x178,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 4e7390 <hypre_Free>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass.extracted.28–	1.40	0.75
▼Loop 966 - par_multi_interp.c:1747-1876 - exec–	0.14	0.06
▼Loop 973 - par_multi_interp.c:1747-1837 - exec–	0.48	0.21
○Loop 977 - par_multi_interp.c:1816-1822 - exec	0.31	0.13
○Loop 976 - par_multi_interp.c:1816-1820 - exec	0.00	0.01
○Loop 975 - par_multi_interp.c:1824-1830 - exec	0.00	0.00
○Loop 974 - par_multi_interp.c:1824-1828 - exec	0.00	0.00
○Loop 979 - par_multi_interp.c:1799-1803 - exec	0.44	0.19
○Loop 983 - par_multi_interp.c:1782-1787 - exec	0.02	0.01
○Loop 969 - par_multi_interp.c:1873-1874 - exec	0.00	0.01
▼Loop 971 - par_multi_interp.c:1836-1867 - exec–	0.00	0.01
○Loop 972 - par_multi_interp.c:1851-1860 - exec	0.00	0.00
○Loop 970 - par_multi_interp.c:1873-1874 - exec	0.00	0.00
○Loop 978 - par_multi_interp.c:1805-1809 - exec	0.00	0.00
○Loop 980 - par_multi_interp.c:1792-1797 - exec	0.00	0.00
○Loop 982 - par_multi_interp.c:1792-1797 - exec	0.00	0.00
○Loop 981 - par_multi_interp.c:1792-1797 - exec	0.00	0.00
○Loop 984 - par_multi_interp.c:1782-1787 - exec	0.00	0.00
○Loop 968 - par_multi_interp.c:1875-1876 - exec	0.00	0.00
○Loop 967 - par_multi_interp.c:1875-1876 - exec	0.00	0.00
○Loop 985 - par_multi_interp.c:1782-1787 - exec	0.00	0.00

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