OV - exec - Loop 996

0x452940 MOV	-0x80(%RBP),%RSI

0x452944 INC	%RSI

0x452947 CMP	-0xc8(%RBP),%RSI

0x45294e JGE	453000

0x452954 MOV	-0x88(%RBP),%RDX

0x45295b MOV	%RSI,-0x80(%RBP)

0x45295f MOV	(%RDX,%RSI,8),%RSI

0x452963 MOV	-0xa8(%RBP),%RDX

0x45296a MOV	(%RDX,%RSI,8),%R8

0x45296e MOV	%RSI,%RDI

0x452971 NOT	%RDI

0x452974 MOV	%RSI,-0x50(%RBP)

0x452978 JMP	452992

  (999) 0x452980 MOV	-0x38(%RBP),%R10

  (999) 0x452984 INC	%R8

  (999) 0x452987 MOV	-0xa8(%RBP),%RDX

  (999) 0x45298e MOV	-0x50(%RBP),%RSI

  (999) 0x452992 CMP	0x8(%RDX,%RSI,8),%R8

  (999) 0x452997 JGE	452d40

  (999) 0x45299d MOV	-0x128(%RBP),%RDX

  (999) 0x4529a4 MOV	(%RDX,%R8,8),%R14

  (999) 0x4529a8 MOV	-0x118(%RBP),%RDX

  (999) 0x4529af CMP	%R10,(%RDX,%R14,8)

  (999) 0x4529b3 JNE	452984

  (999) 0x4529b5 MOV	-0x58(%RBP),%RDX

  (999) 0x4529b9 MOV	0x8(%RDX,%R14,8),%R10

  (999) 0x4529be TEST	%R10,%R10

  (999) 0x4529c1 JLE	452b84

  (999) 0x4529c7 MOV	-0x90(%RBP),%RDX

  (999) 0x4529ce MOV	%R14,-0x30(%RBP)

  (999) 0x4529d2 MOV	(%RDX,%R14,8),%R11

  (999) 0x4529d6 ADD	%R11,%R10

  (999) 0x4529d9 MOV	-0x40(%RBP),%RDX

  (999) 0x4529dd MOV	-0x8(%RDX,%R12,8),%RSI

  (999) 0x4529e2 LEA	0x1(%R11),%RDX

  (999) 0x4529e6 CMP	%RDX,%R10

  (999) 0x4529e9 CMOVLE	%RDX,%R10

  (999) 0x4529ed MOV	%R10,%RDX

  (999) 0x4529f0 SUB	%R11,%RDX

  (999) 0x4529f3 CMP	$0x4,%RDX

  (999) 0x4529f7 MOV	%RDX,-0xd0(%RBP)

  (999) 0x4529fe JAE	452a80

  (999) 0x452a04 MOV	-0xd0(%RBP),%R9

  (999) 0x452a0b MOV	%R9,%RDX

  (999) 0x452a0e AND	$-0x4,%RDX

  (999) 0x452a12 CMP	%R9,%RDX

  (999) 0x452a15 JAE	452b80

  (999) 0x452a1b ADD	%RDX,%R11

  (999) 0x452a1e MOV	-0x30(%RBP),%R14

  (999) 0x452a22 JMP	452a4c

    (1002) 0x452a40 INC	%R11

    (1002) 0x452a43 CMP	%R11,%R10

    (1002) 0x452a46 JE	452b84

    (1002) 0x452a4c MOV	(%RSI,%R11,8),%RDX

    (1002) 0x452a50 CMP	%RDI,(%RBX,%RDX,8)

    (1002) 0x452a54 JE	452a40

    (1002) 0x452a56 MOV	-0x40(%RBP),%R9

    (1002) 0x452a5a MOV	(%R9,%R12,8),%R9

    (1002) 0x452a5e MOV	%RDX,(%R9,%RAX,8)

    (1002) 0x452a62 INC	%RAX

    (1002) 0x452a65 MOV	%RDI,(%RBX,%RDX,8)

    (1002) 0x452a69 JMP	452a40

  (999) 0x452a80 SHR	$0x2,%RDX

  (999) 0x452a84 LEA	0x18(%RSI,%R11,8),%R13

  (999) 0x452a89 JMP	452acd

    (1003) 0x452ac0 ADD	$0x20,%R13

    (1003) 0x452ac4 DEC	%RDX

    (1003) 0x452ac7 JE	452a04

    (1003) 0x452acd MOV	-0x18(%R13),%R14

    (1003) 0x452ad1 CMP	%RDI,(%RBX,%R14,8)

    (1003) 0x452ad5 JNE	452b00

    (1003) 0x452ad7 MOV	-0x10(%R13),%R14

    (1003) 0x452adb CMP	%RDI,(%RBX,%R14,8)

    (1003) 0x452adf JNE	452b1d

    (1003) 0x452ae1 MOV	-0x8(%R13),%R14

    (1003) 0x452ae5 CMP	%RDI,(%RBX,%R14,8)

    (1003) 0x452ae9 JNE	452b3a

    (1003) 0x452aeb MOV	(%R13),%R14

    (1003) 0x452aef CMP	%RDI,(%RBX,%R14,8)

    (1003) 0x452af3 JE	452ac0

    (1003) 0x452af5 JMP	452b5b

    (1003) 0x452b00 MOV	-0x40(%RBP),%R9

    (1003) 0x452b04 MOV	(%R9,%R12,8),%R9

    (1003) 0x452b08 MOV	%R14,(%R9,%RAX,8)

    (1003) 0x452b0c INC	%RAX

    (1003) 0x452b0f MOV	%RDI,(%RBX,%R14,8)

    (1003) 0x452b13 MOV	-0x10(%R13),%R14

    (1003) 0x452b17 CMP	%RDI,(%RBX,%R14,8)

    (1003) 0x452b1b JE	452ae1

    (1003) 0x452b1d MOV	-0x40(%RBP),%R9

    (1003) 0x452b21 MOV	(%R9,%R12,8),%R9

    (1003) 0x452b25 MOV	%R14,(%R9,%RAX,8)

    (1003) 0x452b29 INC	%RAX

    (1003) 0x452b2c MOV	%RDI,(%RBX,%R14,8)

    (1003) 0x452b30 MOV	-0x8(%R13),%R14

    (1003) 0x452b34 CMP	%RDI,(%RBX,%R14,8)

    (1003) 0x452b38 JE	452aeb

    (1003) 0x452b3a MOV	-0x40(%RBP),%R9

    (1003) 0x452b3e MOV	(%R9,%R12,8),%R9

    (1003) 0x452b42 MOV	%R14,(%R9,%RAX,8)

    (1003) 0x452b46 INC	%RAX

    (1003) 0x452b49 MOV	%RDI,(%RBX,%R14,8)

    (1003) 0x452b4d MOV	(%R13),%R14

    (1003) 0x452b51 CMP	%RDI,(%RBX,%R14,8)

    (1003) 0x452b55 JE	452ac0

    (1003) 0x452b5b MOV	-0x40(%RBP),%R9

    (1003) 0x452b5f MOV	(%R9,%R12,8),%R9

    (1003) 0x452b63 MOV	%R14,(%R9,%RAX,8)

    (1003) 0x452b67 INC	%RAX

    (1003) 0x452b6a MOV	%RDI,(%RBX,%R14,8)

    (1003) 0x452b6e JMP	452ac0

  (999) 0x452b80 MOV	-0x30(%RBP),%R14

  (999) 0x452b84 MOV	-0x60(%RBP),%RDX

  (999) 0x452b88 MOV	0x8(%RDX,%R14,8),%R10

  (999) 0x452b8d TEST	%R10,%R10

  (999) 0x452b90 JLE	452980

  (999) 0x452b96 MOV	-0x98(%RBP),%RDX

  (999) 0x452b9d MOV	(%RDX,%R14,8),%R9

  (999) 0x452ba1 ADD	%R9,%R10

  (999) 0x452ba4 MOV	-0x48(%RBP),%RDX

  (999) 0x452ba8 MOV	-0x8(%RDX,%R12,8),%RSI

  (999) 0x452bad LEA	0x1(%R9),%RDX

  (999) 0x452bb1 CMP	%RDX,%R10

  (999) 0x452bb4 CMOVLE	%RDX,%R10

  (999) 0x452bb8 MOV	%R10,%R11

  (999) 0x452bbb SUB	%R9,%R11

  (999) 0x452bbe CMP	$0x4,%R11

  (999) 0x452bc2 MOV	%R11,-0x30(%RBP)

  (999) 0x452bc6 JAE	452c40

  (999) 0x452bc8 MOV	-0x30(%RBP),%RDX

  (999) 0x452bcc MOV	%RDX,%R11

  (999) 0x452bcf AND	$-0x4,%R11

  (999) 0x452bd3 CMP	%RDX,%R11

  (999) 0x452bd6 JAE	452980

  (999) 0x452bdc ADD	%R11,%R9

  (999) 0x452bdf JMP	452c0c

    (1000) 0x452c00 INC	%R9

    (1000) 0x452c03 CMP	%R9,%R10

    (1000) 0x452c06 JE	452980

    (1000) 0x452c0c MOV	(%RSI,%R9,8),%RDX

    (1000) 0x452c10 CMP	%RDI,(%R15,%RDX,8)

    (1000) 0x452c14 JE	452c00

    (1000) 0x452c16 MOV	-0x48(%RBP),%R11

    (1000) 0x452c1a MOV	(%R11,%R12,8),%R11

    (1000) 0x452c1e MOV	%RDX,(%R11,%RCX,8)

    (1000) 0x452c22 INC	%RCX

    (1000) 0x452c25 MOV	%RDI,(%R15,%RDX,8)

    (1000) 0x452c29 JMP	452c00

  (999) 0x452c40 SHR	$0x2,%R11

  (999) 0x452c44 LEA	0x18(%RSI,%R9,8),%R14

  (999) 0x452c49 JMP	452c8d

    (1001) 0x452c80 ADD	$0x20,%R14

    (1001) 0x452c84 DEC	%R11

    (1001) 0x452c87 JE	452bc8

    (1001) 0x452c8d MOV	-0x18(%R14),%R13

    (1001) 0x452c91 CMP	%RDI,(%R15,%R13,8)

    (1001) 0x452c95 JNE	452cc0

    (1001) 0x452c97 MOV	-0x10(%R14),%R13

    (1001) 0x452c9b CMP	%RDI,(%R15,%R13,8)

    (1001) 0x452c9f JNE	452cdd

    (1001) 0x452ca1 MOV	-0x8(%R14),%R13

    (1001) 0x452ca5 CMP	%RDI,(%R15,%R13,8)

    (1001) 0x452ca9 JNE	452cfa

    (1001) 0x452cab MOV	(%R14),%R13

    (1001) 0x452cae CMP	%RDI,(%R15,%R13,8)

    (1001) 0x452cb2 JE	452c80

    (1001) 0x452cb4 JMP	452d1a

    (1001) 0x452cc0 MOV	-0x48(%RBP),%RDX

    (1001) 0x452cc4 MOV	(%RDX,%R12,8),%RDX

    (1001) 0x452cc8 MOV	%R13,(%RDX,%RCX,8)

    (1001) 0x452ccc INC	%RCX

    (1001) 0x452ccf MOV	%RDI,(%R15,%R13,8)

    (1001) 0x452cd3 MOV	-0x10(%R14),%R13

    (1001) 0x452cd7 CMP	%RDI,(%R15,%R13,8)

    (1001) 0x452cdb JE	452ca1

    (1001) 0x452cdd MOV	-0x48(%RBP),%RDX

    (1001) 0x452ce1 MOV	(%RDX,%R12,8),%RDX

    (1001) 0x452ce5 MOV	%R13,(%RDX,%RCX,8)

    (1001) 0x452ce9 INC	%RCX

    (1001) 0x452cec MOV	%RDI,(%R15,%R13,8)

    (1001) 0x452cf0 MOV	-0x8(%R14),%R13

    (1001) 0x452cf4 CMP	%RDI,(%R15,%R13,8)

    (1001) 0x452cf8 JE	452cab

    (1001) 0x452cfa MOV	-0x48(%RBP),%RDX

    (1001) 0x452cfe MOV	(%RDX,%R12,8),%RDX

    (1001) 0x452d02 MOV	%R13,(%RDX,%RCX,8)

    (1001) 0x452d06 INC	%RCX

    (1001) 0x452d09 MOV	%RDI,(%R15,%R13,8)

    (1001) 0x452d0d MOV	(%R14),%R13

    (1001) 0x452d10 CMP	%RDI,(%R15,%R13,8)

    (1001) 0x452d14 JE	452c80

    (1001) 0x452d1a MOV	-0x48(%RBP),%RDX

    (1001) 0x452d1e MOV	(%RDX,%R12,8),%RDX

    (1001) 0x452d22 MOV	%R13,(%RDX,%RCX,8)

    (1001) 0x452d26 INC	%RCX

    (1001) 0x452d29 MOV	%RDI,(%R15,%R13,8)

    (1001) 0x452d2d JMP	452c80

0x452d40 MOV	-0xa0(%RBP),%RDX

0x452d47 MOV	-0x50(%RBP),%RSI

0x452d4b MOV	(%RDX,%RSI,8),%R8

0x452d4f MOV	0x8(%RDX,%RSI,8),%RDX

0x452d54 CMP	%RDX,%R8

0x452d57 JL	452d8c

0x452d59 JMP	452940

  (997) 0x452d80 INC	%R8

  (997) 0x452d83 CMP	%RDX,%R8

  (997) 0x452d86 JGE	452940

  (997) 0x452d8c MOV	-0x130(%RBP),%RSI

  (997) 0x452d93 MOV	(%RSI,%R8,8),%R9

  (997) 0x452d97 MOV	-0x120(%RBP),%RSI

  (997) 0x452d9e CMP	%R10,(%RSI,%R9,8)

  (997) 0x452da2 JNE	452d80

  (997) 0x452da4 MOV	-0x110(%RBP),%RSI

  (997) 0x452dab MOV	0x8(%RSI,%R9,8),%RSI

  (997) 0x452db0 TEST	%RSI,%RSI

  (997) 0x452db3 JLE	452d80

  (997) 0x452db5 MOV	-0x100(%RBP),%RDX

  (997) 0x452dbc MOV	(%RDX,%R9,8),%R9

  (997) 0x452dc0 ADD	%R9,%RSI

  (997) 0x452dc3 MOV	-0x108(%RBP),%RDX

  (997) 0x452dca MOV	(%RDX,%R12,8),%R11

  (997) 0x452dce LEA	0x1(%R9),%R10

  (997) 0x452dd2 CMP	%R10,%RSI

  (997) 0x452dd5 CMOVLE	%R10,%RSI

  (997) 0x452dd9 MOV	%RSI,%RDX

  (997) 0x452ddc SUB	%R9,%RDX

  (997) 0x452ddf CMP	%R10,%RSI

  (997) 0x452de2 MOV	%R11,-0x30(%RBP)

  (997) 0x452de6 JNE	452e40

  (997) 0x452de8 XOR	%R11D,%R11D

  (997) 0x452deb TEST	$0x1,%DL

  (997) 0x452dee MOV	-0x38(%RBP),%R10

  (997) 0x452df2 JE	452fa0

  (997) 0x452df8 ADD	%R11,%R9

  (997) 0x452dfb MOV	-0x30(%RBP),%RDX

  (997) 0x452dff MOV	(%RDX,%R9,8),%RDX

  (997) 0x452e03 TEST	%RDX,%RDX

  (997) 0x452e06 JS	452f80

  (997) 0x452e0c CMP	%RDI,(%R15,%RDX,8)

  (997) 0x452e10 JE	452fa0

  (997) 0x452e16 MOV	-0x48(%RBP),%RSI

  (997) 0x452e1a MOV	(%RSI,%R12,8),%RSI

  (997) 0x452e1e MOV	%RDX,(%RSI,%RCX,8)

  (997) 0x452e22 INC	%RCX

  (997) 0x452e25 MOV	%RDI,(%R15,%RDX,8)

  (997) 0x452e29 JMP	452fa0

  (997) 0x452e40 MOV	%RDX,%RSI

  (997) 0x452e43 AND	$-0x2,%RSI

  (997) 0x452e47 LEA	0x8(%R11,%R9,8),%R10

  (997) 0x452e4c XOR	%R11D,%R11D

  (997) 0x452e4f JMP	452e8d

    (998) 0x452e80 ADD	$0x2,%R11

    (998) 0x452e84 CMP	%R11,%RSI

    (998) 0x452e87 JE	452deb

    (998) 0x452e8d MOV	-0x8(%R10,%R11,8),%R14

    (998) 0x452e92 TEST	%R14,%R14

    (998) 0x452e95 JS	452ec0

    (998) 0x452e97 CMP	%RDI,(%R15,%R14,8)

    (998) 0x452e9b JE	452ee0

    (998) 0x452e9d MOV	-0x48(%RBP),%R13

    (998) 0x452ea1 MOV	(%R13,%R12,8),%R13

    (998) 0x452ea6 MOV	%R14,(%R13,%RCX,8)

    (998) 0x452eab INC	%RCX

    (998) 0x452eae MOV	%RDI,(%R15,%R14,8)

    (998) 0x452eb2 JMP	452ee0

    (998) 0x452ec0 NOT	%R14

    (998) 0x452ec3 CMP	%RDI,(%RBX,%R14,8)

    (998) 0x452ec7 JE	452ee0

    (998) 0x452ec9 MOV	-0x40(%RBP),%R13

    (998) 0x452ecd MOV	(%R13,%R12,8),%R13

    (998) 0x452ed2 MOV	%R14,(%R13,%RAX,8)

    (998) 0x452ed7 INC	%RAX

    (998) 0x452eda MOV	%RDI,(%RBX,%R14,8)

    (998) 0x452ede XCHG	%AX,%AX

    (998) 0x452ee0 MOV	(%R10,%R11,8),%R14

    (998) 0x452ee4 TEST	%R14,%R14

    (998) 0x452ee7 JS	452f40

    (998) 0x452ee9 CMP	%RDI,(%R15,%R14,8)

    (998) 0x452eed JE	452e80

    (998) 0x452eef MOV	-0x48(%RBP),%R13

    (998) 0x452ef3 MOV	(%R13,%R12,8),%R13

    (998) 0x452ef8 MOV	%R14,(%R13,%RCX,8)

    (998) 0x452efd INC	%RCX

    (998) 0x452f00 MOV	%RDI,(%R15,%R14,8)

    (998) 0x452f04 JMP	452e80

    (998) 0x452f40 NOT	%R14

    (998) 0x452f43 CMP	%RDI,(%RBX,%R14,8)

    (998) 0x452f47 JE	452e80

    (998) 0x452f4d MOV	-0x40(%RBP),%R13

    (998) 0x452f51 MOV	(%R13,%R12,8),%R13

    (998) 0x452f56 MOV	%R14,(%R13,%RAX,8)

    (998) 0x452f5b INC	%RAX

    (998) 0x452f5e MOV	%RDI,(%RBX,%R14,8)

    (998) 0x452f62 JMP	452e80

  (997) 0x452f80 NOT	%RDX

  (997) 0x452f83 CMP	%RDI,(%RBX,%RDX,8)

  (997) 0x452f87 JE	452fa0

  (997) 0x452f89 MOV	-0x40(%RBP),%RSI

  (997) 0x452f8d MOV	(%RSI,%R12,8),%RSI

  (997) 0x452f91 MOV	%RDX,(%RSI,%RAX,8)

  (997) 0x452f95 INC	%RAX

  (997) 0x452f98 MOV	%RDI,(%RBX,%RDX,8)

  (997) 0x452f9c NOPL	(%RAX)

  (997) 0x452fa0 MOV	-0xa0(%RBP),%RDX

  (997) 0x452fa7 MOV	-0x50(%RBP),%RSI

  (997) 0x452fab MOV	0x8(%RDX,%RSI,8),%RDX

  (997) 0x452fb0 INC	%R8

  (997) 0x452fb3 CMP	%RDX,%R8

  (997) 0x452fb6 JL	452d8c

0x452fbc JMP	452940

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 917 - 1125

--------------------------------------------------------------------------------

917:           for (i=0; i < n_coarse; i++)

[...]

1072:           for (i=thread_start; i < thread_stop; i++)

1073:           {

1074:              i1 = pass_array[i];

1075:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1076:              {

1077:                 j1 = S_diag_j[j];

1078:                 if (assigned[j1] == pass-1)

1079:                 {

1080:                    j_start = P_diag_start[j1];

1081:                    j_end = j_start+P_diag_i[j1+1];

1082:                    for (k=j_start; k < j_end; k++)

1083:                    {

1084:                       k1 = P_diag_pass[pass-1][k];

1085:                       if (P_marker[k1] != -i1-1)

1086:                       {

1087:                           P_diag_pass[pass][cnt_nz++] = k1;

1088:                           P_marker[k1] = -i1-1;

1089:                       }

1090:                    }

1091:                    j_start = P_offd_start[j1];

1092:                    j_end = j_start+P_offd_i[j1+1];

1093:                    for (k=j_start; k < j_end; k++)

1094:                    {

1095:                       k1 = P_offd_pass[pass-1][k];

1096:                       if (P_marker_offd[k1] != -i1-1)

1097:                       {

1098:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1099:                          P_marker_offd[k1] = -i1-1;

1100:                       }

1101:                    }

1102:                 }

1103:              }

1104:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1105:              {

1106:                 j1 = S_offd_j[j];

1107:                 if (assigned_offd[j1] == pass-1)

1108:                 {

1109:                    j_start = Pext_start[j1];

1110:                    j_end = j_start+Pext_i[j1+1];

1111:                    for (k=j_start; k < j_end; k++)

1112:                    {

1113:                       k1 = Pext_pass[pass][k];

1114:                       if (k1 < 0)

1115:                       {

1116:                          if (P_marker[-k1-1] != -i1-1)

1117:                          {

1118:                             P_diag_pass[pass][cnt_nz++] = -k1-1;

1119:                             P_marker[-k1-1] = -i1-1;

1120:                          }

1121:                       }

1122:                       else if (P_marker_offd[k1] != -i1-1)

1123:                       {

1124:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1125:                          P_marker_offd[k1] = -i1-1;

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass.extracted.34
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1078-1078,par_multi_interp.c:1099-1099,par_multi_interp.c:1104-1104
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.50
CQA cycles if no scalar integer	3.50
CQA cycles if FP arith vectorized	3.50
CQA cycles if fully vectorized	0.44
Front-end cycles	3.50
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	3.33
P3 cycles	3.33
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	1.00
P11 cycles	3.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	10.00
Nb stores	2.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.43
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass.extracted.34
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1078-1078,par_multi_interp.c:1099-1099,par_multi_interp.c:1104-1104
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.50
CQA cycles if no scalar integer	3.50
CQA cycles if FP arith vectorized	3.50
CQA cycles if fully vectorized	0.44
Front-end cycles	3.50
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	3.33
P3 cycles	3.33
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	1.00
P11 cycles	3.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	10.00
Nb stores	2.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.43
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass.extracted.34
Source file and lines	par_multi_interp.c:917-1125
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:917,1072-1125.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1075,1078,1099,1104.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 2793 paths individually, rerun with max-paths=2793
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 2793 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.50 to 0.44 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 80 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	21
nb uops	21
loop length	93
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.00	1.00	3.33	3.33	1.00	1.00	1.00	1.00	1.00	1.00	1.00	3.33
cycles	1.00	1.00	3.33	3.33	1.00	1.00	1.00	1.00	1.00	1.00	1.00	3.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.50
Dispatch	3.33
Overall L1	3.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.50 cycles. At this rate:

11% of peak load performance is reached (22.86 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.57 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.50 to 3.33 cycles (1.05x speedup).

ASM code

In the binary file, the address of the loop is: 452954

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x80(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP -0xc8(%RBP),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 453000 <hypre_BoomerAMGBuildMultipass.extracted.34+0x13e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x88(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDX,%RSI,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xa8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RSI,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
NOT %RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RSI,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 452992 <hypre_BoomerAMGBuildMultipass.extracted.34+0xd72>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0xa0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RSI,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RDX,%RSI,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JL 452d8c <hypre_BoomerAMGBuildMultipass.extracted.34+0x116c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 452940 <hypre_BoomerAMGBuildMultipass.extracted.34+0xd20>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 452940 <hypre_BoomerAMGBuildMultipass.extracted.34+0xd20>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	hypre_BoomerAMGBuildMultipass.extracted.34
Source file and lines	par_multi_interp.c:917-1125
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:917,1072-1125.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1075,1078,1099,1104.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 2793 paths individually, rerun with max-paths=2793
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 2793 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.50 to 0.44 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 80 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	21
nb uops	21
loop length	93
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.00	1.00	3.33	3.33	1.00	1.00	1.00	1.00	1.00	1.00	1.00	3.33
cycles	1.00	1.00	3.33	3.33	1.00	1.00	1.00	1.00	1.00	1.00	1.00	3.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.50
Dispatch	3.33
Overall L1	3.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.50 cycles. At this rate:

11% of peak load performance is reached (22.86 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.57 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.50 to 3.33 cycles (1.05x speedup).

ASM code

In the binary file, the address of the loop is: 452954

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x80(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP -0xc8(%RBP),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 453000 <hypre_BoomerAMGBuildMultipass.extracted.34+0x13e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x88(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDX,%RSI,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xa8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RSI,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
NOT %RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RSI,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 452992 <hypre_BoomerAMGBuildMultipass.extracted.34+0xd72>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0xa0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RSI,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RDX,%RSI,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JL 452d8c <hypre_BoomerAMGBuildMultipass.extracted.34+0x116c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 452940 <hypre_BoomerAMGBuildMultipass.extracted.34+0xd20>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 452940 <hypre_BoomerAMGBuildMultipass.extracted.34+0xd20>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code