OV - exec - Loop 981

	Loop Id: 981	Module: exec	Source: par_multi_interp.c:1747-1837 [...]	Coverage: 0.48%

0x451380 MOV	-0x58(%RBP),%RAX

0x451384 MOV	-0x30(%RBP),%R9

0x451388 INC	%RDX

0x45138b CMP	%R11,%RDX

0x45138e JE	451780

0x451394 MOV	-0x158(%RBP),%RSI

0x45139b MOV	(%RSI,%RDX,8),%RSI

0x45139f MOV	-0x70(%RBP),%RDI

0x4513a3 CMP	%R9,(%RDI,%RSI,8)

0x4513a7 JNE	451400

0x4513a9 MOV	-0x98(%RBP),%R8

0x4513b0 MOV	(%R8,%RSI,8),%RDI

0x4513b4 MOV	0x8(%R8,%RSI,8),%R8

0x4513b9 MOV	%R8,%R9

0x4513bc SUB	%RDI,%R9

0x4513bf JLE	451588

0x4513c5 CMP	$0x4,%R9

0x4513c9 JAE	451440

0x4513cb JMP	451519

0x451400 MOV	-0x140(%RBP),%RDI

0x451407 CMPQ	$-0x3,(%RDI,%RSI,8)

0x45140c JE	451388

0x451412 CMPQ	$0x1,-0xc8(%RBP)

0x45141a JE	451431

0x45141c MOV	-0xa8(%RBP),%R8

0x451423 MOV	(%R8,%R9,8),%RDI

0x451427 CMP	(%R8,%RSI,8),%RDI

0x45142b JNE	451388

0x451431 VADDSD	(%RBX,%RDX,8),%XMM0,%XMM0

0x451436 JMP	451388

0x451440 MOV	%R9,%R10

0x451443 SHR	$0x2,%R10

0x451447 LEA	0x18(,%RDI,8),%R11

0x45144f MOV	%R12,%RCX

0x451452 NOPW	%CS:(%RAX,%RAX,1)

  (984) 0x451460 MOV	-0x18(%RAX,%R11,1),%R12

  (984) 0x451465 VMOVSD	-0x18(%R14,%R11,1),%XMM2

  (984) 0x45146c VMOVSD	(%RBX,%RDX,8),%XMM3

  (984) 0x451471 MOV	(%RCX,%R12,8),%R12

  (984) 0x451475 VMOVSD	(%R14,%R12,8),%XMM4

  (984) 0x45147b VFMADD231SD	%XMM2,%XMM3,%XMM4

  (984) 0x451480 VMOVSD	%XMM4,(%R14,%R12,8)

  (984) 0x451486 MOV	-0x10(%RAX,%R11,1),%R12

  (984) 0x45148b VMOVSD	-0x10(%R14,%R11,1),%XMM4

  (984) 0x451492 VMOVSD	(%RBX,%RDX,8),%XMM5

  (984) 0x451497 MOV	(%RCX,%R12,8),%R12

  (984) 0x45149b VMOVSD	(%R14,%R12,8),%XMM6

  (984) 0x4514a1 VFMADD231SD	%XMM4,%XMM5,%XMM6

  (984) 0x4514a6 VMOVSD	%XMM6,(%R14,%R12,8)

  (984) 0x4514ac MOV	-0x8(%RAX,%R11,1),%R12

  (984) 0x4514b1 VMOVSD	-0x8(%R14,%R11,1),%XMM6

  (984) 0x4514b8 VMOVSD	(%RBX,%RDX,8),%XMM7

  (984) 0x4514bd MOV	(%RCX,%R12,8),%R12

  (984) 0x4514c1 VMOVSD	(%R14,%R12,8),%XMM8

  (984) 0x4514c7 VFMADD231SD	%XMM6,%XMM7,%XMM8

  (984) 0x4514cc VMOVSD	%XMM8,(%R14,%R12,8)

  (984) 0x4514d2 VMOVSD	(%R14,%R11,1),%XMM8

  (984) 0x4514d8 VMULSD	(%RBX,%RDX,8),%XMM8,%XMM18

  (984) 0x4514df MOV	(%RAX,%R11,1),%R12

  (984) 0x4514e3 MOV	(%RCX,%R12,8),%R12

  (984) 0x4514e7 VADDSD	(%R14,%R12,8),%XMM18,%XMM8

  (984) 0x4514ee VMOVSD	%XMM8,(%R14,%R12,8)

  (984) 0x4514f4 VFMADD213SD	%XMM18,%XMM5,%XMM4

  (984) 0x4514fa VFMADD231SD	%XMM2,%XMM3,%XMM4

  (984) 0x4514ff VFMADD231SD	%XMM6,%XMM7,%XMM4

  (984) 0x451504 VADDSD	%XMM1,%XMM4,%XMM1

  (984) 0x451508 VADDSD	%XMM0,%XMM4,%XMM0

  (984) 0x45150c ADD	$0x20,%R11

  (984) 0x451510 DEC	%R10

  (984) 0x451513 JNE	451460

0x451519 MOV	%R9,%R10

0x45151c AND	$-0x4,%R10

0x451520 CMP	%R9,%R10

0x451523 MOV	-0x38(%RBP),%R11

0x451527 JAE	451580

0x451529 ADD	%R10,%RDI

0x45152c MOV	-0x40(%RBP),%R10

0x451530 MOV	-0x50(%RBP),%R12

0x451534 NOPW	%CS:(%RAX,%RAX,1)

  (985) 0x451540 MOV	(%RAX,%RDI,8),%R9

  (985) 0x451544 VMOVSD	(%R14,%RDI,8),%XMM2

  (985) 0x45154a VMULSD	(%RBX,%RDX,8),%XMM2,%XMM18

  (985) 0x451551 MOV	(%R12,%R9,8),%R9

  (985) 0x451555 VADDSD	(%R14,%R9,8),%XMM18,%XMM2

  (985) 0x45155c VMOVSD	%XMM2,(%R14,%R9,8)

  (985) 0x451562 VADDSD	%XMM1,%XMM18,%XMM1

  (985) 0x451568 VADDSD	%XMM0,%XMM18,%XMM0

  (985) 0x45156e INC	%RDI

  (985) 0x451571 CMP	%RDI,%R8

  (985) 0x451574 JNE	451540

0x451576 JMP	451588

0x451580 MOV	-0x40(%RBP),%R10

0x451584 MOV	-0x50(%RBP),%R12

0x451588 MOV	-0xa0(%RBP),%RAX

0x45158f MOV	(%RAX,%RSI,8),%RDI

0x451593 MOV	0x8(%RAX,%RSI,8),%RSI

0x451598 MOV	%RSI,%R8

0x45159b SUB	%RDI,%R8

0x45159e JLE	451380

0x4515a4 CMP	$0x4,%R8

0x4515a8 JAE	4515c0

0x4515aa JMP	4516a2

0x4515c0 MOV	%R8,%R9

0x4515c3 SHR	$0x2,%R9

0x4515c7 MOV	%R10,%RAX

0x4515ca LEA	0x18(,%RDI,8),%R10

0x4515d2 NOPW	%CS:(%RAX,%RAX,1)

  (982) 0x4515e0 MOV	-0x18(%RAX,%R10,1),%R11

  (982) 0x4515e5 VMOVSD	-0x18(%R13,%R10,1),%XMM2

  (982) 0x4515ec VMOVSD	(%RBX,%RDX,8),%XMM3

  (982) 0x4515f1 MOV	(%R15,%R11,8),%R11

  (982) 0x4515f5 VMOVSD	(%R13,%R11,8),%XMM4

  (982) 0x4515fc VFMADD231SD	%XMM2,%XMM3,%XMM4

  (982) 0x451601 VMOVSD	%XMM4,(%R13,%R11,8)

  (982) 0x451608 MOV	-0x10(%RAX,%R10,1),%R11

  (982) 0x45160d VMOVSD	-0x10(%R13,%R10,1),%XMM4

  (982) 0x451614 VMOVSD	(%RBX,%RDX,8),%XMM5

  (982) 0x451619 MOV	(%R15,%R11,8),%R11

  (982) 0x45161d VMOVSD	(%R13,%R11,8),%XMM6

  (982) 0x451624 VFMADD231SD	%XMM4,%XMM5,%XMM6

  (982) 0x451629 VMOVSD	%XMM6,(%R13,%R11,8)

  (982) 0x451630 MOV	-0x8(%RAX,%R10,1),%R11

  (982) 0x451635 VMOVSD	-0x8(%R13,%R10,1),%XMM6

  (982) 0x45163c VMOVSD	(%RBX,%RDX,8),%XMM7

  (982) 0x451641 MOV	(%R15,%R11,8),%R11

  (982) 0x451645 VMOVSD	(%R13,%R11,8),%XMM8

  (982) 0x45164c VFMADD231SD	%XMM6,%XMM7,%XMM8

  (982) 0x451651 VMOVSD	%XMM8,(%R13,%R11,8)

  (982) 0x451658 VMOVSD	(%R13,%R10,1),%XMM8

  (982) 0x45165f VMULSD	(%RBX,%RDX,8),%XMM8,%XMM18

  (982) 0x451666 MOV	(%RAX,%R10,1),%R11

  (982) 0x45166a MOV	(%R15,%R11,8),%R11

  (982) 0x45166e VADDSD	(%R13,%R11,8),%XMM18,%XMM8

  (982) 0x451676 VMOVSD	%XMM8,(%R13,%R11,8)

  (982) 0x45167d VFMADD213SD	%XMM18,%XMM5,%XMM4

  (982) 0x451683 VFMADD231SD	%XMM2,%XMM3,%XMM4

  (982) 0x451688 VFMADD231SD	%XMM6,%XMM7,%XMM4

  (982) 0x45168d VADDSD	%XMM1,%XMM4,%XMM1

  (982) 0x451691 VADDSD	%XMM0,%XMM4,%XMM0

  (982) 0x451695 ADD	$0x20,%R10

  (982) 0x451699 DEC	%R9

  (982) 0x45169c JNE	4515e0

0x4516a2 MOV	%R8,%R9

0x4516a5 AND	$-0x4,%R9

0x4516a9 CMP	%R8,%R9

0x4516ac JAE	451740

0x4516b2 ADD	%R9,%RDI

0x4516b5 MOV	-0x40(%RBP),%R10

0x4516b9 MOV	-0x58(%RBP),%RAX

0x4516bd MOV	-0x30(%RBP),%R9

0x4516c1 MOV	-0x38(%RBP),%R11

0x4516c5 NOPW	%CS:(%RAX,%RAX,1)

  (983) 0x4516d0 MOV	(%R10,%RDI,8),%R8

  (983) 0x4516d4 VMOVSD	(%R13,%RDI,8),%XMM2

  (983) 0x4516db VMULSD	(%RBX,%RDX,8),%XMM2,%XMM18

  (983) 0x4516e2 MOV	(%R15,%R8,8),%R8

  (983) 0x4516e6 VADDSD	(%R13,%R8,8),%XMM18,%XMM2

  (983) 0x4516ee VMOVSD	%XMM2,(%R13,%R8,8)

  (983) 0x4516f5 VADDSD	%XMM1,%XMM18,%XMM1

  (983) 0x4516fb VADDSD	%XMM0,%XMM18,%XMM0

  (983) 0x451701 INC	%RDI

  (983) 0x451704 CMP	%RDI,%RSI

  (983) 0x451707 JNE	4516d0

0x451709 JMP	451388

0x451740 MOV	-0x40(%RBP),%R10

0x451744 MOV	-0x58(%RBP),%RAX

0x451748 MOV	-0x30(%RBP),%R9

0x45174c MOV	-0x38(%RBP),%R11

0x451750 JMP	451388

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1747 - 1837

--------------------------------------------------------------------------------

1747:              if (n_fine)

[...]

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

Coverage (%)	Name	Source Location	Module
►99.60+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	2.22
CQA speedup if FP arith vectorized	2.46
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass.extracted.28
Source	par_multi_interp.c:1747-1747,par_multi_interp.c:1811-1816,par_multi_interp.c:1824-1824,par_multi_interp.c:1835-1837
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.33
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	5.42
CQA cycles if fully vectorized	1.67
Front-end cycles	13.33
P0 cycles	6.50
P1 cycles	5.30
P2 cycles	10.67
P3 cycles	10.67
P4 cycles	0.00
P5 cycles	5.30
P6 cycles	6.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	5.40
P11 cycles	10.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	77.00
Nb uops	77.00
Nb loads	32.00
Nb stores	0.00
Nb stack references	12.00
FLOP/cycle	0.08
Nb FLOP add-sub	1.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.20
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	2.22
CQA speedup if FP arith vectorized	2.46
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass.extracted.28
Source	par_multi_interp.c:1747-1747,par_multi_interp.c:1811-1816,par_multi_interp.c:1824-1824,par_multi_interp.c:1835-1837
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.33
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	5.42
CQA cycles if fully vectorized	1.67
Front-end cycles	13.33
P0 cycles	6.50
P1 cycles	5.30
P2 cycles	10.67
P3 cycles	10.67
P4 cycles	0.00
P5 cycles	5.30
P6 cycles	6.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	5.40
P11 cycles	10.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	77.00
Nb uops	77.00
Nb loads	32.00
Nb stores	0.00
Nb stack references	12.00
FLOP/cycle	0.08
Nb FLOP add-sub	1.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.20
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass.extracted.28
Source file and lines	par_multi_interp.c:1747-1837
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1747,1811-1837.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1747,1811-1816,1824,1835-1837.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=29
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 29 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.33 to 6.00 cycles (2.22x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 13.33 to 1.67 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary loop is loading 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	77
nb uops	77
loop length	363
used x86 registers	12
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.33 cycles
front end	13.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.50	5.30	10.67	10.67	0.00	5.30	6.50	0.00	0.00	0.00	5.40	10.67
cycles	6.50	5.30	10.67	10.67	0.00	5.30	6.50	0.00	0.00	0.00	5.40	10.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.33
Dispatch	10.67
Overall L1	13.33

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.33 cycles. At this rate:

10% of peak load performance is reached (19.20 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 13.33 to 10.67 cycles (1.25x speedup).

ASM code

In the binary file, the address of the loop is: 451394

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JE 451780 <hypre_BoomerAMGBuildMultipass.extracted.28+0xcd0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x158(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RSI,%RDX,8),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP %R9,(%RDI,%RSI,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JNE 451400 <hypre_BoomerAMGBuildMultipass.extracted.28+0x950>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x98(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%R8,%RSI,8),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R8,%RSI,8),%R8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RDI,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JLE 451588 <hypre_BoomerAMGBuildMultipass.extracted.28+0xad8>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP $0x4,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JAE 451440 <hypre_BoomerAMGBuildMultipass.extracted.28+0x990>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
JMP 451519 <hypre_BoomerAMGBuildMultipass.extracted.28+0xa69>	1	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0x140(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMPQ $-0x3,(%RDI,%RSI,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JE 451388 <hypre_BoomerAMGBuildMultipass.extracted.28+0x8d8>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMPQ $0x1,-0xc8(%RBP)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JE 451431 <hypre_BoomerAMGBuildMultipass.extracted.28+0x981>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0xa8(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%R8,%R9,8),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP (%R8,%RSI,8),%RDI	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JNE 451388 <hypre_BoomerAMGBuildMultipass.extracted.28+0x8d8>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VADDSD (%RBX,%RDX,8),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	scal (12.5%)
JMP 451388 <hypre_BoomerAMGBuildMultipass.extracted.28+0x8d8>	1	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %R9,%R10	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x2,%R10	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
LEA 0x18(,%RDI,8),%R11	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RCX	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,%R10	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x4,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	scal (12.5%)
CMP %R9,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
JAE 451580 <hypre_BoomerAMGBuildMultipass.extracted.28+0xad0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
ADD %R10,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV -0x40(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x50(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 451588 <hypre_BoomerAMGBuildMultipass.extracted.28+0xad8>	1	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0x40(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x50(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xa0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%RSI,8),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX,%RSI,8),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RDI,%R8	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JLE 451380 <hypre_BoomerAMGBuildMultipass.extracted.28+0x8d0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP $0x4,%R8	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JAE 4515c0 <hypre_BoomerAMGBuildMultipass.extracted.28+0xb10>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
JMP 4516a2 <hypre_BoomerAMGBuildMultipass.extracted.28+0xbf2>	1	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x2,%R9	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
MOV %R10,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x18(,%RDI,8),%R10	1	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
CMP %R8,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JAE 451740 <hypre_BoomerAMGBuildMultipass.extracted.28+0xc90>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
ADD %R9,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV -0x40(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 451388 <hypre_BoomerAMGBuildMultipass.extracted.28+0x8d8>	1	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0x40(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 451388 <hypre_BoomerAMGBuildMultipass.extracted.28+0x8d8>	1	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	hypre_BoomerAMGBuildMultipass.extracted.28
Source file and lines	par_multi_interp.c:1747-1837
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=29
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.33 to 6.00 cycles (2.22x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 13.33 to 1.67 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary loop is loading 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	77
nb uops	77
loop length	363
used x86 registers	12
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.33 cycles
front end	13.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.50	5.30	10.67	10.67	0.00	5.30	6.50	0.00	0.00	0.00	5.40	10.67
cycles	6.50	5.30	10.67	10.67	0.00	5.30	6.50	0.00	0.00	0.00	5.40	10.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.33
Dispatch	10.67
Overall L1	13.33

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.33 cycles. At this rate:

10% of peak load performance is reached (19.20 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 451394

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JE 451780 <hypre_BoomerAMGBuildMultipass.extracted.28+0xcd0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x158(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RSI,%RDX,8),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP %R9,(%RDI,%RSI,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JNE 451400 <hypre_BoomerAMGBuildMultipass.extracted.28+0x950>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x98(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%R8,%RSI,8),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R8,%RSI,8),%R8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RDI,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JLE 451588 <hypre_BoomerAMGBuildMultipass.extracted.28+0xad8>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP $0x4,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JAE 451440 <hypre_BoomerAMGBuildMultipass.extracted.28+0x990>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
JMP 451519 <hypre_BoomerAMGBuildMultipass.extracted.28+0xa69>	1	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0x140(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMPQ $-0x3,(%RDI,%RSI,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JE 451388 <hypre_BoomerAMGBuildMultipass.extracted.28+0x8d8>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMPQ $0x1,-0xc8(%RBP)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JE 451431 <hypre_BoomerAMGBuildMultipass.extracted.28+0x981>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0xa8(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%R8,%R9,8),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP (%R8,%RSI,8),%RDI	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JNE 451388 <hypre_BoomerAMGBuildMultipass.extracted.28+0x8d8>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VADDSD (%RBX,%RDX,8),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	scal (12.5%)
JMP 451388 <hypre_BoomerAMGBuildMultipass.extracted.28+0x8d8>	1	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %R9,%R10	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x2,%R10	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
LEA 0x18(,%RDI,8),%R11	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RCX	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,%R10	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x4,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	scal (12.5%)
CMP %R9,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
JAE 451580 <hypre_BoomerAMGBuildMultipass.extracted.28+0xad0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
ADD %R10,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV -0x40(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x50(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 451588 <hypre_BoomerAMGBuildMultipass.extracted.28+0xad8>	1	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0x40(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x50(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xa0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%RSI,8),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX,%RSI,8),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RDI,%R8	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JLE 451380 <hypre_BoomerAMGBuildMultipass.extracted.28+0x8d0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP $0x4,%R8	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JAE 4515c0 <hypre_BoomerAMGBuildMultipass.extracted.28+0xb10>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
JMP 4516a2 <hypre_BoomerAMGBuildMultipass.extracted.28+0xbf2>	1	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x2,%R9	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
MOV %R10,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x18(,%RDI,8),%R10	1	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
CMP %R8,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JAE 451740 <hypre_BoomerAMGBuildMultipass.extracted.28+0xc90>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
ADD %R9,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV -0x40(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 451388 <hypre_BoomerAMGBuildMultipass.extracted.28+0x8d8>	1	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0x40(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 451388 <hypre_BoomerAMGBuildMultipass.extracted.28+0x8d8>	1	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code