OV - exec - Loop 974

	Loop Id: 974	Module: exec	Source: par_multi_interp.c:1747-1876 [...]	Coverage: 0.14%

0x450e40 MOV	-0x90(%RBP),%RDX

0x450e47 INC	%RDX

0x450e4a CMP	-0x88(%RBP),%RDX

0x450e51 JGE	451a80

0x450e57 MOV	-0x100(%RBP),%RAX

0x450e5e MOV	%RDX,-0x90(%RBP)

0x450e65 MOV	(%RAX,%RDX,8),%R9

0x450e69 MOV	-0x108(%RBP),%RAX

0x450e70 MOV	(%RAX,%R9,8),%R8

0x450e74 MOV	-0x98(%RBP),%RAX

0x450e7b MOV	(%RAX,%R9,8),%R12

0x450e7f MOV	0x8(%RAX,%R9,8),%RDI

0x450e84 LEA	(%RDI,%R8,1),%RAX

0x450e88 SUB	%R12,%RAX

0x450e8b CMP	%RAX,%R8

0x450e8e MOV	%R9,-0x30(%RBP)

0x450e92 JGE	45106f

0x450e98 MOV	-0x60(%RBP),%RAX

0x450e9c MOV	(%RAX),%RAX

0x450e9f MOV	-0xe0(%RBP),%RCX

0x450ea6 MOV	(%RCX,%RAX,8),%RAX

0x450eaa MOV	%RDI,%RCX

0x450ead SUB	%R12,%RCX

0x450eb0 CMP	$0xd,%RCX

0x450eb4 JB	451040

0x450eba MOV	%RDI,-0x80(%RBP)

0x450ebe LEA	(%R14,%R12,8),%RDI

0x450ec2 MOV	%RCX,-0x78(%RBP)

0x450ec6 LEA	(,%RCX,8),%RDX

0x450ece XOR	%ESI,%ESI

0x450ed0 MOV	%RAX,-0x38(%RBP)

0x450ed4 MOV	%R8,-0x48(%RBP)

0x450ed8 VZEROUPPER

0x450edb CALL	5277f0 <__intel_avx_rep_memset>

0x450ee0 MOV	-0x78(%RBP),%RAX

0x450ee4 MOV	%RAX,%R10

0x450ee7 SHR	$0x3,%RAX

0x450eeb MOV	-0x48(%RBP),%RDX

0x450eef MOV	-0x38(%RBP),%RCX

0x450ef3 LEA	0x38(%RCX,%RDX,8),%RCX

0x450ef8 MOV	-0xd8(%RBP),%RDX

0x450eff LEA	(%RDX,%R12,8),%RDX

0x450f03 MOV	%RAX,%RSI

0x450f06 XOR	%EDI,%EDI

0x450f08 MOV	-0x50(%RBP),%R11

0x450f0c NOPL	(%RAX)

  (992) 0x450f10 MOV	-0x38(%RCX,%RDI,8),%R8

  (992) 0x450f15 LEA	(%R12,%RDI,1),%R9

  (992) 0x450f19 MOV	%R9,(%R11,%R8,8)

  (992) 0x450f1d MOV	%R8,-0x38(%RDX,%RDI,8)

  (992) 0x450f22 MOV	-0x30(%RCX,%RDI,8),%R8

  (992) 0x450f27 LEA	0x1(%R12,%RDI,1),%R9

  (992) 0x450f2c MOV	%R9,(%R11,%R8,8)

  (992) 0x450f30 MOV	%R8,-0x30(%RDX,%RDI,8)

  (992) 0x450f35 MOV	-0x28(%RCX,%RDI,8),%R8

  (992) 0x450f3a LEA	0x2(%R12,%RDI,1),%R9

  (992) 0x450f3f MOV	%R9,(%R11,%R8,8)

  (992) 0x450f43 MOV	%R8,-0x28(%RDX,%RDI,8)

  (992) 0x450f48 MOV	-0x20(%RCX,%RDI,8),%R8

  (992) 0x450f4d LEA	0x3(%R12,%RDI,1),%R9

  (992) 0x450f52 MOV	%R9,(%R11,%R8,8)

  (992) 0x450f56 MOV	%R8,-0x20(%RDX,%RDI,8)

  (992) 0x450f5b MOV	-0x18(%RCX,%RDI,8),%R8

  (992) 0x450f60 LEA	0x4(%R12,%RDI,1),%R9

  (992) 0x450f65 MOV	%R9,(%R11,%R8,8)

  (992) 0x450f69 MOV	%R8,-0x18(%RDX,%RDI,8)

  (992) 0x450f6e MOV	-0x10(%RCX,%RDI,8),%R8

  (992) 0x450f73 LEA	0x5(%R12,%RDI,1),%R9

  (992) 0x450f78 MOV	%R9,(%R11,%R8,8)

  (992) 0x450f7c MOV	%R8,-0x10(%RDX,%RDI,8)

  (992) 0x450f81 MOV	-0x8(%RCX,%RDI,8),%R8

  (992) 0x450f86 LEA	0x6(%R12,%RDI,1),%R9

  (992) 0x450f8b MOV	%R9,(%R11,%R8,8)

  (992) 0x450f8f MOV	%R8,-0x8(%RDX,%RDI,8)

  (992) 0x450f94 MOV	(%RCX,%RDI,8),%R8

  (992) 0x450f98 LEA	0x7(%R12,%RDI,1),%R9

  (992) 0x450f9d MOV	%R9,(%R11,%R8,8)

  (992) 0x450fa1 MOV	%R8,(%RDX,%RDI,8)

  (992) 0x450fa5 ADD	$0x8,%RDI

  (992) 0x450fa9 DEC	%RSI

  (992) 0x450fac JNE	450f10

0x450fb2 MOV	%R10,%RDX

0x450fb5 MOV	%R10,%RCX

0x450fb8 AND	$-0x8,%RCX

0x450fbc CMP	%R10,%RCX

0x450fbf MOV	-0x40(%RBP),%R10

0x450fc3 MOV	-0x58(%RBP),%RDX

0x450fc7 MOV	-0x30(%RBP),%R9

0x450fcb MOV	-0x80(%RBP),%RSI

0x450fcf MOV	-0x38(%RBP),%RDI

0x450fd3 MOV	-0x48(%RBP),%R8

0x450fd7 JAE	45106f

0x450fdd ADD	%RCX,%R12

0x450fe0 SAL	$0x6,%RAX

0x450fe4 LEA	(%RAX,%R8,8),%RAX

0x450fe8 ADD	%RAX,%RDI

0x450feb NOPL	(%RAX,%RAX,1)

  (993) 0x450ff0 MOV	(%RDI),%RAX

  (993) 0x450ff3 MOV	%R12,(%R11,%RAX,8)

  (993) 0x450ff7 MOV	%RAX,(%RDX,%R12,8)

  (993) 0x450ffb INC	%R12

  (993) 0x450ffe ADD	$0x8,%RDI

  (993) 0x451002 CMP	%R12,%RSI

  (993) 0x451005 JNE	450ff0

0x451007 JMP	45106f

0x451040 LEA	(%RAX,%R8,8),%RAX

0x451044 MOV	-0x58(%RBP),%RDX

0x451048 MOV	-0x50(%RBP),%RSI

0x45104c NOPL	(%RAX)

  (991) 0x451050 MOV	(%RAX),%RCX

  (991) 0x451053 MOV	%R12,(%RSI,%RCX,8)

  (991) 0x451057 MOVQ	$0,(%R14,%R12,8)

  (991) 0x45105f MOV	%RCX,(%RDX,%R12,8)

  (991) 0x451063 INC	%R12

  (991) 0x451066 ADD	$0x8,%RAX

  (991) 0x45106a CMP	%R12,%RDI

  (991) 0x45106d JNE	451050

0x45106f MOV	-0x110(%RBP),%RAX

0x451076 MOV	(%RAX,%R9,8),%RSI

0x45107a MOV	-0xa0(%RBP),%RAX

0x451081 MOV	(%RAX,%R9,8),%R12

0x451085 MOV	0x8(%RAX,%R9,8),%RDX

0x45108a LEA	(%RDX,%RSI,1),%RAX

0x45108e SUB	%R12,%RAX

0x451091 CMP	%RAX,%RSI

0x451094 JGE	451230

0x45109a MOV	-0x60(%RBP),%RAX

0x45109e MOV	(%RAX),%RAX

0x4510a1 MOV	-0xe8(%RBP),%RCX

0x4510a8 MOV	(%RCX,%RAX,8),%RAX

0x4510ac MOV	%RDX,%RCX

0x4510af SUB	%R12,%RCX

0x4510b2 CMP	$0xd,%RCX

0x4510b6 JB	451200

0x4510bc MOV	%RDX,-0x48(%RBP)

0x4510c0 LEA	(%R13,%R12,8),%RDI

0x4510c5 LEA	(,%RCX,8),%RDX

0x4510cd MOV	%RSI,-0x38(%RBP)

0x4510d1 XOR	%ESI,%ESI

0x4510d3 MOV	%RAX,-0x80(%RBP)

0x4510d7 MOV	%RCX,-0x78(%RBP)

0x4510db VZEROUPPER

0x4510de CALL	5277f0 <__intel_avx_rep_memset>

0x4510e3 MOV	-0x80(%RBP),%R11

0x4510e7 MOV	-0x78(%RBP),%RAX

0x4510eb MOV	%RAX,%R10

0x4510ee SHR	$0x3,%RAX

0x4510f2 MOV	-0x38(%RBP),%RCX

0x4510f6 LEA	0x38(%R11,%RCX,8),%RCX

0x4510fb MOV	-0xd0(%RBP),%RDX

0x451102 LEA	(%RDX,%R12,8),%RDX

0x451106 MOV	%RAX,%RSI

0x451109 XOR	%EDI,%EDI

0x45110b NOPL	(%RAX,%RAX,1)

  (989) 0x451110 MOV	-0x38(%RCX,%RDI,8),%R8

  (989) 0x451115 LEA	(%R12,%RDI,1),%R9

  (989) 0x451119 MOV	%R9,(%R15,%R8,8)

  (989) 0x45111d MOV	%R8,-0x38(%RDX,%RDI,8)

  (989) 0x451122 MOV	-0x30(%RCX,%RDI,8),%R8

  (989) 0x451127 LEA	0x1(%R12,%RDI,1),%R9

  (989) 0x45112c MOV	%R9,(%R15,%R8,8)

  (989) 0x451130 MOV	%R8,-0x30(%RDX,%RDI,8)

  (989) 0x451135 MOV	-0x28(%RCX,%RDI,8),%R8

  (989) 0x45113a LEA	0x2(%R12,%RDI,1),%R9

  (989) 0x45113f MOV	%R9,(%R15,%R8,8)

  (989) 0x451143 MOV	%R8,-0x28(%RDX,%RDI,8)

  (989) 0x451148 MOV	-0x20(%RCX,%RDI,8),%R8

  (989) 0x45114d LEA	0x3(%R12,%RDI,1),%R9

  (989) 0x451152 MOV	%R9,(%R15,%R8,8)

  (989) 0x451156 MOV	%R8,-0x20(%RDX,%RDI,8)

  (989) 0x45115b MOV	-0x18(%RCX,%RDI,8),%R8

  (989) 0x451160 LEA	0x4(%R12,%RDI,1),%R9

  (989) 0x451165 MOV	%R9,(%R15,%R8,8)

  (989) 0x451169 MOV	%R8,-0x18(%RDX,%RDI,8)

  (989) 0x45116e MOV	-0x10(%RCX,%RDI,8),%R8

  (989) 0x451173 LEA	0x5(%R12,%RDI,1),%R9

  (989) 0x451178 MOV	%R9,(%R15,%R8,8)

  (989) 0x45117c MOV	%R8,-0x10(%RDX,%RDI,8)

  (989) 0x451181 MOV	-0x8(%RCX,%RDI,8),%R8

  (989) 0x451186 LEA	0x6(%R12,%RDI,1),%R9

  (989) 0x45118b MOV	%R9,(%R15,%R8,8)

  (989) 0x45118f MOV	%R8,-0x8(%RDX,%RDI,8)

  (989) 0x451194 MOV	(%RCX,%RDI,8),%R8

  (989) 0x451198 LEA	0x7(%R12,%RDI,1),%R9

  (989) 0x45119d MOV	%R9,(%R15,%R8,8)

  (989) 0x4511a1 MOV	%R8,(%RDX,%RDI,8)

  (989) 0x4511a5 ADD	$0x8,%RDI

  (989) 0x4511a9 DEC	%RSI

  (989) 0x4511ac JNE	451110

0x4511b2 MOV	%R10,%RDX

0x4511b5 MOV	%R10,%RCX

0x4511b8 AND	$-0x8,%RCX

0x4511bc CMP	%R10,%RCX

0x4511bf MOV	-0x40(%RBP),%R10

0x4511c3 MOV	-0x30(%RBP),%R9

0x4511c7 MOV	-0x48(%RBP),%RDX

0x4511cb MOV	-0x38(%RBP),%RSI

0x4511cf JAE	451230

0x4511d1 ADD	%RCX,%R12

0x4511d4 SAL	$0x6,%RAX

0x4511d8 LEA	(%RAX,%RSI,8),%RAX

0x4511dc ADD	%RAX,%R11

0x4511df NOP

  (990) 0x4511e0 MOV	(%R11),%RAX

  (990) 0x4511e3 MOV	%R12,(%R15,%RAX,8)

  (990) 0x4511e7 MOV	%RAX,(%R10,%R12,8)

  (990) 0x4511eb INC	%R12

  (990) 0x4511ee ADD	$0x8,%R11

  (990) 0x4511f2 CMP	%R12,%RDX

  (990) 0x4511f5 JNE	4511e0

0x4511f7 JMP	451230

0x451200 LEA	(%RAX,%RSI,8),%RAX

0x451204 NOPW	%CS:(%RAX,%RAX,1)

  (988) 0x451210 MOV	(%RAX),%RCX

  (988) 0x451213 MOV	%R12,(%R15,%RCX,8)

  (988) 0x451217 MOVQ	$0,(%R13,%R12,8)

  (988) 0x451220 MOV	%RCX,(%R10,%R12,8)

  (988) 0x451224 INC	%R12

  (988) 0x451227 ADD	$0x8,%RAX

  (988) 0x45122b CMP	%R12,%RDX

  (988) 0x45122e JNE	451210

0x451230 MOV	-0xb8(%RBP),%RCX

0x451237 MOV	(%RCX,%R9,8),%RAX

0x45123b MOV	0x8(%RCX,%R9,8),%RCX

0x451240 CMP	%RCX,%RAX

0x451243 MOV	-0x50(%RBP),%R12

0x451247 JGE	4512c0

0x451249 MOV	-0x60(%RBP),%RDX

0x45124d MOV	(%RDX),%RDX

0x451250 DEC	%RDX

0x451253 JMP	451288

  (987) 0x451280 INC	%RAX

  (987) 0x451283 CMP	%RCX,%RAX

  (987) 0x451286 JGE	4512c0

  (987) 0x451288 MOV	-0x168(%RBP),%RSI

  (987) 0x45128f MOV	(%RSI,%RAX,8),%RSI

  (987) 0x451293 MOV	-0x178(%RBP),%RDI

  (987) 0x45129a CMP	%RDX,(%RDI,%RSI,8)

  (987) 0x45129e JNE	451280

  (987) 0x4512a0 MOV	-0x70(%RBP),%RCX

  (987) 0x4512a4 MOV	%R9,(%RCX,%RSI,8)

  (987) 0x4512a8 MOV	-0xb8(%RBP),%RCX

  (987) 0x4512af MOV	0x8(%RCX,%R9,8),%RCX

  (987) 0x4512b4 JMP	451280

0x4512c0 MOV	-0xc0(%RBP),%RCX

0x4512c7 MOV	(%RCX,%R9,8),%RAX

0x4512cb MOV	0x8(%RCX,%R9,8),%RCX

0x4512d0 CMP	%RCX,%RAX

0x4512d3 JGE	451340

0x4512d5 MOV	-0x60(%RBP),%RDX

0x4512d9 MOV	(%RDX),%RDX

0x4512dc DEC	%RDX

0x4512df JMP	451308

  (986) 0x451300 INC	%RAX

  (986) 0x451303 CMP	%RCX,%RAX

  (986) 0x451306 JGE	451340

  (986) 0x451308 MOV	-0x170(%RBP),%RSI

  (986) 0x45130f MOV	(%RSI,%RAX,8),%RSI

  (986) 0x451313 MOV	-0x180(%RBP),%RDI

  (986) 0x45131a CMP	%RDX,(%RDI,%RSI,8)

  (986) 0x45131e JNE	451300

  (986) 0x451320 MOV	-0x68(%RBP),%RCX

  (986) 0x451324 MOV	%R9,(%RCX,%RSI,8)

  (986) 0x451328 MOV	-0xc0(%RBP),%RCX

  (986) 0x45132f MOV	0x8(%RCX,%R9,8),%RCX

  (986) 0x451334 JMP	451300

0x451340 MOV	-0xf0(%RBP),%RAX

0x451347 MOV	(%RAX,%R9,8),%RCX

0x45134b MOV	0x8(%RAX,%R9,8),%R11

0x451350 LEA	0x1(%RCX),%RDX

0x451354 VXORPD	%XMM1,%XMM1,%XMM1

0x451358 CMP	%R11,%RDX

0x45135b MOV	%RCX,-0x48(%RBP)

0x45135f VXORPD	%XMM0,%XMM0,%XMM0

0x451363 JGE	451780

0x451369 MOV	-0x58(%RBP),%RAX

0x45136d MOV	%R11,-0x38(%RBP)

0x451371 JMP	451394

  (981) 0x451380 MOV	-0x58(%RBP),%RAX

  (981) 0x451384 MOV	-0x30(%RBP),%R9

  (981) 0x451388 INC	%RDX

  (981) 0x45138b CMP	%R11,%RDX

  (981) 0x45138e JE	451780

  (981) 0x451394 MOV	-0x158(%RBP),%RSI

  (981) 0x45139b MOV	(%RSI,%RDX,8),%RSI

  (981) 0x45139f MOV	-0x70(%RBP),%RDI

  (981) 0x4513a3 CMP	%R9,(%RDI,%RSI,8)

  (981) 0x4513a7 JNE	451400

  (981) 0x4513a9 MOV	-0x98(%RBP),%R8

  (981) 0x4513b0 MOV	(%R8,%RSI,8),%RDI

  (981) 0x4513b4 MOV	0x8(%R8,%RSI,8),%R8

  (981) 0x4513b9 MOV	%R8,%R9

  (981) 0x4513bc SUB	%RDI,%R9

  (981) 0x4513bf JLE	451588

  (981) 0x4513c5 CMP	$0x4,%R9

  (981) 0x4513c9 JAE	451440

  (981) 0x4513cb JMP	451519

  (981) 0x451400 MOV	-0x140(%RBP),%RDI

  (981) 0x451407 CMPQ	$-0x3,(%RDI,%RSI,8)

  (981) 0x45140c JE	451388

  (981) 0x451412 CMPQ	$0x1,-0xc8(%RBP)

  (981) 0x45141a JE	451431

  (981) 0x45141c MOV	-0xa8(%RBP),%R8

  (981) 0x451423 MOV	(%R8,%R9,8),%RDI

  (981) 0x451427 CMP	(%R8,%RSI,8),%RDI

  (981) 0x45142b JNE	451388

  (981) 0x451431 VADDSD	(%RBX,%RDX,8),%XMM0,%XMM0

  (981) 0x451436 JMP	451388

  (981) 0x451440 MOV	%R9,%R10

  (981) 0x451443 SHR	$0x2,%R10

  (981) 0x451447 LEA	0x18(,%RDI,8),%R11

  (981) 0x45144f MOV	%R12,%RCX

  (981) 0x451452 NOPW	%CS:(%RAX,%RAX,1)

    (984) 0x451460 MOV	-0x18(%RAX,%R11,1),%R12

    (984) 0x451465 VMOVSD	-0x18(%R14,%R11,1),%XMM2

    (984) 0x45146c VMOVSD	(%RBX,%RDX,8),%XMM3

    (984) 0x451471 MOV	(%RCX,%R12,8),%R12

    (984) 0x451475 VMOVSD	(%R14,%R12,8),%XMM4

    (984) 0x45147b VFMADD231SD	%XMM2,%XMM3,%XMM4

    (984) 0x451480 VMOVSD	%XMM4,(%R14,%R12,8)

    (984) 0x451486 MOV	-0x10(%RAX,%R11,1),%R12

    (984) 0x45148b VMOVSD	-0x10(%R14,%R11,1),%XMM4

    (984) 0x451492 VMOVSD	(%RBX,%RDX,8),%XMM5

    (984) 0x451497 MOV	(%RCX,%R12,8),%R12

    (984) 0x45149b VMOVSD	(%R14,%R12,8),%XMM6

    (984) 0x4514a1 VFMADD231SD	%XMM4,%XMM5,%XMM6

    (984) 0x4514a6 VMOVSD	%XMM6,(%R14,%R12,8)

    (984) 0x4514ac MOV	-0x8(%RAX,%R11,1),%R12

    (984) 0x4514b1 VMOVSD	-0x8(%R14,%R11,1),%XMM6

    (984) 0x4514b8 VMOVSD	(%RBX,%RDX,8),%XMM7

    (984) 0x4514bd MOV	(%RCX,%R12,8),%R12

    (984) 0x4514c1 VMOVSD	(%R14,%R12,8),%XMM8

    (984) 0x4514c7 VFMADD231SD	%XMM6,%XMM7,%XMM8

    (984) 0x4514cc VMOVSD	%XMM8,(%R14,%R12,8)

    (984) 0x4514d2 VMOVSD	(%R14,%R11,1),%XMM8

    (984) 0x4514d8 VMULSD	(%RBX,%RDX,8),%XMM8,%XMM18

    (984) 0x4514df MOV	(%RAX,%R11,1),%R12

    (984) 0x4514e3 MOV	(%RCX,%R12,8),%R12

    (984) 0x4514e7 VADDSD	(%R14,%R12,8),%XMM18,%XMM8

    (984) 0x4514ee VMOVSD	%XMM8,(%R14,%R12,8)

    (984) 0x4514f4 VFMADD213SD	%XMM18,%XMM5,%XMM4

    (984) 0x4514fa VFMADD231SD	%XMM2,%XMM3,%XMM4

    (984) 0x4514ff VFMADD231SD	%XMM6,%XMM7,%XMM4

    (984) 0x451504 VADDSD	%XMM1,%XMM4,%XMM1

    (984) 0x451508 VADDSD	%XMM0,%XMM4,%XMM0

    (984) 0x45150c ADD	$0x20,%R11

    (984) 0x451510 DEC	%R10

    (984) 0x451513 JNE	451460

  (981) 0x451519 MOV	%R9,%R10

  (981) 0x45151c AND	$-0x4,%R10

  (981) 0x451520 CMP	%R9,%R10

  (981) 0x451523 MOV	-0x38(%RBP),%R11

  (981) 0x451527 JAE	451580

  (981) 0x451529 ADD	%R10,%RDI

  (981) 0x45152c MOV	-0x40(%RBP),%R10

  (981) 0x451530 MOV	-0x50(%RBP),%R12

  (981) 0x451534 NOPW	%CS:(%RAX,%RAX,1)

    (985) 0x451540 MOV	(%RAX,%RDI,8),%R9

    (985) 0x451544 VMOVSD	(%R14,%RDI,8),%XMM2

    (985) 0x45154a VMULSD	(%RBX,%RDX,8),%XMM2,%XMM18

    (985) 0x451551 MOV	(%R12,%R9,8),%R9

    (985) 0x451555 VADDSD	(%R14,%R9,8),%XMM18,%XMM2

    (985) 0x45155c VMOVSD	%XMM2,(%R14,%R9,8)

    (985) 0x451562 VADDSD	%XMM1,%XMM18,%XMM1

    (985) 0x451568 VADDSD	%XMM0,%XMM18,%XMM0

    (985) 0x45156e INC	%RDI

    (985) 0x451571 CMP	%RDI,%R8

    (985) 0x451574 JNE	451540

  (981) 0x451576 JMP	451588

  (981) 0x451580 MOV	-0x40(%RBP),%R10

  (981) 0x451584 MOV	-0x50(%RBP),%R12

  (981) 0x451588 MOV	-0xa0(%RBP),%RAX

  (981) 0x45158f MOV	(%RAX,%RSI,8),%RDI

  (981) 0x451593 MOV	0x8(%RAX,%RSI,8),%RSI

  (981) 0x451598 MOV	%RSI,%R8

  (981) 0x45159b SUB	%RDI,%R8

  (981) 0x45159e JLE	451380

  (981) 0x4515a4 CMP	$0x4,%R8

  (981) 0x4515a8 JAE	4515c0

  (981) 0x4515aa JMP	4516a2

  (981) 0x4515c0 MOV	%R8,%R9

  (981) 0x4515c3 SHR	$0x2,%R9

  (981) 0x4515c7 MOV	%R10,%RAX

  (981) 0x4515ca LEA	0x18(,%RDI,8),%R10

  (981) 0x4515d2 NOPW	%CS:(%RAX,%RAX,1)

    (982) 0x4515e0 MOV	-0x18(%RAX,%R10,1),%R11

    (982) 0x4515e5 VMOVSD	-0x18(%R13,%R10,1),%XMM2

    (982) 0x4515ec VMOVSD	(%RBX,%RDX,8),%XMM3

    (982) 0x4515f1 MOV	(%R15,%R11,8),%R11

    (982) 0x4515f5 VMOVSD	(%R13,%R11,8),%XMM4

    (982) 0x4515fc VFMADD231SD	%XMM2,%XMM3,%XMM4

    (982) 0x451601 VMOVSD	%XMM4,(%R13,%R11,8)

    (982) 0x451608 MOV	-0x10(%RAX,%R10,1),%R11

    (982) 0x45160d VMOVSD	-0x10(%R13,%R10,1),%XMM4

    (982) 0x451614 VMOVSD	(%RBX,%RDX,8),%XMM5

    (982) 0x451619 MOV	(%R15,%R11,8),%R11

    (982) 0x45161d VMOVSD	(%R13,%R11,8),%XMM6

    (982) 0x451624 VFMADD231SD	%XMM4,%XMM5,%XMM6

    (982) 0x451629 VMOVSD	%XMM6,(%R13,%R11,8)

    (982) 0x451630 MOV	-0x8(%RAX,%R10,1),%R11

    (982) 0x451635 VMOVSD	-0x8(%R13,%R10,1),%XMM6

    (982) 0x45163c VMOVSD	(%RBX,%RDX,8),%XMM7

    (982) 0x451641 MOV	(%R15,%R11,8),%R11

    (982) 0x451645 VMOVSD	(%R13,%R11,8),%XMM8

    (982) 0x45164c VFMADD231SD	%XMM6,%XMM7,%XMM8

    (982) 0x451651 VMOVSD	%XMM8,(%R13,%R11,8)

    (982) 0x451658 VMOVSD	(%R13,%R10,1),%XMM8

    (982) 0x45165f VMULSD	(%RBX,%RDX,8),%XMM8,%XMM18

    (982) 0x451666 MOV	(%RAX,%R10,1),%R11

    (982) 0x45166a MOV	(%R15,%R11,8),%R11

    (982) 0x45166e VADDSD	(%R13,%R11,8),%XMM18,%XMM8

    (982) 0x451676 VMOVSD	%XMM8,(%R13,%R11,8)

    (982) 0x45167d VFMADD213SD	%XMM18,%XMM5,%XMM4

    (982) 0x451683 VFMADD231SD	%XMM2,%XMM3,%XMM4

    (982) 0x451688 VFMADD231SD	%XMM6,%XMM7,%XMM4

    (982) 0x45168d VADDSD	%XMM1,%XMM4,%XMM1

    (982) 0x451691 VADDSD	%XMM0,%XMM4,%XMM0

    (982) 0x451695 ADD	$0x20,%R10

    (982) 0x451699 DEC	%R9

    (982) 0x45169c JNE	4515e0

  (981) 0x4516a2 MOV	%R8,%R9

  (981) 0x4516a5 AND	$-0x4,%R9

  (981) 0x4516a9 CMP	%R8,%R9

  (981) 0x4516ac JAE	451740

  (981) 0x4516b2 ADD	%R9,%RDI

  (981) 0x4516b5 MOV	-0x40(%RBP),%R10

  (981) 0x4516b9 MOV	-0x58(%RBP),%RAX

  (981) 0x4516bd MOV	-0x30(%RBP),%R9

  (981) 0x4516c1 MOV	-0x38(%RBP),%R11

  (981) 0x4516c5 NOPW	%CS:(%RAX,%RAX,1)

    (983) 0x4516d0 MOV	(%R10,%RDI,8),%R8

    (983) 0x4516d4 VMOVSD	(%R13,%RDI,8),%XMM2

    (983) 0x4516db VMULSD	(%RBX,%RDX,8),%XMM2,%XMM18

    (983) 0x4516e2 MOV	(%R15,%R8,8),%R8

    (983) 0x4516e6 VADDSD	(%R13,%R8,8),%XMM18,%XMM2

    (983) 0x4516ee VMOVSD	%XMM2,(%R13,%R8,8)

    (983) 0x4516f5 VADDSD	%XMM1,%XMM18,%XMM1

    (983) 0x4516fb VADDSD	%XMM0,%XMM18,%XMM0

    (983) 0x451701 INC	%RDI

    (983) 0x451704 CMP	%RDI,%RSI

    (983) 0x451707 JNE	4516d0

  (981) 0x451709 JMP	451388

  (981) 0x451740 MOV	-0x40(%RBP),%R10

  (981) 0x451744 MOV	-0x58(%RBP),%RAX

  (981) 0x451748 MOV	-0x30(%RBP),%R9

  (981) 0x45174c MOV	-0x38(%RBP),%R11

  (981) 0x451750 JMP	451388

0x451780 MOV	-0xf8(%RBP),%RAX

0x451787 MOV	(%RAX,%R9,8),%RCX

0x45178b MOV	0x8(%RAX,%R9,8),%RDX

0x451790 CMP	%RDX,%RCX

0x451793 JL	451860

0x451799 MOV	-0x48(%RBP),%RAX

0x45179d VMULSD	(%RBX,%RAX,8),%XMM1,%XMM1

0x4517a2 VUCOMISD	%XMM16,%XMM1

0x4517a8 JE	4517b6

0x4517aa VXORPD	%XMM17,%XMM0,%XMM0

0x4517b0 VDIVSD	%XMM1,%XMM0,%XMM18

0x4517b6 MOV	-0x98(%RBP),%RAX

0x4517bd MOV	(%RAX,%R9,8),%RDX

0x4517c1 MOV	0x8(%RAX,%R9,8),%RAX

0x4517c6 MOV	%RAX,%RSI

0x4517c9 SUB	%RDX,%RSI

0x4517cc JLE	4519e5

0x4517d2 MOV	%RSI,%RCX

0x4517d5 AND	$-0x4,%RCX

0x4517d9 JE	4519c0

0x4517df LEA	-0x1(%RCX),%RDI

0x4517e3 VBROADCASTSD	%XMM18,%YMM0

0x4517e9 LEA	(%R14,%RDX,8),%R8

0x4517ed XOR	%R9D,%R9D

  (978) 0x4517f0 VMULPD	(%R8,%R9,8),%YMM0,%YMM1

  (978) 0x4517f6 VMOVUPD	%YMM1,(%R8,%R9,8)

  (978) 0x4517fc ADD	$0x4,%R9

  (978) 0x451800 CMP	%RDI,%R9

  (978) 0x451803 JBE	4517f0

0x451805 CMP	%RCX,%RSI

0x451808 MOV	-0x30(%RBP),%R9

0x45180c JNE	4519c2

0x451812 JMP	4519e5

  (979) 0x451840 VADDSD	(%R8,%RCX,8),%XMM0,%XMM0

  (979) 0x451846 MOV	%R12,%R11

  (979) 0x451849 INC	%RCX

  (979) 0x45184c CMP	%RDX,%RCX

  (979) 0x45184f MOV	-0x40(%RBP),%R10

  (979) 0x451853 MOV	%R11,%R12

  (979) 0x451856 MOV	-0x30(%RBP),%R9

  (979) 0x45185a JE	451799

  (979) 0x451860 MOV	-0x160(%RBP),%RAX

  (979) 0x451867 LEA	(%RAX,%RCX,8),%RSI

  (979) 0x45186b CMPQ	$0,-0x188(%RBP)

  (979) 0x451873 JE	451883

  (979) 0x451875 MOV	(%RSI),%RSI

  (979) 0x451878 MOV	-0x148(%RBP),%RDI

  (979) 0x45187f LEA	(%RDI,%RSI,8),%RSI

  (979) 0x451883 MOV	(%RSI),%RDI

  (979) 0x451886 TEST	%RDI,%RDI

  (979) 0x451889 JS	451940

  (979) 0x45188f MOV	-0x68(%RBP),%RSI

  (979) 0x451893 CMP	%R9,(%RSI,%RDI,8)

  (979) 0x451897 JNE	451940

  (979) 0x45189d MOV	-0x138(%RBP),%RSI

  (979) 0x4518a4 MOV	0x8(%RSI,%RDI,8),%RSI

  (979) 0x4518a9 TEST	%RSI,%RSI

  (979) 0x4518ac JLE	451846

  (979) 0x4518ae MOV	-0x120(%RBP),%R8

  (979) 0x4518b5 MOV	(%R8,%RDI,8),%RDI

  (979) 0x4518b9 ADD	%RDI,%RSI

  (979) 0x4518bc MOV	-0x60(%RBP),%R8

  (979) 0x4518c0 MOV	(%R8),%R8

  (979) 0x4518c3 MOV	-0x128(%RBP),%R9

  (979) 0x4518ca MOV	(%R9,%R8,8),%R8

  (979) 0x4518ce MOV	%R12,%R11

  (979) 0x4518d1 MOV	-0xb0(%RBP),%R12

  (979) 0x4518d8 MOV	-0x130(%RBP),%RAX

  (979) 0x4518df NOP

    (980) 0x4518e0 MOV	(%R8,%RDI,8),%R9

    (980) 0x4518e4 VMOVSD	(%RAX,%RDI,8),%XMM2

    (980) 0x4518e9 VMULSD	(%R12,%RCX,8),%XMM2,%XMM18

    (980) 0x4518f0 TEST	%R9,%R9

    (980) 0x4518f3 LEA	(%R15,%R9,8),%R10

    (980) 0x4518f7 NOT	%R9

    (980) 0x4518fa LEA	(%R11,%R9,8),%R9

    (980) 0x4518fe CMOVNS	%R10,%R9

    (980) 0x451902 MOV	%R13,%R10

    (980) 0x451905 CMOVS	%R14,%R10

    (980) 0x451909 MOV	(%R9),%R9

    (980) 0x45190c VADDSD	(%R10,%R9,8),%XMM18,%XMM2

    (980) 0x451913 VMOVSD	%XMM2,(%R10,%R9,8)

    (980) 0x451919 VADDSD	%XMM1,%XMM18,%XMM1

    (980) 0x45191f VADDSD	%XMM0,%XMM18,%XMM0

    (980) 0x451925 INC	%RDI

    (980) 0x451928 CMP	%RSI,%RDI

    (980) 0x45192b JL	4518e0

  (979) 0x45192d JMP	451849

  (979) 0x451940 MOV	-0x150(%RBP),%RSI

  (979) 0x451947 CMPQ	$-0x3,(%RSI,%RDI,8)

  (979) 0x45194c JE	451846

  (979) 0x451952 CMPQ	$0x1,-0xc8(%RBP)

  (979) 0x45195a MOV	-0xb0(%RBP),%R8

  (979) 0x451961 JE	451840

  (979) 0x451967 MOV	-0x118(%RBP),%RSI

  (979) 0x45196e MOV	(%RSI,%RDI,8),%RSI

  (979) 0x451972 MOV	-0xa8(%RBP),%RDI

  (979) 0x451979 CMP	(%RDI,%R9,8),%RSI

  (979) 0x45197d JE	451840

  (979) 0x451983 JMP	451846

0x4519c0 XOR	%ECX,%ECX

0x4519c2 ADD	%RDX,%RCX

0x4519c5 NOPW	%CS:(%RAX,%RAX,1)

  (977) 0x4519d0 VMULSD	(%R14,%RCX,8),%XMM18,%XMM0

  (977) 0x4519d7 VMOVSD	%XMM0,(%R14,%RCX,8)

  (977) 0x4519dd INC	%RCX

  (977) 0x4519e0 CMP	%RCX,%RAX

  (977) 0x4519e3 JNE	4519d0

0x4519e5 MOV	-0xa0(%RBP),%RAX

0x4519ec MOV	(%RAX,%R9,8),%RDX

0x4519f0 MOV	0x8(%RAX,%R9,8),%RAX

0x4519f5 MOV	%RAX,%RSI

0x4519f8 SUB	%RDX,%RSI

0x4519fb JLE	450e40

0x451a01 MOV	%RSI,%RCX

0x451a04 AND	$-0x4,%RCX

0x451a08 JE	451a40

0x451a0a LEA	-0x1(%RCX),%RDI

0x451a0e VBROADCASTSD	%XMM18,%YMM0

0x451a14 LEA	(%R13,%RDX,8),%R8

0x451a19 XOR	%R9D,%R9D

0x451a1c NOPL	(%RAX)

  (976) 0x451a20 VMULPD	(%R8,%R9,8),%YMM0,%YMM1

  (976) 0x451a26 VMOVUPD	%YMM1,(%R8,%R9,8)

  (976) 0x451a2c ADD	$0x4,%R9

  (976) 0x451a30 CMP	%RDI,%R9

  (976) 0x451a33 JBE	451a20

0x451a35 CMP	%RCX,%RSI

0x451a38 JE	450e40

0x451a3e JMP	451a42

0x451a40 XOR	%ECX,%ECX

0x451a42 ADD	%RDX,%RCX

0x451a45 NOPW	%CS:(%RAX,%RAX,1)

  (975) 0x451a50 VMULSD	(%R13,%RCX,8),%XMM18,%XMM0

  (975) 0x451a58 VMOVSD	%XMM0,(%R13,%RCX,8)

  (975) 0x451a5f INC	%RCX

  (975) 0x451a62 CMP	%RCX,%RAX

  (975) 0x451a65 JNE	451a50

0x451a67 JMP	450e40

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1747 - 1876

--------------------------------------------------------------------------------

1747:              if (n_fine)

[...]

1774:              for (i=thread_start; i < thread_stop; i++)

1775:              {

1776:                 i1 = pass_array[i];

1777:                 sum_C = 0;

1778:                 sum_N = 0;

1779:                 j_start = P_diag_start[i1];

1780:                 j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1781:                 cnt = P_diag_i[i1];

1782:                 for (j=j_start; j < j_end; j++)

1783:                 {

1784:                    k1 = P_diag_pass[pass][j];

1785:                tmp_array[k1] = cnt;

1786:                P_diag_data[cnt] = 0;

1787:                P_diag_j[cnt++] = k1;

1788:                 }

1789:                 j_start = P_offd_start[i1];

1790:                 j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1791:                 cnt_offd = P_offd_i[i1];

1792:                 for (j=j_start; j < j_end; j++)

1793:                 {

1794:                    k1 = P_offd_pass[pass][j];

1795:                tmp_array_offd[k1] = cnt_offd;

1796:                P_offd_data[cnt_offd] = 0;

1797:                P_offd_j[cnt_offd++] = k1;

1798:                 }

1799:                 for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1800:                 {

1801:                j1 = S_diag_j[j];

1802:                if (assigned[j1] == pass-1)

1803:                   tmp_marker[j1] = i1;

1804:                 }

1805:                 for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1806:                 {

1807:                j1 = S_offd_j[j];

1808:                if (assigned_offd[j1] == pass-1)

1809:                   tmp_marker_offd[j1] = i1;

1810:                 }

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

1838:                    }

1839:                 }

1840:                 for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1841:                 {

1842:                if (col_offd_S_to_A)

1843:                   j1 = map_A_to_S[A_offd_j[j]];

1844:                else

1845:                   j1 = A_offd_j[j];

1846:

1847:                if (j1 > -1 && tmp_marker_offd[j1] == i1)

1848:                {

1849:                   j_start = Pext_start[j1];

1850:                   j_end = j_start+Pext_i[j1+1];

1851:                   for (k=j_start; k < j_end; k++)

1852:                   {

1853:                  k1 = Pext_pass[pass][k];

1854:                      alfa = A_offd_data[j]*Pext_data[k];

1855:                  if (k1 < 0)

1856:                         P_diag_data[tmp_array[-k1-1]] += alfa;

1857:                  else

1858:                         P_offd_data[tmp_array_offd[k1]] += alfa;

1859:                      sum_C += alfa;

1860:                      sum_N += alfa;

1861:                       }

1862:                    }

1863:                    else

1864:                    {

1865:                       if (CF_marker_offd[j1] != -3 &&

1866:                 (num_functions == 1 || dof_func_offd[j1] == dof_func[i1]))

1867:                  sum_N += A_offd_data[j];

1868:                    }

1869:                 }

1870:                 diagonal = A_diag_data[A_diag_i[i1]];

1871:                 if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1872:

1873:                 for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++)

1874:                P_diag_data[j] *= alfa;

1875:                 for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++)

1876:                P_offd_data[j] *= alfa;

Coverage (%)	Name	Source Location	Module
►99.74+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	2.55
CQA speedup if FP arith vectorized	3.78
CQA speedup if fully vectorized	7.92
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.49
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass.extracted.28
Source	par_multi_interp.c:1747-1747,par_multi_interp.c:1774-1776,par_multi_interp.c:1779-1786,par_multi_interp.c:1789-1796,par_multi_interp.c:1799-1799,par_multi_interp.c:1802-1802,par_multi_interp.c:1805-1805,par_multi_interp.c:1808-1808,par_multi_interp.c:1811-1811,par_multi_interp.c:1824-1824,par_multi_interp.c:1840-1840,par_multi_interp.c:1865-1865,par_multi_interp.c:1871-1876
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	34.83
CQA cycles if no scalar integer	13.67
CQA cycles if FP arith vectorized	9.21
CQA cycles if fully vectorized	4.40
Front-end cycles	34.83
P0 cycles	12.00
P1 cycles	11.80
P2 cycles	23.33
P3 cycles	23.33
P4 cycles	7.00
P5 cycles	11.60
P6 cycles	12.00
P7 cycles	7.00
P8 cycles	7.00
P9 cycles	7.00
P10 cycles	11.60
P11 cycles	23.33
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	204.00
Nb uops	208.00
Nb loads	70.00
Nb stores	12.00
Nb stack references	24.00
FLOP/cycle	0.06
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.83
Bytes prefetched	0.00
Bytes loaded	560.00
Bytes stored	96.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	12.82
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	21.74
Vector-efficiency ratio all	14.10
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	15.22

Metric	Value
CQA speedup if no scalar integer	2.55
CQA speedup if FP arith vectorized	3.78
CQA speedup if fully vectorized	7.92
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.49
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass.extracted.28
Source	par_multi_interp.c:1747-1747,par_multi_interp.c:1774-1776,par_multi_interp.c:1779-1786,par_multi_interp.c:1789-1796,par_multi_interp.c:1799-1799,par_multi_interp.c:1802-1802,par_multi_interp.c:1805-1805,par_multi_interp.c:1808-1808,par_multi_interp.c:1811-1811,par_multi_interp.c:1824-1824,par_multi_interp.c:1840-1840,par_multi_interp.c:1865-1865,par_multi_interp.c:1871-1876
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	34.83
CQA cycles if no scalar integer	13.67
CQA cycles if FP arith vectorized	9.21
CQA cycles if fully vectorized	4.40
Front-end cycles	34.83
P0 cycles	12.00
P1 cycles	11.80
P2 cycles	23.33
P3 cycles	23.33
P4 cycles	7.00
P5 cycles	11.60
P6 cycles	12.00
P7 cycles	7.00
P8 cycles	7.00
P9 cycles	7.00
P10 cycles	11.60
P11 cycles	23.33
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	204.00
Nb uops	208.00
Nb loads	70.00
Nb stores	12.00
Nb stack references	24.00
FLOP/cycle	0.06
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.83
Bytes prefetched	0.00
Bytes loaded	560.00
Bytes stored	96.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	12.82
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	21.74
Vector-efficiency ratio all	14.10
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	15.22

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass.extracted.28
Source file and lines	par_multi_interp.c:1747-1876
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1747,1774-1876.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1747,1774-1776,1779-1786,1789-1796,1799,1802,1805,1808,1811,1824,1840,1865,1871-1876.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 34.83 to 13.67 cycles (2.55x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__intel_avx_rep_memset: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1786
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1796

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1786
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1796

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: multiply
1: divide

The binary loop is loading 560 bytes (70 double precision FP elements). The binary loop is storing 96 bytes (12 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	204
nb uops	208
loop length	871
used x86 registers	14
used mmx registers	0
used xmm registers	5
used ymm registers	1
used zmm registers	0
nb stack references	24

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	34.83 cycles
front end	34.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	12.00	11.80	23.33	23.33	7.00	11.60	12.00	7.00	7.00	7.00	11.60	23.33
cycles	12.00	11.80	23.33	23.33	7.00	11.60	12.00	7.00	7.00	7.00	11.60	23.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	34.83
Dispatch	23.33
DIV/SQRT	4.00
Overall L1	34.83

Vectorization ratios

INT

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	37%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	50%

INT+FP

all	12%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	21%

Vector efficiency ratios

INT

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	17%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	18%

INT+FP

all	14%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 34.83 cycles. At this rate:

8% of peak load performance is reached (16.08 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.76 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 34.83 to 23.33 cycles (1.49x speedup).

ASM code

In the binary file, the address of the loop is: 450e57

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x90(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP -0x88(%RBP),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 451a80 <hypre_BoomerAMGBuildMultipass.extracted.28+0xfd0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x100(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RAX,%RDX,8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x108(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R9,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x98(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R9,8),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX,%R9,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDI,%R8,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R12,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RAX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R9,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JGE 45106f <hypre_BoomerAMGBuildMultipass.extracted.28+0x5bf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xe0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R12,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP $0xd,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 451040 <hypre_BoomerAMGBuildMultipass.extracted.28+0x590>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R14,%R12,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%RCX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 5277f0 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x78(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x38(%RCX,%RDX,8),%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0xd8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%R12,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x50(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R10,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %R10,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x40(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x58(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x80(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JAE 45106f <hypre_BoomerAMGBuildMultipass.extracted.28+0x5bf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %RCX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SAL $0x6,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%RAX,%R8,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 45106f <hypre_BoomerAMGBuildMultipass.extracted.28+0x5bf>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
LEA (%RAX,%R8,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x58(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x110(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R9,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xa0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R9,8),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX,%R9,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%RSI,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R12,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 451230 <hypre_BoomerAMGBuildMultipass.extracted.28+0x780>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xe8(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R12,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP $0xd,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 451200 <hypre_BoomerAMGBuildMultipass.extracted.28+0x750>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R13,%R12,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%RCX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 5277f0 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x80(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x78(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV -0x38(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x38(%R11,%RCX,8),%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0xd0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%R12,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R10,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %R10,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x40(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JAE 451230 <hypre_BoomerAMGBuildMultipass.extracted.28+0x780>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %RCX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SAL $0x6,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%RAX,%RSI,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RAX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 451230 <hypre_BoomerAMGBuildMultipass.extracted.28+0x780>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
LEA (%RAX,%RSI,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0xb8(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%R9,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RCX,%R9,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x50(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JGE 4512c0 <hypre_BoomerAMGBuildMultipass.extracted.28+0x810>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x60(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DEC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 451288 <hypre_BoomerAMGBuildMultipass.extracted.28+0x7d8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0xc0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%R9,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RCX,%R9,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 451340 <hypre_BoomerAMGBuildMultipass.extracted.28+0x890>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x60(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DEC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 451308 <hypre_BoomerAMGBuildMultipass.extracted.28+0x858>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0xf0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R9,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX,%R9,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%RCX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMP %R11,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RCX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JGE 451780 <hypre_BoomerAMGBuildMultipass.extracted.28+0xcd0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 451394 <hypre_BoomerAMGBuildMultipass.extracted.28+0x8e4>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0xf8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R9,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX,%R9,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 451860 <hypre_BoomerAMGBuildMultipass.extracted.28+0xdb0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD (%RBX,%RAX,8),%XMM1,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VUCOMISD %XMM16,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JE 4517b6 <hypre_BoomerAMGBuildMultipass.extracted.28+0xd06>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPD %XMM17,%XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VDIVSD %XMM1,%XMM0,%XMM18	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
MOV -0x98(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R9,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX,%R9,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JLE 4519e5 <hypre_BoomerAMGBuildMultipass.extracted.28+0xf35>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4519c0 <hypre_BoomerAMGBuildMultipass.extracted.28+0xf10>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RCX),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VBROADCASTSD %XMM18,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA (%R14,%RDX,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RCX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x30(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 4519c2 <hypre_BoomerAMGBuildMultipass.extracted.28+0xf12>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 4519e5 <hypre_BoomerAMGBuildMultipass.extracted.28+0xf35>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0xa0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R9,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX,%R9,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JLE 450e40 <hypre_BoomerAMGBuildMultipass.extracted.28+0x390>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 451a40 <hypre_BoomerAMGBuildMultipass.extracted.28+0xf90>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RCX),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VBROADCASTSD %XMM18,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA (%R13,%RDX,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RCX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 450e40 <hypre_BoomerAMGBuildMultipass.extracted.28+0x390>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 451a42 <hypre_BoomerAMGBuildMultipass.extracted.28+0xf92>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 450e40 <hypre_BoomerAMGBuildMultipass.extracted.28+0x390>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	hypre_BoomerAMGBuildMultipass.extracted.28
Source file and lines	par_multi_interp.c:1747-1876
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

__intel_avx_rep_memset: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1786
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1796

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1786
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1796

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: multiply
1: divide

The binary loop is loading 560 bytes (70 double precision FP elements). The binary loop is storing 96 bytes (12 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	204
nb uops	208
loop length	871
used x86 registers	14
used mmx registers	0
used xmm registers	5
used ymm registers	1
used zmm registers	0
nb stack references	24

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	34.83 cycles
front end	34.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	12.00	11.80	23.33	23.33	7.00	11.60	12.00	7.00	7.00	7.00	11.60	23.33
cycles	12.00	11.80	23.33	23.33	7.00	11.60	12.00	7.00	7.00	7.00	11.60	23.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	34.83
Dispatch	23.33
DIV/SQRT	4.00
Overall L1	34.83

Vectorization ratios

INT

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	37%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	50%

INT+FP

all	12%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	21%

Vector efficiency ratios

INT

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	17%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	18%

INT+FP

all	14%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 34.83 cycles. At this rate:

8% of peak load performance is reached (16.08 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.76 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 450e57

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x90(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP -0x88(%RBP),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 451a80 <hypre_BoomerAMGBuildMultipass.extracted.28+0xfd0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x100(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RAX,%RDX,8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x108(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R9,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x98(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R9,8),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX,%R9,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDI,%R8,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R12,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RAX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R9,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JGE 45106f <hypre_BoomerAMGBuildMultipass.extracted.28+0x5bf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xe0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R12,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP $0xd,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 451040 <hypre_BoomerAMGBuildMultipass.extracted.28+0x590>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R14,%R12,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%RCX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 5277f0 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x78(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x38(%RCX,%RDX,8),%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0xd8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%R12,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x50(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R10,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %R10,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x40(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x58(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x80(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JAE 45106f <hypre_BoomerAMGBuildMultipass.extracted.28+0x5bf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %RCX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SAL $0x6,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%RAX,%R8,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 45106f <hypre_BoomerAMGBuildMultipass.extracted.28+0x5bf>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
LEA (%RAX,%R8,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x58(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x110(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R9,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xa0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R9,8),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX,%R9,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%RSI,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R12,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 451230 <hypre_BoomerAMGBuildMultipass.extracted.28+0x780>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xe8(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R12,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP $0xd,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 451200 <hypre_BoomerAMGBuildMultipass.extracted.28+0x750>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R13,%R12,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%RCX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 5277f0 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x80(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x78(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV -0x38(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x38(%R11,%RCX,8),%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0xd0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%R12,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R10,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %R10,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x40(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JAE 451230 <hypre_BoomerAMGBuildMultipass.extracted.28+0x780>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %RCX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SAL $0x6,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%RAX,%RSI,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RAX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 451230 <hypre_BoomerAMGBuildMultipass.extracted.28+0x780>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
LEA (%RAX,%RSI,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0xb8(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%R9,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RCX,%R9,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x50(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JGE 4512c0 <hypre_BoomerAMGBuildMultipass.extracted.28+0x810>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x60(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DEC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 451288 <hypre_BoomerAMGBuildMultipass.extracted.28+0x7d8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0xc0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%R9,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RCX,%R9,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 451340 <hypre_BoomerAMGBuildMultipass.extracted.28+0x890>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x60(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DEC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 451308 <hypre_BoomerAMGBuildMultipass.extracted.28+0x858>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0xf0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R9,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX,%R9,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%RCX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMP %R11,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RCX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JGE 451780 <hypre_BoomerAMGBuildMultipass.extracted.28+0xcd0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 451394 <hypre_BoomerAMGBuildMultipass.extracted.28+0x8e4>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0xf8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R9,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX,%R9,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 451860 <hypre_BoomerAMGBuildMultipass.extracted.28+0xdb0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD (%RBX,%RAX,8),%XMM1,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VUCOMISD %XMM16,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JE 4517b6 <hypre_BoomerAMGBuildMultipass.extracted.28+0xd06>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPD %XMM17,%XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VDIVSD %XMM1,%XMM0,%XMM18	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
MOV -0x98(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R9,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX,%R9,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JLE 4519e5 <hypre_BoomerAMGBuildMultipass.extracted.28+0xf35>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4519c0 <hypre_BoomerAMGBuildMultipass.extracted.28+0xf10>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RCX),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VBROADCASTSD %XMM18,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA (%R14,%RDX,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RCX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x30(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 4519c2 <hypre_BoomerAMGBuildMultipass.extracted.28+0xf12>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 4519e5 <hypre_BoomerAMGBuildMultipass.extracted.28+0xf35>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0xa0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R9,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX,%R9,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JLE 450e40 <hypre_BoomerAMGBuildMultipass.extracted.28+0x390>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 451a40 <hypre_BoomerAMGBuildMultipass.extracted.28+0xf90>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RCX),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VBROADCASTSD %XMM18,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA (%R13,%RDX,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RCX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 450e40 <hypre_BoomerAMGBuildMultipass.extracted.28+0x390>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 451a42 <hypre_BoomerAMGBuildMultipass.extracted.28+0xf92>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 450e40 <hypre_BoomerAMGBuildMultipass.extracted.28+0x390>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code