OV - exec - Loop 963

	Loop Id: 963	Module: exec	Source: par_multi_interp.c:1585-1660 [...]	Coverage: 0.05%

0x450480 MOV	-0x50(%RBP),%RDX

0x450484 INC	%RDX

0x450487 CMP	-0x38(%RBP),%RDX

0x45048b JGE	450a80

0x450491 MOV	-0xd8(%RBP),%RAX

0x450498 MOV	%RDX,-0x50(%RBP)

0x45049c MOV	(%RAX,%RDX,8),%RAX

0x4504a0 MOV	-0xe0(%RBP),%RCX

0x4504a7 MOV	(%RCX,%RAX,8),%RDI

0x4504ab MOV	-0x58(%RBP),%RCX

0x4504af MOV	(%RCX,%RAX,8),%RSI

0x4504b3 MOV	0x8(%RCX,%RAX,8),%RCX

0x4504b8 LEA	(%RCX,%RDI,1),%RDX

0x4504bc SUB	%RSI,%RDX

0x4504bf CMP	%RDX,%RDI

0x4504c2 JGE	450595

0x4504c8 MOV	-0xc0(%RBP),%RDX

0x4504cf MOV	0x8(%RDX),%R8

0x4504d3 SUB	%RSI,%RCX

0x4504d6 CMP	$0x8,%RCX

0x4504da JB	450560

0x4504e0 MOV	%RCX,%R9

0x4504e3 SHR	$0x3,%R9

0x4504e7 LEA	0x38(%R8,%RDI,8),%R10

0x4504ec NOPL	(%RAX)

  (973) 0x4504f0 MOV	-0x38(%R10),%RDX

  (973) 0x4504f4 MOV	(%R15,%RDX,8),%RDX

  (973) 0x4504f8 MOV	%RAX,(%R13,%RDX,8)

  (973) 0x4504fd MOV	-0x30(%R10),%RDX

  (973) 0x450501 MOV	(%R15,%RDX,8),%RDX

  (973) 0x450505 MOV	%RAX,(%R13,%RDX,8)

  (973) 0x45050a MOV	-0x28(%R10),%RDX

  (973) 0x45050e MOV	(%R15,%RDX,8),%RDX

  (973) 0x450512 MOV	%RAX,(%R13,%RDX,8)

  (973) 0x450517 MOV	-0x20(%R10),%RDX

  (973) 0x45051b MOV	(%R15,%RDX,8),%RDX

  (973) 0x45051f MOV	%RAX,(%R13,%RDX,8)

  (973) 0x450524 MOV	-0x18(%R10),%RDX

  (973) 0x450528 MOV	(%R15,%RDX,8),%RDX

  (973) 0x45052c MOV	%RAX,(%R13,%RDX,8)

  (973) 0x450531 MOV	-0x10(%R10),%RDX

  (973) 0x450535 MOV	(%R15,%RDX,8),%RDX

  (973) 0x450539 MOV	%RAX,(%R13,%RDX,8)

  (973) 0x45053e MOV	-0x8(%R10),%RDX

  (973) 0x450542 MOV	(%R15,%RDX,8),%RDX

  (973) 0x450546 MOV	%RAX,(%R13,%RDX,8)

  (973) 0x45054b MOV	(%R10),%RDX

  (973) 0x45054e MOV	(%R15,%RDX,8),%RDX

  (973) 0x450552 MOV	%RAX,(%R13,%RDX,8)

  (973) 0x450557 ADD	$0x40,%R10

  (973) 0x45055b DEC	%R9

  (973) 0x45055e JNE	4504f0

0x450560 MOV	%RCX,%R9

0x450563 AND	$-0x8,%R9

0x450567 CMP	%RCX,%R9

0x45056a MOV	-0x40(%RBP),%R10

0x45056e JAE	450595

0x450570 LEA	(%R8,%RDI,8),%RDI

0x450574 NOPW	%CS:(%RAX,%RAX,1)

  (972) 0x450580 MOV	(%RDI,%R9,8),%RDX

  (972) 0x450584 MOV	(%R15,%RDX,8),%RDX

  (972) 0x450588 MOV	%RAX,(%R13,%RDX,8)

  (972) 0x45058d INC	%R9

  (972) 0x450590 CMP	%R9,%RCX

  (972) 0x450593 JNE	450580

0x450595 MOV	-0x58(%RBP),%RCX

0x450599 MOV	(%RCX,%RAX,8),%RDX

0x45059d MOV	-0x68(%RBP),%RCX

0x4505a1 MOV	(%RCX,%RAX,8),%RDI

0x4505a5 MOV	0x8(%RCX,%RAX,8),%R8

0x4505aa INC	%RDI

0x4505ad VXORPD	%XMM4,%XMM4,%XMM4

0x4505b1 CMP	%R8,%RDI

0x4505b4 MOV	%RDX,-0x30(%RBP)

0x4505b8 VXORPD	%XMM3,%XMM3,%XMM3

0x4505bc JGE	4506c0

0x4505c2 MOV	-0xb8(%RBP),%RCX

0x4505c9 MOV	-0x78(%RBP),%RSI

0x4505cd JMP	45060c

  (971) 0x450600 INC	%RDI

  (971) 0x450603 CMP	%R8,%RDI

  (971) 0x450606 JGE	4506c0

  (971) 0x45060c MOV	(%RSI,%RDI,8),%R9

  (971) 0x450610 CMPQ	$-0x3,(%R10,%R9,8)

  (971) 0x450615 JE	45063f

  (971) 0x450617 CMPQ	$0x1,-0xa0(%RBP)

  (971) 0x45061f JE	450636

  (971) 0x450621 MOV	-0x90(%RBP),%RSI

  (971) 0x450628 MOV	(%RSI,%RAX,8),%RDX

  (971) 0x45062c CMP	(%RSI,%R9,8),%RDX

  (971) 0x450630 MOV	-0x78(%RBP),%RSI

  (971) 0x450634 JNE	45063f

  (971) 0x450636 MOV	-0x70(%RBP),%RDX

  (971) 0x45063a VADDSD	(%RDX,%RDI,8),%XMM3,%XMM3

  (971) 0x45063f CMP	$-0x1,%R9

  (971) 0x450643 JE	450600

  (971) 0x450645 CMP	%RAX,(%R13,%R9,8)

  (971) 0x45064a JNE	450600

  (971) 0x45064c MOV	-0x70(%RBP),%R8

  (971) 0x450650 VMOVSD	(%R8,%RDI,8),%XMM5

  (971) 0x450656 MOV	-0x88(%RBP),%RDX

  (971) 0x45065d MOV	-0x30(%RBP),%R11

  (971) 0x450661 VMOVSD	%XMM5,(%RDX,%R11,8)

  (971) 0x450667 MOV	-0x108(%RBP),%RDX

  (971) 0x45066e MOV	(%RDX,%R9,8),%RDX

  (971) 0x450672 MOV	%RDX,(%RCX,%R11,8)

  (971) 0x450676 INC	%R11

  (971) 0x450679 MOV	%R11,-0x30(%RBP)

  (971) 0x45067d VADDSD	(%R8,%RDI,8),%XMM4,%XMM4

  (971) 0x450683 MOV	-0x68(%RBP),%RDX

  (971) 0x450687 MOV	0x8(%RDX,%RAX,8),%R8

  (971) 0x45068c JMP	450600

0x4506c0 MOV	-0xe8(%RBP),%RDX

0x4506c7 MOV	(%RDX,%RAX,8),%R8

0x4506cb MOV	-0x60(%RBP),%RCX

0x4506cf MOV	(%RCX,%RAX,8),%RSI

0x4506d3 MOV	0x8(%RCX,%RAX,8),%RDI

0x4506d8 LEA	(%RDI,%R8,1),%RDX

0x4506dc SUB	%RSI,%RDX

0x4506df CMP	%RDX,%R8

0x4506e2 JGE	4507a4

0x4506e8 MOV	-0xc8(%RBP),%RDX

0x4506ef MOV	0x8(%RDX),%R9

0x4506f3 SUB	%RSI,%RDI

0x4506f6 CMP	$0x8,%RDI

0x4506fa JB	450778

0x450700 MOV	%RDI,%R10

0x450703 SHR	$0x3,%R10

0x450707 LEA	0x38(%R9,%R8,8),%R11

0x45070c NOPL	(%RAX)

  (970) 0x450710 MOV	-0x38(%R11),%RDX

  (970) 0x450714 MOV	(%RBX,%RDX,8),%RDX

  (970) 0x450718 MOV	%RAX,(%R14,%RDX,8)

  (970) 0x45071c MOV	-0x30(%R11),%RDX

  (970) 0x450720 MOV	(%RBX,%RDX,8),%RDX

  (970) 0x450724 MOV	%RAX,(%R14,%RDX,8)

  (970) 0x450728 MOV	-0x28(%R11),%RDX

  (970) 0x45072c MOV	(%RBX,%RDX,8),%RDX

  (970) 0x450730 MOV	%RAX,(%R14,%RDX,8)

  (970) 0x450734 MOV	-0x20(%R11),%RDX

  (970) 0x450738 MOV	(%RBX,%RDX,8),%RDX

  (970) 0x45073c MOV	%RAX,(%R14,%RDX,8)

  (970) 0x450740 MOV	-0x18(%R11),%RDX

  (970) 0x450744 MOV	(%RBX,%RDX,8),%RDX

  (970) 0x450748 MOV	%RAX,(%R14,%RDX,8)

  (970) 0x45074c MOV	-0x10(%R11),%RDX

  (970) 0x450750 MOV	(%RBX,%RDX,8),%RDX

  (970) 0x450754 MOV	%RAX,(%R14,%RDX,8)

  (970) 0x450758 MOV	-0x8(%R11),%RDX

  (970) 0x45075c MOV	(%RBX,%RDX,8),%RDX

  (970) 0x450760 MOV	%RAX,(%R14,%RDX,8)

  (970) 0x450764 MOV	(%R11),%RDX

  (970) 0x450767 MOV	(%RBX,%RDX,8),%RDX

  (970) 0x45076b MOV	%RAX,(%R14,%RDX,8)

  (970) 0x45076f ADD	$0x40,%R11

  (970) 0x450773 DEC	%R10

  (970) 0x450776 JNE	450710

0x450778 MOV	%RDI,%R10

0x45077b AND	$-0x8,%R10

0x45077f CMP	%RDI,%R10

0x450782 JAE	4507a4

0x450784 LEA	(%R9,%R8,8),%R8

0x450788 NOPL	(%RAX,%RAX,1)

  (969) 0x450790 MOV	(%R8,%R10,8),%RDX

  (969) 0x450794 MOV	(%RBX,%RDX,8),%RDX

  (969) 0x450798 MOV	%RAX,(%R14,%RDX,8)

  (969) 0x45079c INC	%R10

  (969) 0x45079f CMP	%R10,%RDI

  (969) 0x4507a2 JNE	450790

0x4507a4 MOV	-0x60(%RBP),%RCX

0x4507a8 MOV	(%RCX,%RAX,8),%RDI

0x4507ac MOV	-0x80(%RBP),%RCX

0x4507b0 MOV	(%RCX,%RAX,8),%R8

0x4507b4 MOV	0x8(%RCX,%RAX,8),%R10

0x4507b9 CMP	%R10,%R8

0x4507bc JGE	4508c0

0x4507c2 MOV	-0xb0(%RBP),%RCX

0x4507c9 LEA	(%RCX,%R8,8),%R9

0x4507cd MOV	-0xd0(%RBP),%RSI

0x4507d4 JMP	450810

  (968) 0x450800 INC	%R8

  (968) 0x450803 ADD	$0x8,%R9

  (968) 0x450807 CMP	%R10,%R8

  (968) 0x45080a JGE	4508c0

  (968) 0x450810 MOV	%R9,%RDX

  (968) 0x450813 TEST	%RSI,%RSI

  (968) 0x450816 JE	450826

  (968) 0x450818 MOV	(%R9),%RDX

  (968) 0x45081b MOV	-0x110(%RBP),%R11

  (968) 0x450822 LEA	(%R11,%RDX,8),%RDX

  (968) 0x450826 MOV	(%RDX),%R11

  (968) 0x450829 CMPQ	$-0x3,(%R12,%R11,8)

  (968) 0x45082e JE	450865

  (968) 0x450830 CMPQ	$0x1,-0xa0(%RBP)

  (968) 0x450838 JE	450858

  (968) 0x45083a MOV	-0x90(%RBP),%RDX

  (968) 0x450841 MOV	(%RDX,%RAX,8),%RDX

  (968) 0x450845 MOV	%R12,%RCX

  (968) 0x450848 MOV	-0xf0(%RBP),%R12

  (968) 0x45084f CMP	(%R12,%R11,8),%RDX

  (968) 0x450853 MOV	%RCX,%R12

  (968) 0x450856 JNE	450865

  (968) 0x450858 MOV	-0x98(%RBP),%RCX

  (968) 0x45085f VADDSD	(%RCX,%R8,8),%XMM3,%XMM3

  (968) 0x450865 CMP	$-0x1,%R11

  (968) 0x450869 JE	450800

  (968) 0x45086b CMP	%RAX,(%R14,%R11,8)

  (968) 0x45086f JNE	450800

  (968) 0x450871 MOV	-0x98(%RBP),%R10

  (968) 0x450878 VMOVSD	(%R10,%R8,8),%XMM5

  (968) 0x45087e MOV	-0x48(%RBP),%RCX

  (968) 0x450882 VMOVSD	%XMM5,(%RCX,%RDI,8)

  (968) 0x450887 MOV	-0x100(%RBP),%RDX

  (968) 0x45088e MOV	(%RDX,%R11,8),%RDX

  (968) 0x450892 MOV	-0xf8(%RBP),%RCX

  (968) 0x450899 MOV	%RDX,(%RCX,%RDI,8)

  (968) 0x45089d INC	%RDI

  (968) 0x4508a0 VADDSD	(%R10,%R8,8),%XMM4,%XMM4

  (968) 0x4508a6 MOV	-0x80(%RBP),%RCX

  (968) 0x4508aa MOV	0x8(%RCX,%RAX,8),%R10

  (968) 0x4508af JMP	450800

0x4508c0 MOV	-0x68(%RBP),%RCX

0x4508c4 MOV	(%RCX,%RAX,8),%RDX

0x4508c8 MOV	-0x70(%RBP),%RCX

0x4508cc VMULSD	(%RCX,%RDX,8),%XMM4,%XMM4

0x4508d1 VUCOMISD	%XMM0,%XMM4

0x4508d5 JE	4508df

0x4508d7 VXORPD	%XMM1,%XMM3,%XMM2

0x4508db VDIVSD	%XMM4,%XMM2,%XMM2

0x4508df MOV	-0x58(%RBP),%RCX

0x4508e3 MOV	(%RCX,%RAX,8),%R9

0x4508e7 MOV	-0x30(%RBP),%RSI

0x4508eb MOV	%RSI,%R10

0x4508ee SUB	%R9,%R10

0x4508f1 MOV	-0x48(%RBP),%RDX

0x4508f5 MOV	-0x88(%RBP),%RCX

0x4508fc JLE	4509a4

0x450902 MOV	%R10,%R8

0x450905 AND	$-0x4,%R8

0x450909 JE	450980

0x45090b LEA	-0x1(%R8),%R11

0x45090f VBROADCASTSD	%XMM2,%YMM3

0x450914 LEA	(%RCX,%R9,8),%RSI

0x450918 XOR	%EDX,%EDX

0x45091a NOPW	(%RAX,%RAX,1)

  (967) 0x450920 VMULPD	(%RSI,%RDX,8),%YMM3,%YMM4

  (967) 0x450925 VMOVUPD	%YMM4,(%RSI,%RDX,8)

  (967) 0x45092a ADD	$0x4,%RDX

  (967) 0x45092e CMP	%R11,%RDX

  (967) 0x450931 JBE	450920

0x450933 CMP	%R8,%R10

0x450936 MOV	-0x48(%RBP),%RDX

0x45093a MOV	-0x30(%RBP),%RSI

0x45093e JNE	450983

0x450940 JMP	4509a4

0x450980 XOR	%R8D,%R8D

0x450983 ADD	%R9,%R8

0x450986 NOPW	%CS:(%RAX,%RAX,1)

  (966) 0x450990 VMULSD	(%RCX,%R8,8),%XMM2,%XMM3

  (966) 0x450996 VMOVSD	%XMM3,(%RCX,%R8,8)

  (966) 0x45099c INC	%R8

  (966) 0x45099f CMP	%R8,%RSI

  (966) 0x4509a2 JNE	450990

0x4509a4 MOV	-0x60(%RBP),%RCX

0x4509a8 MOV	(%RCX,%RAX,8),%RCX

0x4509ac MOV	%RDI,%R8

0x4509af SUB	%RCX,%R8

0x4509b2 MOV	-0x40(%RBP),%R10

0x4509b6 JLE	450480

0x4509bc MOV	%R8,%RAX

0x4509bf AND	$-0x4,%RAX

0x4509c3 JE	450a40

0x4509c5 LEA	-0x1(%RAX),%R9

0x4509c9 VBROADCASTSD	%XMM2,%YMM3

0x4509ce LEA	(%RDX,%RCX,8),%RSI

0x4509d2 XOR	%EDX,%EDX

0x4509d4 NOPW	%CS:(%RAX,%RAX,1)

  (965) 0x4509e0 VMULPD	(%RSI,%RDX,8),%YMM3,%YMM4

  (965) 0x4509e5 VMOVUPD	%YMM4,(%RSI,%RDX,8)

  (965) 0x4509ea ADD	$0x4,%RDX

  (965) 0x4509ee CMP	%R9,%RDX

  (965) 0x4509f1 JBE	4509e0

0x4509f3 CMP	%RAX,%R8

0x4509f6 MOV	-0x48(%RBP),%RDX

0x4509fa JE	450480

0x450a00 JMP	450a42

0x450a40 XOR	%EAX,%EAX

0x450a42 ADD	%RCX,%RAX

0x450a45 NOPW	%CS:(%RAX,%RAX,1)

  (964) 0x450a50 VMULSD	(%RDX,%RAX,8),%XMM2,%XMM3

  (964) 0x450a55 VMOVSD	%XMM3,(%RDX,%RAX,8)

  (964) 0x450a5a INC	%RAX

  (964) 0x450a5d CMP	%RAX,%RDI

  (964) 0x450a60 JNE	450a50

0x450a62 JMP	450480

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1585 - 1660

--------------------------------------------------------------------------------

1585:            if (n_fine)

[...]

1598:            thread_start = pass_pointer[1] + (pass_length/num_threads)*my_thread_num;

[...]

1605:            for (i=thread_start; i < thread_stop; i++)

1606:            {

1607:              i1 = pass_array[i];

1608:              sum_C = 0;

1609:              sum_N = 0;

1610:              j_start = P_diag_start[i1];

1611:              j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1612:              for (j=j_start; j < j_end; j++)

1613:              {

1614:                 k1 = P_diag_pass[1][j];

1615:                 tmp_marker[C_array[k1]] = i1;

1616:              }

1617:              cnt = P_diag_i[i1];

1618:              for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1619:              {

1620:                 j1 = A_diag_j[j];

1621:                 if (CF_marker[j1] != -3 &&

1622:                    (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1623:                    sum_N += A_diag_data[j];

1624:                 if (j1 != -1 && tmp_marker[j1] == i1)

1625:                 {

1626:                    P_diag_data[cnt] = A_diag_data[j];

1627:                    P_diag_j[cnt++] = fine_to_coarse[j1];

1628:                    sum_C += A_diag_data[j];

1629:                 }

1630:              }

1631:              j_start = P_offd_start[i1];

1632:              j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1633:              for (j=j_start; j < j_end; j++)

1634:              {

1635:                 k1 = P_offd_pass[1][j];

1636:                 tmp_marker_offd[C_array_offd[k1]] = i1;

1637:              }

1638:              cnt_offd = P_offd_i[i1];

1639:              for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1640:              {

1641:                 if (col_offd_S_to_A)

1642:                     j1 = map_A_to_S[A_offd_j[j]];

1643:                 else

1644:                     j1 = A_offd_j[j];

1645:                 if (CF_marker_offd[j1] != -3 &&

1646:                   (num_functions == 1 || dof_func[i1] == dof_func_offd[j1]))

1647:                     sum_N += A_offd_data[j];

1648:                 if (j1 != -1 && tmp_marker_offd[j1] == i1)

1649:                 {

1650:                    P_offd_data[cnt_offd] = A_offd_data[j];

1651:                    P_offd_j[cnt_offd++] = map_S_to_new[j1];

1652:                    sum_C += A_offd_data[j];

1653:                 }

1654:              }

1655:              diagonal = A_diag_data[A_diag_i[i1]];

1656:              if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1657:              for (j=P_diag_i[i1]; j < cnt; j++)

1658:                 P_diag_data[j] *= alfa;

1659:              for (j=P_offd_i[i1]; j < cnt_offd; j++)

1660:                 P_offd_data[j] *= alfa;

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	2.52
CQA speedup if FP arith vectorized	3.23
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.42
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass.extracted.27
Source	par_multi_interp.c:1585-1585,par_multi_interp.c:1598-1598,par_multi_interp.c:1605-1607,par_multi_interp.c:1610-1614,par_multi_interp.c:1617-1618,par_multi_interp.c:1631-1635,par_multi_interp.c:1638-1639,par_multi_interp.c:1655-1660
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	22.67
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	7.02
CQA cycles if fully vectorized	2.83
Front-end cycles	22.67
P0 cycles	10.00
P1 cycles	9.80
P2 cycles	16.00
P3 cycles	16.00
P4 cycles	1.00
P5 cycles	9.60
P6 cycles	10.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	9.60
P11 cycles	16.00
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	135.00
Nb uops	135.00
Nb loads	48.00
Nb stores	2.00
Nb stack references	20.00
FLOP/cycle	0.09
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.65
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	8.33
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	13.64
Vector-efficiency ratio all	13.54
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	14.20

Metric	Value
CQA speedup if no scalar integer	2.52
CQA speedup if FP arith vectorized	3.23
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.42
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass.extracted.27
Source	par_multi_interp.c:1585-1585,par_multi_interp.c:1598-1598,par_multi_interp.c:1605-1607,par_multi_interp.c:1610-1614,par_multi_interp.c:1617-1618,par_multi_interp.c:1631-1635,par_multi_interp.c:1638-1639,par_multi_interp.c:1655-1660
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	22.67
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	7.02
CQA cycles if fully vectorized	2.83
Front-end cycles	22.67
P0 cycles	10.00
P1 cycles	9.80
P2 cycles	16.00
P3 cycles	16.00
P4 cycles	1.00
P5 cycles	9.60
P6 cycles	10.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	9.60
P11 cycles	16.00
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	135.00
Nb uops	135.00
Nb loads	48.00
Nb stores	2.00
Nb stack references	20.00
FLOP/cycle	0.09
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.65
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	8.33
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	13.64
Vector-efficiency ratio all	13.54
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	14.20

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass.extracted.27
Source file and lines	par_multi_interp.c:1585-1660
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1585,1598,1605-1660.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1585,1598,1605-1607,1610-1614,1617-1618,1631-1635,1638-1639,1655-1660.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 22.67 to 9.00 cycles (2.52x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: multiply
1: divide

The binary loop is loading 384 bytes (48 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	135
nb uops	135
loop length	579
used x86 registers	10
used mmx registers	0
used xmm registers	5
used ymm registers	1
used zmm registers	0
nb stack references	20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	22.67 cycles
front end	22.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.00	9.80	16.00	16.00	1.00	9.60	10.00	1.00	1.00	1.00	9.60	16.00
cycles	10.00	9.80	16.00	16.00	1.00	9.60	10.00	1.00	1.00	1.00	9.60	16.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	22.67
Dispatch	16.00
DIV/SQRT	4.00
Overall L1	22.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	37%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	50%

INT+FP

all	8%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	13%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	17%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	18%

INT+FP

all	13%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 22.67 cycles. At this rate:

8% of peak load performance is reached (16.94 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.71 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 22.67 to 16.00 cycles (1.42x speedup).

ASM code

In the binary file, the address of the loop is: 450491

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x50(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP -0x38(%RBP),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 450a80 <hypre_BoomerAMGBuildMultipass.extracted.27+0x8e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xd8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RAX,%RDX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xe0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x58(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%RCX,%RAX,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%RDI,1),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RDX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 450595 <hypre_BoomerAMGBuildMultipass.extracted.27+0x3f5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xc0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RDX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RSI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP $0x8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 450560 <hypre_BoomerAMGBuildMultipass.extracted.27+0x3c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%R9	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA 0x38(%R8,%RDI,8),%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x40(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JAE 450595 <hypre_BoomerAMGBuildMultipass.extracted.27+0x3f5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%R8,%RDI,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x58(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RCX,%RAX,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VXORPD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMP %R8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RDX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JGE 4506c0 <hypre_BoomerAMGBuildMultipass.extracted.27+0x520>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xb8(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x78(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 45060c <hypre_BoomerAMGBuildMultipass.extracted.27+0x46c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0xe8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RAX,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x60(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%RCX,%RAX,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDI,%R8,1),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RDX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4507a4 <hypre_BoomerAMGBuildMultipass.extracted.27+0x604>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xc8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RDX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RSI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP $0x8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 450778 <hypre_BoomerAMGBuildMultipass.extracted.27+0x5d8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x3,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
LEA 0x38(%R9,%R8,8),%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x8,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
CMP %RDI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 4507a4 <hypre_BoomerAMGBuildMultipass.extracted.27+0x604>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%R9,%R8,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x60(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x80(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RCX,%RAX,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %R10,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4508c0 <hypre_BoomerAMGBuildMultipass.extracted.27+0x720>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xb0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%R8,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0xd0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 450810 <hypre_BoomerAMGBuildMultipass.extracted.27+0x670>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0x68(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD (%RCX,%RDX,8),%XMM4,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VUCOMISD %XMM0,%XMM4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JE 4508df <hypre_BoomerAMGBuildMultipass.extracted.27+0x73f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPD %XMM1,%XMM3,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VDIVSD %XMM4,%XMM2,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
MOV -0x58(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RSI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %R9,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x88(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JLE 4509a4 <hypre_BoomerAMGBuildMultipass.extracted.27+0x804>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 450980 <hypre_BoomerAMGBuildMultipass.extracted.27+0x7e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%R8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VBROADCASTSD %XMM2,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA (%RCX,%R9,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R8,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JNE 450983 <hypre_BoomerAMGBuildMultipass.extracted.27+0x7e3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 4509a4 <hypre_BoomerAMGBuildMultipass.extracted.27+0x804>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R9,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x60(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RCX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x40(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JLE 450480 <hypre_BoomerAMGBuildMultipass.extracted.27+0x2e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 450a40 <hypre_BoomerAMGBuildMultipass.extracted.27+0x8a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RAX),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VBROADCASTSD %XMM2,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA (%RDX,%RCX,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RAX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 450480 <hypre_BoomerAMGBuildMultipass.extracted.27+0x2e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 450a42 <hypre_BoomerAMGBuildMultipass.extracted.27+0x8a2>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 450480 <hypre_BoomerAMGBuildMultipass.extracted.27+0x2e0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	hypre_BoomerAMGBuildMultipass.extracted.27
Source file and lines	par_multi_interp.c:1585-1660
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 22.67 to 9.00 cycles (2.52x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: multiply
1: divide

The binary loop is loading 384 bytes (48 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	135
nb uops	135
loop length	579
used x86 registers	10
used mmx registers	0
used xmm registers	5
used ymm registers	1
used zmm registers	0
nb stack references	20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	22.67 cycles
front end	22.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.00	9.80	16.00	16.00	1.00	9.60	10.00	1.00	1.00	1.00	9.60	16.00
cycles	10.00	9.80	16.00	16.00	1.00	9.60	10.00	1.00	1.00	1.00	9.60	16.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	22.67
Dispatch	16.00
DIV/SQRT	4.00
Overall L1	22.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	37%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	50%

INT+FP

all	8%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	13%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	17%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	18%

INT+FP

all	13%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 22.67 cycles. At this rate:

8% of peak load performance is reached (16.94 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.71 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 450491

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x50(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP -0x38(%RBP),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 450a80 <hypre_BoomerAMGBuildMultipass.extracted.27+0x8e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xd8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RAX,%RDX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xe0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x58(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%RCX,%RAX,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%RDI,1),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RDX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 450595 <hypre_BoomerAMGBuildMultipass.extracted.27+0x3f5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xc0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RDX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RSI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP $0x8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 450560 <hypre_BoomerAMGBuildMultipass.extracted.27+0x3c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%R9	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA 0x38(%R8,%RDI,8),%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x40(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JAE 450595 <hypre_BoomerAMGBuildMultipass.extracted.27+0x3f5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%R8,%RDI,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x58(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RCX,%RAX,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VXORPD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMP %R8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RDX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JGE 4506c0 <hypre_BoomerAMGBuildMultipass.extracted.27+0x520>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xb8(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x78(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 45060c <hypre_BoomerAMGBuildMultipass.extracted.27+0x46c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0xe8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RAX,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x60(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%RCX,%RAX,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDI,%R8,1),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RDX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4507a4 <hypre_BoomerAMGBuildMultipass.extracted.27+0x604>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xc8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RDX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RSI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP $0x8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 450778 <hypre_BoomerAMGBuildMultipass.extracted.27+0x5d8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x3,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
LEA 0x38(%R9,%R8,8),%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x8,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
CMP %RDI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 4507a4 <hypre_BoomerAMGBuildMultipass.extracted.27+0x604>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%R9,%R8,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x60(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x80(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RCX,%RAX,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %R10,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4508c0 <hypre_BoomerAMGBuildMultipass.extracted.27+0x720>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xb0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%R8,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0xd0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 450810 <hypre_BoomerAMGBuildMultipass.extracted.27+0x670>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0x68(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD (%RCX,%RDX,8),%XMM4,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VUCOMISD %XMM0,%XMM4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JE 4508df <hypre_BoomerAMGBuildMultipass.extracted.27+0x73f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPD %XMM1,%XMM3,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VDIVSD %XMM4,%XMM2,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
MOV -0x58(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RSI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %R9,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x88(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JLE 4509a4 <hypre_BoomerAMGBuildMultipass.extracted.27+0x804>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 450980 <hypre_BoomerAMGBuildMultipass.extracted.27+0x7e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%R8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VBROADCASTSD %XMM2,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA (%RCX,%R9,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R8,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JNE 450983 <hypre_BoomerAMGBuildMultipass.extracted.27+0x7e3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 4509a4 <hypre_BoomerAMGBuildMultipass.extracted.27+0x804>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R9,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x60(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RCX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x40(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JLE 450480 <hypre_BoomerAMGBuildMultipass.extracted.27+0x2e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 450a40 <hypre_BoomerAMGBuildMultipass.extracted.27+0x8a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RAX),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VBROADCASTSD %XMM2,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA (%RDX,%RCX,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RAX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 450480 <hypre_BoomerAMGBuildMultipass.extracted.27+0x2e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 450a42 <hypre_BoomerAMGBuildMultipass.extracted.27+0x8a2>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 450480 <hypre_BoomerAMGBuildMultipass.extracted.27+0x2e0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code