OV - exec - Loop 4358

	Loop Id: 4358	Module: exec	Source: csr_matvec.c:560-567	Coverage: 0.60%

0x512bc0 CMP	%R11,%RDX

0x512bc3 LEA	0x1(%RDX),%RDX

0x512bc7 JE	512a03

0x512bcd LEA	(%RCX,%RDX,1),%RSI

0x512bd1 MOV	-0x90(%RBP),%RAX

0x512bd8 MOV	(%RAX,%RSI,8),%RDI

0x512bdc MOV	0x8(%RAX,%RSI,8),%R8

0x512be1 MOV	%R8,%R10

0x512be4 SUB	%RDI,%R10

0x512be7 JLE	512bc0

0x512be9 MOV	%R10,%R9

0x512bec AND	$-0x4,%R9

0x512bf0 JE	512c40

0x512bf2 LEA	-0x1(%R9),%RAX

0x512bf6 XOR	%R11D,%R11D

0x512bf9 NOPL	(%RAX)

  (4362) 0x512c00 ADD	$0x4,%R11

  (4362) 0x512c04 CMP	%RAX,%R11

  (4362) 0x512c07 JBE	512c00

0x512c09 MOV	%R9,%RAX

0x512c0c CMP	%R9,%R10

0x512c0f JNE	512c42

0x512c11 JMP	512c55

0x512c40 XOR	%EAX,%EAX

0x512c42 ADD	%RDI,%RAX

0x512c45 SUB	%R8,%RAX

0x512c48 NOPL	(%RAX,%RAX,1)

  (4359) 0x512c50 INC	%RAX

  (4359) 0x512c53 JNE	512c50

0x512c55 CMP	$0x4,%R10

0x512c59 JB	512cfb

0x512c5f MOV	%R10,%R11

0x512c62 SHR	$0x2,%R11

0x512c66 LEA	0x18(,%RDI,8),%RAX

0x512c6e XCHG	%AX,%AX

  (4361) 0x512c70 VMOVSD	(%R15,%RSI,8),%XMM0

  (4361) 0x512c76 VMOVSD	-0x18(%R12,%RAX,1),%XMM1

  (4361) 0x512c7d MOV	-0x18(%R14,%RAX,1),%RCX

  (4361) 0x512c82 ADD	%R13,%RCX

  (4361) 0x512c85 VFMADD213SD	(%RBX,%RCX,8),%XMM0,%XMM1

  (4361) 0x512c8b VMOVSD	%XMM1,(%RBX,%RCX,8)

  (4361) 0x512c90 VMOVSD	(%R15,%RSI,8),%XMM0

  (4361) 0x512c96 VMOVSD	-0x10(%R12,%RAX,1),%XMM1

  (4361) 0x512c9d MOV	-0x10(%R14,%RAX,1),%RCX

  (4361) 0x512ca2 ADD	%R13,%RCX

  (4361) 0x512ca5 VFMADD213SD	(%RBX,%RCX,8),%XMM0,%XMM1

  (4361) 0x512cab VMOVSD	%XMM1,(%RBX,%RCX,8)

  (4361) 0x512cb0 VMOVSD	(%R15,%RSI,8),%XMM0

  (4361) 0x512cb6 VMOVSD	-0x8(%R12,%RAX,1),%XMM1

  (4361) 0x512cbd MOV	-0x8(%R14,%RAX,1),%RCX

  (4361) 0x512cc2 ADD	%R13,%RCX

  (4361) 0x512cc5 VFMADD213SD	(%RBX,%RCX,8),%XMM0,%XMM1

  (4361) 0x512ccb VMOVSD	%XMM1,(%RBX,%RCX,8)

  (4361) 0x512cd0 VMOVSD	(%R15,%RSI,8),%XMM0

  (4361) 0x512cd6 VMOVSD	(%R12,%RAX,1),%XMM1

  (4361) 0x512cdc MOV	(%R14,%RAX,1),%RCX

  (4361) 0x512ce0 ADD	%R13,%RCX

  (4361) 0x512ce3 VFMADD213SD	(%RBX,%RCX,8),%XMM0,%XMM1

  (4361) 0x512ce9 VMOVSD	%XMM1,(%RBX,%RCX,8)

  (4361) 0x512cee ADD	$0x20,%RAX

  (4361) 0x512cf2 DEC	%R11

  (4361) 0x512cf5 JNE	512c70

0x512cfb CMP	%R10,%R9

0x512cfe MOV	-0x30(%RBP),%RCX

0x512d02 MOV	-0x88(%RBP),%R11

0x512d09 JAE	512bc0

0x512d0f ADD	%R9,%RDI

0x512d12 NOPW	%CS:(%RAX,%RAX,1)

  (4360) 0x512d20 VMOVSD	(%R15,%RSI,8),%XMM0

  (4360) 0x512d26 VMOVSD	(%R12,%RDI,8),%XMM1

  (4360) 0x512d2c MOV	(%R14,%RDI,8),%RAX

  (4360) 0x512d30 ADD	%R13,%RAX

  (4360) 0x512d33 VFMADD213SD	(%RBX,%RAX,8),%XMM0,%XMM1

  (4360) 0x512d39 VMOVSD	%XMM1,(%RBX,%RAX,8)

  (4360) 0x512d3e INC	%RDI

  (4360) 0x512d41 CMP	%RDI,%R8

  (4360) 0x512d44 JNE	512d20

0x512d46 JMP	512bc0

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 560 - 567

--------------------------------------------------------------------------------

560: #pragma omp for HYPRE_SMP_SCHEDULE

561: #endif

562:             for (i = 0; i < num_rows; i++)

563:             {

564:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

565:                {

566:                   j = A_j[jj];

567:                   y_data_expand[offset + j] += A_data[jj] * x_data[i];

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.16
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.76
Bottlenecks	micro-operation queue,
Function	hypre_CSRMatrixMatvecT.extracted.49
Source	csr_matvec.c:560-564
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.17
CQA cycles if no scalar integer	6.17
CQA cycles if FP arith vectorized	6.17
CQA cycles if fully vectorized	0.47
Front-end cycles	6.17
P0 cycles	3.50
P1 cycles	3.00
P2 cycles	1.67
P3 cycles	1.67
P4 cycles	0.00
P5 cycles	3.00
P6 cycles	3.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	3.00
P11 cycles	1.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	5.00
Nb stores	0.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.49
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.93
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.72

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.16
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.76
Bottlenecks	micro-operation queue,
Function	hypre_CSRMatrixMatvecT.extracted.49
Source	csr_matvec.c:560-564
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.17
CQA cycles if no scalar integer	6.17
CQA cycles if FP arith vectorized	6.17
CQA cycles if fully vectorized	0.47
Front-end cycles	6.17
P0 cycles	3.50
P1 cycles	3.00
P2 cycles	1.67
P3 cycles	1.67
P4 cycles	0.00
P5 cycles	3.00
P6 cycles	3.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	3.00
P11 cycles	1.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	5.00
Nb stores	0.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.49
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.93
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.72

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixMatvecT.extracted.49
Source file and lines	csr_matvec.c:560-567
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560-567.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560-564.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=13
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 13 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.17 to 0.47 cycles (13.16x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes.

General properties

nb instructions	37
nb uops	37
loop length	159
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.17 cycles
front end	6.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.50	3.00	1.67	1.67	0.00	3.00	3.50	0.00	0.00	0.00	3.00	1.67
cycles	3.50	3.00	1.67	1.67	0.00	3.00	3.50	0.00	0.00	0.00	3.00	1.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.17
Dispatch	3.50
Overall L1	6.17

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.17 cycles. At this rate:

3% of peak load performance is reached (6.49 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.17 to 3.50 cycles (1.76x speedup).

ASM code

In the binary file, the address of the loop is: 512bcd

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
CMP %R11,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
LEA 0x1(%RDX),%RDX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 512a03 <hypre_CSRMatrixMatvecT.extracted.49+0xc3>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
LEA (%RCX,%RDX,1),%RSI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x90(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%RSI,8),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX,%RSI,8),%R8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R8,%R10	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDI,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JLE 512bc0 <hypre_CSRMatrixMatvecT.extracted.49+0x280>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV %R10,%R9	1	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
JE 512c40 <hypre_CSRMatrixMatvecT.extracted.49+0x300>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
LEA -0x1(%R9),%RAX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JNE 512c42 <hypre_CSRMatrixMatvecT.extracted.49+0x302>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
JMP 512c55 <hypre_CSRMatrixMatvecT.extracted.49+0x315>	1	0	0	0	0	0	0	0	0	0	5.84	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RDI,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
SUB %R8,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x4,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JB 512cfb <hypre_CSRMatrixMatvecT.extracted.49+0x3bb>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV %R10,%R11	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x2,%R11	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
LEA 0x18(,%RDI,8),%RAX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R10,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
MOV -0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x88(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
JAE 512bc0 <hypre_CSRMatrixMatvecT.extracted.49+0x280>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
ADD %R9,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 512bc0 <hypre_CSRMatrixMatvecT.extracted.49+0x280>	1	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	hypre_CSRMatrixMatvecT.extracted.49
Source file and lines	csr_matvec.c:560-567
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=13
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes.

General properties

nb instructions	37
nb uops	37
loop length	159
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.17 cycles
front end	6.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.50	3.00	1.67	1.67	0.00	3.00	3.50	0.00	0.00	0.00	3.00	1.67
cycles	3.50	3.00	1.67	1.67	0.00	3.00	3.50	0.00	0.00	0.00	3.00	1.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.17
Dispatch	3.50
Overall L1	6.17

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.17 cycles. At this rate:

3% of peak load performance is reached (6.49 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 512bcd

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
CMP %R11,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
LEA 0x1(%RDX),%RDX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 512a03 <hypre_CSRMatrixMatvecT.extracted.49+0xc3>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
LEA (%RCX,%RDX,1),%RSI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x90(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%RSI,8),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX,%RSI,8),%R8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R8,%R10	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDI,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JLE 512bc0 <hypre_CSRMatrixMatvecT.extracted.49+0x280>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV %R10,%R9	1	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
JE 512c40 <hypre_CSRMatrixMatvecT.extracted.49+0x300>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
LEA -0x1(%R9),%RAX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JNE 512c42 <hypre_CSRMatrixMatvecT.extracted.49+0x302>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
JMP 512c55 <hypre_CSRMatrixMatvecT.extracted.49+0x315>	1	0	0	0	0	0	0	0	0	0	5.84	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RDI,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
SUB %R8,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x4,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JB 512cfb <hypre_CSRMatrixMatvecT.extracted.49+0x3bb>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV %R10,%R11	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x2,%R11	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
LEA 0x18(,%RDI,8),%RAX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R10,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
MOV -0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x88(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
JAE 512bc0 <hypre_CSRMatrixMatvecT.extracted.49+0x280>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
ADD %R9,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 512bc0 <hypre_CSRMatrixMatvecT.extracted.49+0x280>	1	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code