OV - exec - Loop 4311

	Loop Id: 4311	Module: exec	Source: csr_matvec.c:248-341 [...]	Coverage: 0.91%

0x511200 VMOVSD	%XMM0,(%R13,%R8,8)

0x511207 CMP	%RSI,%RDI

0x51120a LEA	0x1(%RDI),%RDI

0x51120e JE	511d00

0x511214 LEA	(%R12,%RDI,1),%R8

0x511218 MOV	0x28(%RBP),%RAX

0x51121c VMOVSD	(%RAX,%R8,8),%XMM0

0x511222 MOV	(%RBX,%R8,8),%R11

0x511226 MOV	0x8(%RBX,%R8,8),%R9

0x51122b MOV	%R9,%R15

0x51122e SUB	%R11,%R15

0x511231 JLE	511200

0x511233 MOV	%R15,%R10

0x511236 AND	$-0x4,%R10

0x51123a JE	5112c0

0x511240 LEA	-0x1(%R10),%R13

0x511244 LEA	(%R14,%R11,8),%RSI

0x511248 LEA	(%RDX,%R11,8),%RAX

0x51124c VXORPD	%XMM1,%XMM1,%XMM1

0x511250 XOR	%R12D,%R12D

0x511253 NOPW	%CS:(%RAX,%RAX,1)

  (4313) 0x511260 VMOVUPD	(%RAX,%R12,8),%YMM2

  (4313) 0x511266 VXORPD	%XMM3,%XMM3,%XMM3

  (4313) 0x51126a KXNORW	%K0,%K0,%K1

  (4313) 0x51126e VGATHERQPD	(%RCX,%YMM2,8),%YMM3{%K1}

  (4313) 0x511275 VFMADD231PD	(%RSI,%R12,8),%YMM3,%YMM1

  (4313) 0x51127b ADD	$0x4,%R12

  (4313) 0x51127f CMP	%R13,%R12

  (4313) 0x511282 JBE	511260

0x511284 VEXTRACTF128	$0x1,%YMM1,%XMM2

0x51128a VADDPD	%XMM2,%XMM1,%XMM1

0x51128e VSHUFPD	$0x1,%XMM1,%XMM1,%XMM2

0x511293 VADDSD	%XMM2,%XMM1,%XMM1

0x511297 VADDSD	%XMM1,%XMM0,%XMM0

0x51129b CMP	%R10,%R15

0x51129e MOV	-0x38(%RBP),%R12

0x5112a2 MOV	-0x30(%RBP),%RSI

0x5112a6 MOV	0x30(%RBP),%R13

0x5112aa JE	511200

0x5112b0 JMP	5112c3

0x5112c0 XOR	%R10D,%R10D

0x5112c3 ADD	%R11,%R10

0x5112c6 NOPW	%CS:(%RAX,%RAX,1)

  (4312) 0x5112d0 MOV	(%RDX,%R10,8),%RAX

  (4312) 0x5112d4 VMOVSD	(%RCX,%RAX,8),%XMM1

  (4312) 0x5112d9 VFMADD231SD	(%R14,%R10,8),%XMM1,%XMM0

  (4312) 0x5112df INC	%R10

  (4312) 0x5112e2 CMP	%R10,%R9

  (4312) 0x5112e5 JNE	5112d0

0x5112e7 JMP	511200

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 248 - 341

--------------------------------------------------------------------------------

248:       hypre_assert(iBegin <= iEnd);

[...]

334:             for (i = iBegin; i < iEnd; i++)

335:             {

336:                tempx = b_data[i];

337:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

338:                {

339:                   tempx += A_data[jj] * x_data[A_j[jj]];

340:                }

341:                y_data[i] = tempx;

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	2.04
CQA speedup if FP arith vectorized	1.83
CQA speedup if fully vectorized	7.53
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.90
Bottlenecks
Function	hypre_CSRMatrixMatvecOutOfPlace.extracted
Source	csr_matvec.c:248-248,csr_matvec.c:334-341
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	1.96
CQA cycles if FP arith vectorized	2.19
CQA cycles if fully vectorized	0.53
Front-end cycles	4.00
P0 cycles	1.98
P1 cycles	1.85
P2 cycles	1.83
P3 cycles	1.83
P4 cycles	0.50
P5 cycles	1.75
P6 cycles	1.98
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	1.70
P11 cycles	1.83
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.25
Nb uops	24.00
Nb loads	5.50
Nb stores	1.00
Nb stack references	2.50
FLOP/cycle	0.50
Nb FLOP add-sub	2.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.45
Bytes prefetched	0.00
Bytes loaded	44.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	16.23
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	19.44
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	31.25
Vector-efficiency ratio all	14.53
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	14.93
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.41

Metric	Value
CQA speedup if no scalar integer	1.83
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	micro-operation queue,
Function	hypre_CSRMatrixMatvecOutOfPlace.extracted
Source	csr_matvec.c:248-248,csr_matvec.c:334-341
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.83
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.83
CQA cycles if fully vectorized	0.23
Front-end cycles	1.83
P0 cycles	1.00
P1 cycles	0.40
P2 cycles	1.33
P3 cycles	1.33
P4 cycles	0.50
P5 cycles	0.40
P6 cycles	1.00
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	0.20
P11 cycles	1.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	12.00
Nb uops	11.00
Nb loads	4.00
Nb stores	1.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.82
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	2.11
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.11
Bottlenecks	micro-operation queue,
Function	hypre_CSRMatrixMatvecOutOfPlace.extracted
Source	csr_matvec.c:248-248,csr_matvec.c:334-341
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.17
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	3.17
CQA cycles if fully vectorized	0.40
Front-end cycles	3.17
P0 cycles	1.50
P1 cycles	1.40
P2 cycles	1.33
P3 cycles	1.33
P4 cycles	0.50
P5 cycles	1.40
P6 cycles	1.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	1.20
P11 cycles	1.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	19.00
Nb loads	4.00
Nb stores	1.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.63
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	8.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	1.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	2.19
CQA speedup if FP arith vectorized	2.83
CQA speedup if fully vectorized	7.37
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.01
Bottlenecks	micro-operation queue,
Function	hypre_CSRMatrixMatvecOutOfPlace.extracted
Source	csr_matvec.c:248-248,csr_matvec.c:334-341
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.83
CQA cycles if no scalar integer	2.67
CQA cycles if FP arith vectorized	2.06
CQA cycles if fully vectorized	0.79
Front-end cycles	5.83
P0 cycles	2.80
P1 cycles	2.90
P2 cycles	2.33
P3 cycles	2.33
P4 cycles	0.50
P5 cycles	2.70
P6 cycles	2.80
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	2.80
P11 cycles	2.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	35.00
Nb loads	7.00
Nb stores	1.00
Nb stack references	4.00
FLOP/cycle	0.69
Nb FLOP add-sub	4.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.97
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	8.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	4.00
Stride indirect	2.00
Vectorization ratio all	28.57
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	25.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	16.07
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	15.63
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	1.94
CQA speedup if FP arith vectorized	3.06
CQA speedup if fully vectorized	7.29
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.91
Bottlenecks	micro-operation queue,
Function	hypre_CSRMatrixMatvecOutOfPlace.extracted
Source	csr_matvec.c:248-248,csr_matvec.c:334-341
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.17
CQA cycles if no scalar integer	2.67
CQA cycles if FP arith vectorized	1.69
CQA cycles if fully vectorized	0.71
Front-end cycles	5.17
P0 cycles	2.60
P1 cycles	2.70
P2 cycles	2.33
P3 cycles	2.33
P4 cycles	0.50
P5 cycles	2.50
P6 cycles	2.60
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	2.60
P11 cycles	2.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	31.00
Nb loads	7.00
Nb stores	1.00
Nb stack references	4.00
FLOP/cycle	0.77
Nb FLOP add-sub	4.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.39
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	8.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	1.00
Vectorization ratio all	36.36
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	33.33
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	75.00
Vector-efficiency ratio all	17.05
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	16.67
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	21.88

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixMatvecOutOfPlace.extracted
Source file and lines	csr_matvec.c:248-341
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:248,334-341.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions).

Details

16% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
19% of SSE/AVX addition or subtraction instructions are used in vector version.
31% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 0 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

2: addition or subtraction

The binary loop is loading 44 bytes (5 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	24.25
nb uops	24
loop length	109
used x86 registers	12.75
used mmx registers	0
used xmm registers	2
used ymm registers	0.50
used zmm registers	0
nb stack references	2.50

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	4.00 cycles
front end	4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.98	1.85	1.83	1.83	0.50	1.75	1.98	0.50	0.50	0.50	1.70	1.83
cycles	1.98	1.85	1.83	1.83	0.50	1.75	1.98	0.50	0.50	0.50	1.70	1.83

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	4.00
Dispatch	2.11
Data deps.	0.00
Overall L1	4.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	25%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	16%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	19%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	31%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	15%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	14%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

6% of peak load performance is reached (12.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.45 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	hypre_CSRMatrixMatvecOutOfPlace.extracted
Source file and lines	csr_matvec.c:248-341
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.83 to 1.00 cycles (1.83x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.83 to 0.23 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	12
nb uops	11
loop length	51
used x86 registers	11
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.83 cycles
front end	1.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.00	0.40	1.33	1.33	0.50	0.40	1.00	0.50	0.50	0.50	0.20	1.33
cycles	1.00	0.40	1.33	1.33	0.50	0.40	1.00	0.50	0.50	0.50	0.20	1.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	1.83
Dispatch	1.33
Data deps.	0.00
Overall L1	1.83

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.83 cycles. At this rate:

9% of peak load performance is reached (17.45 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.36 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.83 to 1.33 cycles (1.38x speedup).

ASM code

In the binary file, the address of the loop is: 511214

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVSD %XMM0,(%R13,%R8,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RSI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
LEA 0x1(%RDI),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 511d00 <hypre_CSRMatrixMatvecOutOfPlace.extracted+0x1010>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%R12,%RDI,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x28(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RAX,%R8,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RBX,%R8,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RBX,%R8,8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R11,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JLE 511200 <hypre_CSRMatrixMatvecOutOfPlace.extracted+0x510>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	hypre_CSRMatrixMatvecOutOfPlace.extracted
Source file and lines	csr_matvec.c:248-341
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.17 to 1.50 cycles (2.11x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.17 to 0.40 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	19
nb uops	19
loop length	85
used x86 registers	12
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.17 cycles
front end	3.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.50	1.40	1.33	1.33	0.50	1.40	1.50	0.50	0.50	0.50	1.20	1.33
cycles	1.50	1.40	1.33	1.33	0.50	1.40	1.50	0.50	0.50	0.50	1.20	1.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	3.17
Dispatch	1.50
Data deps.	0.00
Overall L1	3.17

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.17 cycles. At this rate:

5% of peak load performance is reached (10.11 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.53 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 511214

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVSD %XMM0,(%R13,%R8,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RSI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
LEA 0x1(%RDI),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 511d00 <hypre_CSRMatrixMatvecOutOfPlace.extracted+0x1010>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%R12,%RDI,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x28(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RAX,%R8,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RBX,%R8,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RBX,%R8,8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %R11,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 511200 <hypre_CSRMatrixMatvecOutOfPlace.extracted+0x510>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 5112c0 <hypre_CSRMatrixMatvecOutOfPlace.extracted+0x5d0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R11,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 511200 <hypre_CSRMatrixMatvecOutOfPlace.extracted+0x510>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	hypre_CSRMatrixMatvecOutOfPlace.extracted
Source file and lines	csr_matvec.c:248-341
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.83 to 2.67 cycles (2.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions).

Details

28% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
25% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)
Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:339

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 4 FP arithmetical operations:

4: addition or subtraction

The binary loop is loading 56 bytes (7 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	35
nb uops	35
loop length	160
used x86 registers	14
used mmx registers	0
used xmm registers	3
used ymm registers	1
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.83 cycles
front end	5.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.80	2.90	2.33	2.33	0.50	2.70	2.80	0.50	0.50	0.50	2.80	2.33
cycles	2.80	2.90	2.33	2.33	0.50	2.70	2.80	0.50	0.50	0.50	2.80	2.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	5.83
Dispatch	2.90
Data deps.	0.00
Overall L1	5.83

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	28%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	18%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	16%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	15%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.83 cycles. At this rate:

5% of peak load performance is reached (9.60 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.37 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 511214

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVSD %XMM0,(%R13,%R8,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RSI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
LEA 0x1(%RDI),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 511d00 <hypre_CSRMatrixMatvecOutOfPlace.extracted+0x1010>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%R12,%RDI,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x28(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RAX,%R8,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RBX,%R8,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RBX,%R8,8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %R11,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 511200 <hypre_CSRMatrixMatvecOutOfPlace.extracted+0x510>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 5112c0 <hypre_CSRMatrixMatvecOutOfPlace.extracted+0x5d0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%R10),%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R14,%R11,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RDX,%R11,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VEXTRACTF128 $0x1,%YMM1,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM2,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM2,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
CMP %R10,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x38(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 511200 <hypre_CSRMatrixMatvecOutOfPlace.extracted+0x510>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 5112c3 <hypre_CSRMatrixMatvecOutOfPlace.extracted+0x5d3>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
ADD %R11,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 511200 <hypre_CSRMatrixMatvecOutOfPlace.extracted+0x510>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	hypre_CSRMatrixMatvecOutOfPlace.extracted
Source file and lines	csr_matvec.c:248-341
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.17 to 2.67 cycles (1.94x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 17% of vector register length is used (average across all SSE/AVX instructions).

Details

36% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
33% of SSE/AVX addition or subtraction instructions are used in vector version.
75% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:339

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 4 FP arithmetical operations:

4: addition or subtraction

The binary loop is loading 56 bytes (7 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	31
nb uops	31
loop length	140
used x86 registers	14
used mmx registers	0
used xmm registers	3
used ymm registers	1
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.17 cycles
front end	5.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.60	2.70	2.33	2.33	0.50	2.50	2.60	0.50	0.50	0.50	2.60	2.33
cycles	2.60	2.70	2.33	2.33	0.50	2.50	2.60	0.50	0.50	0.50	2.60	2.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	5.17
Dispatch	2.70
Data deps.	0.00
Overall L1	5.17

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	36%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	75%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	18%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	17%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.17 cycles. At this rate:

5% of peak load performance is reached (10.84 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.55 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 511214

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVSD %XMM0,(%R13,%R8,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RSI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
LEA 0x1(%RDI),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 511d00 <hypre_CSRMatrixMatvecOutOfPlace.extracted+0x1010>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%R12,%RDI,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x28(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RAX,%R8,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RBX,%R8,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RBX,%R8,8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R11,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JLE 511200 <hypre_CSRMatrixMatvecOutOfPlace.extracted+0x510>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 5112c0 <hypre_CSRMatrixMatvecOutOfPlace.extracted+0x5d0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%R10),%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R14,%R11,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RDX,%R11,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VEXTRACTF128 $0x1,%YMM1,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM2,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM2,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
CMP %R10,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x38(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 511200 <hypre_CSRMatrixMatvecOutOfPlace.extracted+0x510>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check