OV - exec - Loop 3596

	Loop Id: 3596	Module: exec	Source: par_csr_matop.c:937-989 [...]	Coverage: 0.31%

0x4e7900 INC	%RSI

0x4e7903 MOV	-0x60(%RBP),%RDX

0x4e7907 MOV	-0x48(%RBP),%R8

0x4e790b CMP	(%RDX,%R8,8),%RSI

0x4e790f JGE	4e7640

0x4e7915 MOV	-0xc8(%RBP),%RDX

0x4e791c MOV	(%RDX,%RSI,8),%R8

0x4e7920 MOV	-0xc0(%RBP),%RDX

0x4e7927 VMOVSD	(%RDX,%RSI,8),%XMM0

0x4e792c MOV	-0x80(%RBP),%RDX

0x4e7930 MOV	(%RDX,%R8,8),%R9

0x4e7934 MOV	0x8(%RDX,%R8,8),%R10

0x4e7939 CMP	%R10,%R9

0x4e793c JL	4e7966

0x4e793e JMP	4e799b

  (3598) 0x4e7940 MOV	%RAX,(%RDI,%RDX,8)

  (3598) 0x4e7944 VMOVSD	%XMM1,(%R12,%RAX,8)

  (3598) 0x4e794a MOV	-0x50(%RBP),%R10

  (3598) 0x4e794e MOV	%RDX,(%R10,%RAX,8)

  (3598) 0x4e7952 INC	%RAX

  (3598) 0x4e7955 MOV	-0x80(%RBP),%RDX

  (3598) 0x4e7959 MOV	0x8(%RDX,%R8,8),%R10

  (3598) 0x4e795e INC	%R9

  (3598) 0x4e7961 CMP	%R10,%R9

  (3598) 0x4e7964 JGE	4e799b

  (3598) 0x4e7966 MOV	-0x110(%RBP),%RDX

  (3598) 0x4e796d MOV	(%RDX,%R9,8),%RDX

  (3598) 0x4e7971 MOV	(%RDI,%RDX,8),%R11

  (3598) 0x4e7975 MOV	-0x108(%RBP),%R14

  (3598) 0x4e797c VMULSD	(%R14,%R9,8),%XMM0,%XMM1

  (3598) 0x4e7982 CMP	%RBX,%R11

  (3598) 0x4e7985 JL	4e7940

  (3598) 0x4e7987 VADDSD	(%R12,%R11,8),%XMM1,%XMM1

  (3598) 0x4e798d VMOVSD	%XMM1,(%R12,%R11,8)

  (3598) 0x4e7993 INC	%R9

  (3598) 0x4e7996 CMP	%R10,%R9

  (3598) 0x4e7999 JL	4e7966

0x4e799b CMPQ	$0,-0xb8(%RBP)

0x4e79a3 JE	4e7900

0x4e79a9 MOV	-0x68(%RBP),%RDX

0x4e79ad MOV	(%RDX,%R8,8),%R9

0x4e79b1 MOV	0x8(%RDX,%R8,8),%R10

0x4e79b6 JMP	4e79d5

  (3597) 0x4e79c0 VADDSD	(%R13,%R15,8),%XMM1,%XMM1

  (3597) 0x4e79c7 VMOVSD	%XMM1,(%R13,%R15,8)

  (3597) 0x4e79ce MOV	-0x40(%RBP),%R15

  (3597) 0x4e79d2 INC	%R9

  (3597) 0x4e79d5 CMP	%R10,%R9

  (3597) 0x4e79d8 JGE	4e7900

  (3597) 0x4e79de MOV	-0xd8(%RBP),%RDX

  (3597) 0x4e79e5 MOV	(%RDX,%R9,8),%RDX

  (3597) 0x4e79e9 MOV	-0xe0(%RBP),%R11

  (3597) 0x4e79f0 MOV	(%R11,%RDX,8),%RDX

  (3597) 0x4e79f4 LEA	(%RDX,%R15,1),%R11

  (3597) 0x4e79f8 MOV	(%RDI,%R11,8),%R15

  (3597) 0x4e79fc MOV	-0xd0(%RBP),%R14

  (3597) 0x4e7a03 VMULSD	(%R14,%R9,8),%XMM0,%XMM1

  (3597) 0x4e7a09 CMP	-0x30(%RBP),%R15

  (3597) 0x4e7a0d JGE	4e79c0

  (3597) 0x4e7a0f MOV	%RCX,(%RDI,%R11,8)

  (3597) 0x4e7a13 VMOVSD	%XMM1,(%R13,%RCX,8)

  (3597) 0x4e7a1a MOV	-0x88(%RBP),%R10

  (3597) 0x4e7a21 MOV	%RDX,(%R10,%RCX,8)

  (3597) 0x4e7a25 INC	%RCX

  (3597) 0x4e7a28 MOV	-0x68(%RBP),%RDX

  (3597) 0x4e7a2c MOV	0x8(%RDX,%R8,8),%R10

  (3597) 0x4e7a31 JMP	4e79ce

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 937 - 989

--------------------------------------------------------------------------------

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

971:             {

972:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

980:                if (B_marker[i3] < jj_row_begin_offd)

981:                {

982:                   B_marker[i3] = jj_count_offd;

983:                   C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3];

984:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

985:                   jj_count_offd++;

986:                }

987:                else

988:                {

989:                   C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3];

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	3.11
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.27
Bottlenecks	P2, P3, P11,
Function	hypre_ParMatmul.extracted.12
Source	par_csr_matop.c:937-940,par_csr_matop.c:946-946,par_csr_matop.c:968-970
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.67
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	4.67
CQA cycles if fully vectorized	0.58
Front-end cycles	3.67
P0 cycles	1.50
P1 cycles	1.00
P2 cycles	4.67
P3 cycles	4.67
P4 cycles	0.00
P5 cycles	1.00
P6 cycles	1.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	4.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	14.00
Nb stores	0.00
Nb stack references	7.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	3.11
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.27
Bottlenecks	P2, P3, P11,
Function	hypre_ParMatmul.extracted.12
Source	par_csr_matop.c:937-940,par_csr_matop.c:946-946,par_csr_matop.c:968-970
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.67
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	4.67
CQA cycles if fully vectorized	0.58
Front-end cycles	3.67
P0 cycles	1.50
P1 cycles	1.00
P2 cycles	4.67
P3 cycles	4.67
P4 cycles	0.00
P5 cycles	1.00
P6 cycles	1.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	4.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	14.00
Nb stores	0.00
Nb stack references	7.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul.extracted.12
Source file and lines	par_csr_matop.c:937-989
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:937-940,946-948,956-972,980-989.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:937-940,946,968-970.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=12
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 12 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.67 to 1.50 cycles (3.11x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.67 to 0.58 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by reading data from caches/RAM (load units are a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.67 to 3.67 cycles (1.27x speedup).

Workaround

Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 112 bytes.

General properties

nb instructions	21
nb uops	21
loop length	93
used x86 registers	6
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.67 cycles
front end	3.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.50	1.00	4.67	4.67	0.00	1.00	1.50	0.00	0.00	0.00	1.00	4.67
cycles	1.50	1.00	4.67	4.67	0.00	1.00	1.50	0.00	0.00	0.00	1.00	4.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.67
Dispatch	4.67
Overall L1	4.67

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.67 cycles. At this rate:

12% of peak load performance is reached (24.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4e7915

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
INC %RSI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x60(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP (%RDX,%R8,8),%RSI	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JGE 4e7640 <hypre_ParMatmul.extracted.12+0x2c0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0xc8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RSI,8),%R8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0xc0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RDX,%RSI,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x80(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%R8,8),%R9	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%RDX,%R8,8),%R10	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %R10,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JL 4e7966 <hypre_ParMatmul.extracted.12+0x5e6>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
JMP 4e799b <hypre_ParMatmul.extracted.12+0x61b>	1	0	0	0	0	0	0	0	0	0	5.84	N/A
CMPQ $0,-0xb8(%RBP)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	N/A
JE 4e7900 <hypre_ParMatmul.extracted.12+0x580>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x68(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%R8,8),%R9	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%RDX,%R8,8),%R10	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 4e79d5 <hypre_ParMatmul.extracted.12+0x655>	1	0	0	0	0	0	0	0	0	0	5.84	N/A

Function	hypre_ParMatmul.extracted.12
Source file and lines	par_csr_matop.c:937-989
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=12
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.67 to 1.50 cycles (3.11x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.67 to 0.58 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 112 bytes.

General properties

nb instructions	21
nb uops	21
loop length	93
used x86 registers	6
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.67 cycles
front end	3.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.50	1.00	4.67	4.67	0.00	1.00	1.50	0.00	0.00	0.00	1.00	4.67
cycles	1.50	1.00	4.67	4.67	0.00	1.00	1.50	0.00	0.00	0.00	1.00	4.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.67
Dispatch	4.67
Overall L1	4.67

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.67 cycles. At this rate:

12% of peak load performance is reached (24.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4e7915

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
INC %RSI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x60(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP (%RDX,%R8,8),%RSI	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JGE 4e7640 <hypre_ParMatmul.extracted.12+0x2c0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0xc8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RSI,8),%R8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0xc0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RDX,%RSI,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x80(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%R8,8),%R9	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%RDX,%R8,8),%R10	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %R10,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JL 4e7966 <hypre_ParMatmul.extracted.12+0x5e6>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
JMP 4e799b <hypre_ParMatmul.extracted.12+0x61b>	1	0	0	0	0	0	0	0	0	0	5.84	N/A
CMPQ $0,-0xb8(%RBP)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	N/A
JE 4e7900 <hypre_ParMatmul.extracted.12+0x580>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x68(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%R8,8),%R9	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%RDX,%R8,8),%R10	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 4e79d5 <hypre_ParMatmul.extracted.12+0x655>	1	0	0	0	0	0	0	0	0	0	5.84	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code