OV - exec - Loop 3595

	Loop Id: 3595	Module: exec	Source: par_csr_matop.c:865-989 [...]	Coverage: 0.03%

0x4e7640 MOV	%RCX,-0x30(%RBP)

0x4e7644 MOV	%RAX,%RBX

0x4e7647 CMP	-0x38(%RBP),%R8

0x4e764b JGE	4e7a40

0x4e7651 MOV	%R8,%RSI

0x4e7654 CMPQ	$0,-0x98(%RBP)

0x4e765c JE	4e7676

0x4e765e MOV	%RBX,(%RDI,%RSI,8)

0x4e7662 MOVQ	$0,(%R12,%RBX,8)

0x4e766a MOV	-0x50(%RBP),%RAX

0x4e766e MOV	%RSI,(%RAX,%RBX,8)

0x4e7672 LEA	0x1(%RBX),%RAX

0x4e7676 CMPQ	$0,-0x90(%RBP)

0x4e767e JE	4e7880

0x4e7684 MOV	-0x58(%RBP),%RCX

0x4e7688 MOV	(%RCX,%RSI,8),%R10

0x4e768c LEA	0x1(%RSI),%R8

0x4e7690 CMP	0x8(%RCX,%RSI,8),%R10

0x4e7695 JGE	4e7884

0x4e769b MOV	%R8,-0x48(%RBP)

0x4e769f MOV	-0x30(%RBP),%RCX

0x4e76a3 MOV	%RSI,-0xb0(%RBP)

0x4e76aa JMP	4e76dc

  (3599) 0x4e76c0 MOV	%R14,%R10

  (3599) 0x4e76c3 INC	%R10

  (3599) 0x4e76c6 MOV	-0x58(%RBP),%RDX

  (3599) 0x4e76ca MOV	-0xb0(%RBP),%RSI

  (3599) 0x4e76d1 CMP	0x8(%RDX,%RSI,8),%R10

  (3599) 0x4e76d6 JGE	4e78c0

  (3599) 0x4e76dc MOV	-0xa0(%RBP),%RDX

  (3599) 0x4e76e3 MOV	(%RDX,%R10,8),%R9

  (3599) 0x4e76e7 MOV	-0xa8(%RBP),%RDX

  (3599) 0x4e76ee MOV	%R10,%R14

  (3599) 0x4e76f1 VMOVSD	(%RDX,%R10,8),%XMM0

  (3599) 0x4e76f7 MOV	-0x78(%RBP),%RDX

  (3599) 0x4e76fb MOV	(%RDX,%R9,8),%R10

  (3599) 0x4e76ff MOV	0x8(%RDX,%R9,8),%R11

  (3599) 0x4e7704 JMP	4e7755

    (3601) 0x4e7740 VADDSD	(%R13,%R8,8),%XMM1,%XMM1

    (3601) 0x4e7747 VMOVSD	%XMM1,(%R13,%R8,8)

    (3601) 0x4e774e MOV	-0x40(%RBP),%R15

    (3601) 0x4e7752 INC	%R10

    (3601) 0x4e7755 CMP	%R11,%R10

    (3601) 0x4e7758 JGE	4e77c0

    (3601) 0x4e775a MOV	-0x100(%RBP),%RDX

    (3601) 0x4e7761 MOV	(%RDX,%R10,8),%RSI

    (3601) 0x4e7765 LEA	(%RSI,%R15,1),%RDX

    (3601) 0x4e7769 MOV	(%RDI,%RDX,8),%R8

    (3601) 0x4e776d MOV	-0xf8(%RBP),%R15

    (3601) 0x4e7774 VMULSD	(%R15,%R10,8),%XMM0,%XMM1

    (3601) 0x4e777a CMP	-0x30(%RBP),%R8

    (3601) 0x4e777e JGE	4e7740

    (3601) 0x4e7780 MOV	%RCX,(%RDI,%RDX,8)

    (3601) 0x4e7784 VMOVSD	%XMM1,(%R13,%RCX,8)

    (3601) 0x4e778b MOV	-0x88(%RBP),%RDX

    (3601) 0x4e7792 MOV	%RSI,(%RDX,%RCX,8)

    (3601) 0x4e7796 INC	%RCX

    (3601) 0x4e7799 MOV	-0x78(%RBP),%RDX

    (3601) 0x4e779d MOV	0x8(%RDX,%R9,8),%R11

    (3601) 0x4e77a2 JMP	4e774e

  (3599) 0x4e77c0 MOV	-0x70(%RBP),%RDX

  (3599) 0x4e77c4 MOV	(%RDX,%R9,8),%R10

  (3599) 0x4e77c8 MOV	0x8(%RDX,%R9,8),%R11

  (3599) 0x4e77cd CMP	%R11,%R10

  (3599) 0x4e77d0 JL	4e782a

  (3599) 0x4e77d2 JMP	4e76c0

    (3600) 0x4e7800 MOV	%RAX,(%RDI,%RSI,8)

    (3600) 0x4e7804 VMOVSD	%XMM1,(%R12,%RAX,8)

    (3600) 0x4e780a MOV	-0x50(%RBP),%RDX

    (3600) 0x4e780e MOV	%RSI,(%RDX,%RAX,8)

    (3600) 0x4e7812 INC	%RAX

    (3600) 0x4e7815 MOV	-0x70(%RBP),%RDX

    (3600) 0x4e7819 MOV	0x8(%RDX,%R9,8),%R11

    (3600) 0x4e781e INC	%R10

    (3600) 0x4e7821 CMP	%R11,%R10

    (3600) 0x4e7824 JGE	4e76c0

    (3600) 0x4e782a MOV	-0xf0(%RBP),%RDX

    (3600) 0x4e7831 MOV	(%RDX,%R10,8),%RSI

    (3600) 0x4e7835 MOV	(%RDI,%RSI,8),%RDX

    (3600) 0x4e7839 MOV	-0xe8(%RBP),%R8

    (3600) 0x4e7840 VMULSD	(%R8,%R10,8),%XMM0,%XMM1

    (3600) 0x4e7846 CMP	%RBX,%RDX

    (3600) 0x4e7849 JL	4e7800

    (3600) 0x4e784b VADDSD	(%R12,%RDX,8),%XMM1,%XMM1

    (3600) 0x4e7851 VMOVSD	%XMM1,(%R12,%RDX,8)

    (3600) 0x4e7857 INC	%R10

    (3600) 0x4e785a CMP	%R11,%R10

    (3600) 0x4e785d JL	4e782a

  (3599) 0x4e785f JMP	4e76c0

0x4e7880 LEA	0x1(%RSI),%R8

0x4e7884 MOV	-0x30(%RBP),%RCX

0x4e7888 MOV	-0x60(%RBP),%RDX

0x4e788c MOV	(%RDX,%RSI,8),%RSI

0x4e7890 CMP	(%RDX,%R8,8),%RSI

0x4e7894 JGE	4e7640

0x4e789a JMP	4e78d6

0x4e78c0 MOV	-0x48(%RBP),%R8

0x4e78c4 MOV	-0x60(%RBP),%RDX

0x4e78c8 MOV	(%RDX,%RSI,8),%RSI

0x4e78cc CMP	(%RDX,%R8,8),%RSI

0x4e78d0 JGE	4e7640

0x4e78d6 MOV	%R8,-0x48(%RBP)

0x4e78da JMP	4e7915

  (3596) 0x4e7900 INC	%RSI

  (3596) 0x4e7903 MOV	-0x60(%RBP),%RDX

  (3596) 0x4e7907 MOV	-0x48(%RBP),%R8

  (3596) 0x4e790b CMP	(%RDX,%R8,8),%RSI

  (3596) 0x4e790f JGE	4e7640

  (3596) 0x4e7915 MOV	-0xc8(%RBP),%RDX

  (3596) 0x4e791c MOV	(%RDX,%RSI,8),%R8

  (3596) 0x4e7920 MOV	-0xc0(%RBP),%RDX

  (3596) 0x4e7927 VMOVSD	(%RDX,%RSI,8),%XMM0

  (3596) 0x4e792c MOV	-0x80(%RBP),%RDX

  (3596) 0x4e7930 MOV	(%RDX,%R8,8),%R9

  (3596) 0x4e7934 MOV	0x8(%RDX,%R8,8),%R10

  (3596) 0x4e7939 CMP	%R10,%R9

  (3596) 0x4e793c JL	4e7966

  (3596) 0x4e793e JMP	4e799b

    (3598) 0x4e7940 MOV	%RAX,(%RDI,%RDX,8)

    (3598) 0x4e7944 VMOVSD	%XMM1,(%R12,%RAX,8)

    (3598) 0x4e794a MOV	-0x50(%RBP),%R10

    (3598) 0x4e794e MOV	%RDX,(%R10,%RAX,8)

    (3598) 0x4e7952 INC	%RAX

    (3598) 0x4e7955 MOV	-0x80(%RBP),%RDX

    (3598) 0x4e7959 MOV	0x8(%RDX,%R8,8),%R10

    (3598) 0x4e795e INC	%R9

    (3598) 0x4e7961 CMP	%R10,%R9

    (3598) 0x4e7964 JGE	4e799b

    (3598) 0x4e7966 MOV	-0x110(%RBP),%RDX

    (3598) 0x4e796d MOV	(%RDX,%R9,8),%RDX

    (3598) 0x4e7971 MOV	(%RDI,%RDX,8),%R11

    (3598) 0x4e7975 MOV	-0x108(%RBP),%R14

    (3598) 0x4e797c VMULSD	(%R14,%R9,8),%XMM0,%XMM1

    (3598) 0x4e7982 CMP	%RBX,%R11

    (3598) 0x4e7985 JL	4e7940

    (3598) 0x4e7987 VADDSD	(%R12,%R11,8),%XMM1,%XMM1

    (3598) 0x4e798d VMOVSD	%XMM1,(%R12,%R11,8)

    (3598) 0x4e7993 INC	%R9

    (3598) 0x4e7996 CMP	%R10,%R9

    (3598) 0x4e7999 JL	4e7966

  (3596) 0x4e799b CMPQ	$0,-0xb8(%RBP)

  (3596) 0x4e79a3 JE	4e7900

  (3596) 0x4e79a9 MOV	-0x68(%RBP),%RDX

  (3596) 0x4e79ad MOV	(%RDX,%R8,8),%R9

  (3596) 0x4e79b1 MOV	0x8(%RDX,%R8,8),%R10

  (3596) 0x4e79b6 JMP	4e79d5

    (3597) 0x4e79c0 VADDSD	(%R13,%R15,8),%XMM1,%XMM1

    (3597) 0x4e79c7 VMOVSD	%XMM1,(%R13,%R15,8)

    (3597) 0x4e79ce MOV	-0x40(%RBP),%R15

    (3597) 0x4e79d2 INC	%R9

    (3597) 0x4e79d5 CMP	%R10,%R9

    (3597) 0x4e79d8 JGE	4e7900

    (3597) 0x4e79de MOV	-0xd8(%RBP),%RDX

    (3597) 0x4e79e5 MOV	(%RDX,%R9,8),%RDX

    (3597) 0x4e79e9 MOV	-0xe0(%RBP),%R11

    (3597) 0x4e79f0 MOV	(%R11,%RDX,8),%RDX

    (3597) 0x4e79f4 LEA	(%RDX,%R15,1),%R11

    (3597) 0x4e79f8 MOV	(%RDI,%R11,8),%R15

    (3597) 0x4e79fc MOV	-0xd0(%RBP),%R14

    (3597) 0x4e7a03 VMULSD	(%R14,%R9,8),%XMM0,%XMM1

    (3597) 0x4e7a09 CMP	-0x30(%RBP),%R15

    (3597) 0x4e7a0d JGE	4e79c0

    (3597) 0x4e7a0f MOV	%RCX,(%RDI,%R11,8)

    (3597) 0x4e7a13 VMOVSD	%XMM1,(%R13,%RCX,8)

    (3597) 0x4e7a1a MOV	-0x88(%RBP),%R10

    (3597) 0x4e7a21 MOV	%RDX,(%R10,%RCX,8)

    (3597) 0x4e7a25 INC	%RCX

    (3597) 0x4e7a28 MOV	-0x68(%RBP),%RDX

    (3597) 0x4e7a2c MOV	0x8(%RDX,%R8,8),%R10

    (3597) 0x4e7a31 JMP	4e79ce

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 865 - 989

--------------------------------------------------------------------------------

865:     for (i1 = ns; i1 < ne; i1++)

[...]

874:       if ( allsquare )

875:       {

876:          B_marker[i1] = jj_count_diag;

877:          C_diag_data[jj_count_diag] = zero;

878:          C_diag_j[jj_count_diag] = i1;

879:          jj_count_diag++;

[...]

886:       if (num_cols_offd_A)

887:       {

888:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

889:          {

890:             i2 = A_offd_j[jj2];

891:             a_entry = A_offd_data[jj2];

[...]

897:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

898:             {

899:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

907:                if (B_marker[i3] < jj_row_begin_offd)

908:                {

909:                   B_marker[i3] = jj_count_offd;

910:                   C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3];

911:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

912:                   jj_count_offd++;

913:                }

914:                else

915:                   C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3];

916:             }

917:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

918:             {

919:                i3 = B_ext_diag_j[jj3];

920:                if (B_marker[i3] < jj_row_begin_diag)

921:                {

922:                   B_marker[i3] = jj_count_diag;

923:                   C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3];

924:                   C_diag_j[jj_count_diag] = i3;

925:                   jj_count_diag++;

926:                }

927:                else

928:                   C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3];

[...]

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

971:             {

972:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

980:                if (B_marker[i3] < jj_row_begin_offd)

981:                {

982:                   B_marker[i3] = jj_count_offd;

983:                   C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3];

984:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

985:                   jj_count_offd++;

986:                }

987:                else

988:                {

989:                   C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3];

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.08
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue,
Function	hypre_ParMatmul.extracted.12
Source	par_csr_matop.c:865-865,par_csr_matop.c:874-879,par_csr_matop.c:886-888,par_csr_matop.c:937-937
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.67
CQA cycles if no scalar integer	6.67
CQA cycles if FP arith vectorized	6.67
CQA cycles if fully vectorized	0.55
Front-end cycles	6.67
P0 cycles	3.00
P1 cycles	2.00
P2 cycles	5.33
P3 cycles	5.33
P4 cycles	3.50
P5 cycles	2.00
P6 cycles	3.00
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	2.00
P11 cycles	5.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	16.00
Nb stores	7.00
Nb stack references	9.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.60
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.02
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	11.61
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.08
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue,
Function	hypre_ParMatmul.extracted.12
Source	par_csr_matop.c:865-865,par_csr_matop.c:874-879,par_csr_matop.c:886-888,par_csr_matop.c:937-937
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.67
CQA cycles if no scalar integer	6.67
CQA cycles if FP arith vectorized	6.67
CQA cycles if fully vectorized	0.55
Front-end cycles	6.67
P0 cycles	3.00
P1 cycles	2.00
P2 cycles	5.33
P3 cycles	5.33
P4 cycles	3.50
P5 cycles	2.00
P6 cycles	3.00
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	2.00
P11 cycles	5.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	16.00
Nb stores	7.00
Nb stack references	9.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.60
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.02
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	11.61
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul.extracted.12
Source file and lines	par_csr_matop.c:865-989
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,874-879,886-891,897-899,907-928,937-940,946-948,956-972,980-989.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,874-879,886-888,937.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 134 paths individually, rerun with max-paths=134
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 134 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.67 to 0.55 cycles (12.08x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 128 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	37
nb uops	37
loop length	164
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.67 cycles
front end	6.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.00	2.00	5.33	5.33	3.50	2.00	3.00	3.50	3.50	3.50	2.00	5.33
cycles	3.00	2.00	5.33	5.33	3.50	2.00	3.00	3.50	3.50	3.50	2.00	5.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.67
Dispatch	5.33
Overall L1	6.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.67 cycles. At this rate:

10% of peak load performance is reached (19.20 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.67 to 5.33 cycles (1.25x speedup).

ASM code

In the binary file, the address of the loop is: 4e7651

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP -0x38(%RBP),%R8	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 4e7a40 <hypre_ParMatmul.extracted.12+0x6c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMPQ $0,-0x98(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 4e7676 <hypre_ParMatmul.extracted.12+0x2f6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,(%RDI,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0,(%R12,%RBX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV -0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,(%RAX,%RBX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%RBX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMPQ $0,-0x90(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 4e7880 <hypre_ParMatmul.extracted.12+0x500>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x58(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RSI,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RSI),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP 0x8(%RCX,%RSI,8),%R10	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 4e7884 <hypre_ParMatmul.extracted.12+0x504>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 4e76dc <hypre_ParMatmul.extracted.12+0x35c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
LEA 0x1(%RSI),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x60(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RSI,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP (%RDX,%R8,8),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 4e7640 <hypre_ParMatmul.extracted.12+0x2c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 4e78d6 <hypre_ParMatmul.extracted.12+0x556>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0x48(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x60(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RSI,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP (%RDX,%R8,8),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JGE 4e7640 <hypre_ParMatmul.extracted.12+0x2c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 4e7915 <hypre_ParMatmul.extracted.12+0x595>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Function	hypre_ParMatmul.extracted.12
Source file and lines	par_csr_matop.c:865-989
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 134 paths individually, rerun with max-paths=134
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 128 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	37
nb uops	37
loop length	164
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.67 cycles
front end	6.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.00	2.00	5.33	5.33	3.50	2.00	3.00	3.50	3.50	3.50	2.00	5.33
cycles	3.00	2.00	5.33	5.33	3.50	2.00	3.00	3.50	3.50	3.50	2.00	5.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.67
Dispatch	5.33
Overall L1	6.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.67 cycles. At this rate:

10% of peak load performance is reached (19.20 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4e7651

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP -0x38(%RBP),%R8	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 4e7a40 <hypre_ParMatmul.extracted.12+0x6c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMPQ $0,-0x98(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 4e7676 <hypre_ParMatmul.extracted.12+0x2f6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,(%RDI,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0,(%R12,%RBX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV -0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,(%RAX,%RBX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%RBX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMPQ $0,-0x90(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 4e7880 <hypre_ParMatmul.extracted.12+0x500>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x58(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RSI,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RSI),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP 0x8(%RCX,%RSI,8),%R10	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 4e7884 <hypre_ParMatmul.extracted.12+0x504>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 4e76dc <hypre_ParMatmul.extracted.12+0x35c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
LEA 0x1(%RSI),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x60(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RSI,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP (%RDX,%R8,8),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 4e7640 <hypre_ParMatmul.extracted.12+0x2c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 4e78d6 <hypre_ParMatmul.extracted.12+0x556>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0x48(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x60(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RSI,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP (%RDX,%R8,8),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JGE 4e7640 <hypre_ParMatmul.extracted.12+0x2c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 4e7915 <hypre_ParMatmul.extracted.12+0x595>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code