OV - exec - Loop 3571

	Loop Id: 3571	Module: exec	Source: par_csr_matop.c:109-231 [...]	Coverage: 0.59%

0x4e6080 MOV	-0x30(%RBP),%R11

0x4e6084 CMP	%R11,%R12

0x4e6087 LEA	0x1(%R12),%R12

0x4e608c MOV	-0x38(%RBP),%R13

0x4e6090 JE	4e5ac0

0x4e6096 LEA	(%R13,%R12,1),%RAX

0x4e609b MOV	-0x78(%RBP),%RCX

0x4e609f MOV	(%RCX,%RAX,8),%RDI

0x4e60a3 MOV	0x20(%RBP),%RCX

0x4e60a7 MOV	(%RCX,%RDI,8),%RAX

0x4e60ab MOV	0x8(%RCX,%RDI,8),%R13

0x4e60b0 MOV	%R13,%R9

0x4e60b3 SUB	%RAX,%R9

0x4e60b6 JLE	4e6284

0x4e60bc CMP	$0x8,%R9

0x4e60c0 JAE	4e6140

0x4e60c6 MOV	%R9,%RCX

0x4e60c9 AND	$-0x8,%RCX

0x4e60cd CMP	%R9,%RCX

0x4e60d0 JAE	4e6280

0x4e60d6 ADD	%RCX,%RAX

0x4e60d9 MOV	0x28(%RBP),%RSI

0x4e60dd MOV	-0x30(%RBP),%R11

0x4e60e1 JMP	4e610c

  (3574) 0x4e6100 INC	%RAX

  (3574) 0x4e6103 CMP	%RAX,%R13

  (3574) 0x4e6106 JE	4e6284

  (3574) 0x4e610c MOV	(%RSI,%RAX,8),%RCX

  (3574) 0x4e6110 CMP	%R8,(%R14,%RCX,8)

  (3574) 0x4e6114 JGE	4e6100

  (3574) 0x4e6116 MOV	%RBX,(%R14,%RCX,8)

  (3574) 0x4e611a INC	%RBX

  (3574) 0x4e611d JMP	4e6100

0x4e6140 MOV	%R9,%RCX

0x4e6143 SHR	$0x3,%RCX

0x4e6147 MOV	-0x70(%RBP),%RSI

0x4e614b LEA	(%RSI,%RAX,8),%R11

0x4e614f JMP	4e618d

  (3575) 0x4e6180 ADD	$0x40,%R11

  (3575) 0x4e6184 DEC	%RCX

  (3575) 0x4e6187 JE	4e60c6

  (3575) 0x4e618d MOV	-0x38(%R11),%RSI

  (3575) 0x4e6191 CMP	%R8,(%R14,%RSI,8)

  (3575) 0x4e6195 JGE	4e6200

  (3575) 0x4e6197 MOV	%RBX,(%R14,%RSI,8)

  (3575) 0x4e619b INC	%RBX

  (3575) 0x4e619e MOV	-0x30(%R11),%RSI

  (3575) 0x4e61a2 CMP	%R8,(%R14,%RSI,8)

  (3575) 0x4e61a6 JL	4e620a

  (3575) 0x4e61a8 MOV	-0x28(%R11),%RSI

  (3575) 0x4e61ac CMP	%R8,(%R14,%RSI,8)

  (3575) 0x4e61b0 JGE	4e621b

  (3575) 0x4e61b2 MOV	%RBX,(%R14,%RSI,8)

  (3575) 0x4e61b6 INC	%RBX

  (3575) 0x4e61b9 MOV	-0x20(%R11),%RSI

  (3575) 0x4e61bd CMP	%R8,(%R14,%RSI,8)

  (3575) 0x4e61c1 JL	4e6225

  (3575) 0x4e61c3 MOV	-0x18(%R11),%RSI

  (3575) 0x4e61c7 CMP	%R8,(%R14,%RSI,8)

  (3575) 0x4e61cb JGE	4e6236

  (3575) 0x4e61cd MOV	%RBX,(%R14,%RSI,8)

  (3575) 0x4e61d1 INC	%RBX

  (3575) 0x4e61d4 MOV	-0x10(%R11),%RSI

  (3575) 0x4e61d8 CMP	%R8,(%R14,%RSI,8)

  (3575) 0x4e61dc JL	4e6240

  (3575) 0x4e61de MOV	-0x8(%R11),%RSI

  (3575) 0x4e61e2 CMP	%R8,(%R14,%RSI,8)

  (3575) 0x4e61e6 JGE	4e6251

  (3575) 0x4e61e8 MOV	%RBX,(%R14,%RSI,8)

  (3575) 0x4e61ec INC	%RBX

  (3575) 0x4e61ef MOV	(%R11),%RSI

  (3575) 0x4e61f2 CMP	%R8,(%R14,%RSI,8)

  (3575) 0x4e61f6 JGE	4e6180

  (3575) 0x4e61f8 JMP	4e625e

  (3575) 0x4e6200 MOV	-0x30(%R11),%RSI

  (3575) 0x4e6204 CMP	%R8,(%R14,%RSI,8)

  (3575) 0x4e6208 JGE	4e61a8

  (3575) 0x4e620a MOV	%RBX,(%R14,%RSI,8)

  (3575) 0x4e620e INC	%RBX

  (3575) 0x4e6211 MOV	-0x28(%R11),%RSI

  (3575) 0x4e6215 CMP	%R8,(%R14,%RSI,8)

  (3575) 0x4e6219 JL	4e61b2

  (3575) 0x4e621b MOV	-0x20(%R11),%RSI

  (3575) 0x4e621f CMP	%R8,(%R14,%RSI,8)

  (3575) 0x4e6223 JGE	4e61c3

  (3575) 0x4e6225 MOV	%RBX,(%R14,%RSI,8)

  (3575) 0x4e6229 INC	%RBX

  (3575) 0x4e622c MOV	-0x18(%R11),%RSI

  (3575) 0x4e6230 CMP	%R8,(%R14,%RSI,8)

  (3575) 0x4e6234 JL	4e61cd

  (3575) 0x4e6236 MOV	-0x10(%R11),%RSI

  (3575) 0x4e623a CMP	%R8,(%R14,%RSI,8)

  (3575) 0x4e623e JGE	4e61de

  (3575) 0x4e6240 MOV	%RBX,(%R14,%RSI,8)

  (3575) 0x4e6244 INC	%RBX

  (3575) 0x4e6247 MOV	-0x8(%R11),%RSI

  (3575) 0x4e624b CMP	%R8,(%R14,%RSI,8)

  (3575) 0x4e624f JL	4e61e8

  (3575) 0x4e6251 MOV	(%R11),%RSI

  (3575) 0x4e6254 CMP	%R8,(%R14,%RSI,8)

  (3575) 0x4e6258 JGE	4e6180

  (3575) 0x4e625e MOV	%RBX,(%R14,%RSI,8)

  (3575) 0x4e6262 INC	%RBX

  (3575) 0x4e6265 JMP	4e6180

0x4e6280 MOV	-0x30(%RBP),%R11

0x4e6284 MOV	0x30(%RBP),%RCX

0x4e6288 MOV	(%RCX,%RDI,8),%RAX

0x4e628c MOV	0x8(%RCX,%RDI,8),%RCX

0x4e6291 MOV	%RCX,%RDI

0x4e6294 SUB	%RAX,%RDI

0x4e6297 JLE	4e6084

0x4e629d CMP	$0x4,%RDI

0x4e62a1 JAE	4e6340

0x4e62a7 MOV	0x60(%RBP),%R13

0x4e62ab MOV	%RDI,%RSI

0x4e62ae AND	$-0x4,%RSI

0x4e62b2 CMP	%RDI,%RSI

0x4e62b5 JAE	4e6080

0x4e62bb ADD	%RSI,%RAX

0x4e62be MOV	0x38(%RBP),%RDI

0x4e62c2 MOV	-0x30(%RBP),%R11

0x4e62c6 JMP	4e630c

  (3572) 0x4e6300 INC	%RAX

  (3572) 0x4e6303 CMP	%RAX,%RCX

  (3572) 0x4e6306 JE	4e6084

  (3572) 0x4e630c MOV	(%RDI,%RAX,8),%RSI

  (3572) 0x4e6310 MOV	(%R13,%RSI,8),%RSI

  (3572) 0x4e6315 ADD	%R15,%RSI

  (3572) 0x4e6318 CMP	%R10,(%R14,%RSI,8)

  (3572) 0x4e631c JGE	4e6300

  (3572) 0x4e631e MOV	%RDX,(%R14,%RSI,8)

  (3572) 0x4e6322 INC	%RDX

  (3572) 0x4e6325 JMP	4e6300

0x4e6340 MOV	%RDI,%R9

0x4e6343 SHR	$0x2,%R9

0x4e6347 MOV	-0xc0(%RBP),%RSI

0x4e634e LEA	(%RSI,%RAX,8),%R11

0x4e6352 MOV	0x60(%RBP),%R13

0x4e6356 JMP	4e638d

  (3573) 0x4e6380 ADD	$0x20,%R11

  (3573) 0x4e6384 DEC	%R9

  (3573) 0x4e6387 JE	4e62ab

  (3573) 0x4e638d MOV	-0x18(%R11),%RSI

  (3573) 0x4e6391 MOV	(%R13,%RSI,8),%RSI

  (3573) 0x4e6396 ADD	%R15,%RSI

  (3573) 0x4e6399 CMP	%R10,(%R14,%RSI,8)

  (3573) 0x4e639d JGE	4e63a6

  (3573) 0x4e639f MOV	%RDX,(%R14,%RSI,8)

  (3573) 0x4e63a3 INC	%RDX

  (3573) 0x4e63a6 MOV	-0x10(%R11),%RSI

  (3573) 0x4e63aa MOV	(%R13,%RSI,8),%RSI

  (3573) 0x4e63af ADD	%R15,%RSI

  (3573) 0x4e63b2 CMP	%R10,(%R14,%RSI,8)

  (3573) 0x4e63b6 JGE	4e63bf

  (3573) 0x4e63b8 MOV	%RDX,(%R14,%RSI,8)

  (3573) 0x4e63bc INC	%RDX

  (3573) 0x4e63bf MOV	-0x8(%R11),%RSI

  (3573) 0x4e63c3 MOV	(%R13,%RSI,8),%RSI

  (3573) 0x4e63c8 ADD	%R15,%RSI

  (3573) 0x4e63cb CMP	%R10,(%R14,%RSI,8)

  (3573) 0x4e63cf JGE	4e63d8

  (3573) 0x4e63d1 MOV	%RDX,(%R14,%RSI,8)

  (3573) 0x4e63d5 INC	%RDX

  (3573) 0x4e63d8 MOV	(%R11),%RSI

  (3573) 0x4e63db MOV	(%R13,%RSI,8),%RSI

  (3573) 0x4e63e0 ADD	%R15,%RSI

  (3573) 0x4e63e3 CMP	%R10,(%R14,%RSI,8)

  (3573) 0x4e63e7 JGE	4e6380

  (3573) 0x4e63e9 MOV	%RDX,(%R14,%RSI,8)

  (3573) 0x4e63ed INC	%RDX

  (3573) 0x4e63f0 JMP	4e6380

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 109 - 231

--------------------------------------------------------------------------------

109:     if (ii < rest)

[...]

187:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

188:       {

189:          i2 = A_diag_j[jj2];

[...]

195:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

196:          {

197:             i3 = B_diag_j[jj3];

[...]

205:             if (B_marker[i3] < jj_row_begin_diag)

206:             {

207:                B_marker[i3] = jj_count_diag;

208:                jj_count_diag++;

[...]

216:          if (num_cols_offd_B)

217:          {

218:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

219:             {

220:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

228:                if (B_marker[i3] < jj_row_begin_offd)

229:                {

230:                   B_marker[i3] = jj_count_offd;

231:                   jj_count_offd++;

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.39
Bottlenecks	micro-operation queue,
Function	hypre_ParMatmul_RowSizes.extracted
Source	par_csr_matop.c:109-109,par_csr_matop.c:187-189,par_csr_matop.c:195-195,par_csr_matop.c:208-208,par_csr_matop.c:216-218
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.83
CQA cycles if no scalar integer	8.83
CQA cycles if FP arith vectorized	8.83
CQA cycles if fully vectorized	1.10
Front-end cycles	8.83
P0 cycles	4.50
P1 cycles	3.80
P2 cycles	6.33
P3 cycles	6.33
P4 cycles	0.00
P5 cycles	3.60
P6 cycles	4.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	3.60
P11 cycles	6.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	53.00
Nb uops	53.00
Nb loads	19.00
Nb stores	0.00
Nb stack references	10.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.21
Bytes prefetched	0.00
Bytes loaded	152.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.39
Bottlenecks	micro-operation queue,
Function	hypre_ParMatmul_RowSizes.extracted
Source	par_csr_matop.c:109-109,par_csr_matop.c:187-189,par_csr_matop.c:195-195,par_csr_matop.c:208-208,par_csr_matop.c:216-218
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.83
CQA cycles if no scalar integer	8.83
CQA cycles if FP arith vectorized	8.83
CQA cycles if fully vectorized	1.10
Front-end cycles	8.83
P0 cycles	4.50
P1 cycles	3.80
P2 cycles	6.33
P3 cycles	6.33
P4 cycles	0.00
P5 cycles	3.60
P6 cycles	4.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	3.60
P11 cycles	6.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	53.00
Nb uops	53.00
Nb loads	19.00
Nb stores	0.00
Nb stack references	10.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.21
Bytes prefetched	0.00
Bytes loaded	152.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul_RowSizes.extracted
Source file and lines	par_csr_matop.c:109-231
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:109,187-189,195-197,205-208,216-220,228-231.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:109,187-189,195,208,216-218.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 40144 paths individually, rerun with max-paths=40144
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 40144 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 8.83 to 1.10 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 152 bytes.

General properties

nb instructions	53
nb uops	53
loop length	212
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.83 cycles
front end	8.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.50	3.80	6.33	6.33	0.00	3.60	4.50	0.00	0.00	0.00	3.60	6.33
cycles	4.50	3.80	6.33	6.33	0.00	3.60	4.50	0.00	0.00	0.00	3.60	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.83
Dispatch	6.33
Overall L1	8.83

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.83 cycles. At this rate:

8% of peak load performance is reached (17.21 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.83 to 6.33 cycles (1.39x speedup).

ASM code

In the binary file, the address of the loop is: 4e6096

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x30(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %R11,%R12	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
LEA 0x1(%R12),%R12	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x38(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
JE 4e5ac0 <hypre_ParMatmul_RowSizes.extracted+0x2e0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
LEA (%R13,%R12,1),%RAX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x78(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RDI,8),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RCX,%RDI,8),%R13	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV %R13,%R9	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RAX,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JLE 4e6284 <hypre_ParMatmul_RowSizes.extracted+0xaa4>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP $0x8,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JAE 4e6140 <hypre_ParMatmul_RowSizes.extracted+0x960>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV %R9,%RCX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
CMP %R9,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JAE 4e6280 <hypre_ParMatmul_RowSizes.extracted+0xaa0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
ADD %RCX,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV 0x28(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 4e610c <hypre_ParMatmul_RowSizes.extracted+0x92c>	1	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %R9,%RCX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RCX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
MOV -0x70(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%RAX,8),%R11	1	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4e618d <hypre_ParMatmul_RowSizes.extracted+0x9ad>	1	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0x30(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RDI,8),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RCX,%RDI,8),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JLE 4e6084 <hypre_ParMatmul_RowSizes.extracted+0x8a4>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP $0x4,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JAE 4e6340 <hypre_ParMatmul_RowSizes.extracted+0xb60>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV 0x60(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RSI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
CMP %RDI,%RSI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JAE 4e6080 <hypre_ParMatmul_RowSizes.extracted+0x8a0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
ADD %RSI,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV 0x38(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 4e630c <hypre_ParMatmul_RowSizes.extracted+0xb2c>	1	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x2,%R9	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
MOV -0xc0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%RAX,8),%R11	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x60(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
JMP 4e638d <hypre_ParMatmul_RowSizes.extracted+0xbad>	1	0	0	0	0	0	0	0	0	0	5.84	N/A

Function	hypre_ParMatmul_RowSizes.extracted
Source file and lines	par_csr_matop.c:109-231
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 40144 paths individually, rerun with max-paths=40144
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 8.83 to 1.10 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 152 bytes.

General properties

nb instructions	53
nb uops	53
loop length	212
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.83 cycles
front end	8.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.50	3.80	6.33	6.33	0.00	3.60	4.50	0.00	0.00	0.00	3.60	6.33
cycles	4.50	3.80	6.33	6.33	0.00	3.60	4.50	0.00	0.00	0.00	3.60	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.83
Dispatch	6.33
Overall L1	8.83

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.83 cycles. At this rate:

8% of peak load performance is reached (17.21 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4e6096

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x30(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %R11,%R12	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
LEA 0x1(%R12),%R12	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x38(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
JE 4e5ac0 <hypre_ParMatmul_RowSizes.extracted+0x2e0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
LEA (%R13,%R12,1),%RAX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x78(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,8),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RDI,8),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RCX,%RDI,8),%R13	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV %R13,%R9	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RAX,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JLE 4e6284 <hypre_ParMatmul_RowSizes.extracted+0xaa4>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP $0x8,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JAE 4e6140 <hypre_ParMatmul_RowSizes.extracted+0x960>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV %R9,%RCX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
CMP %R9,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JAE 4e6280 <hypre_ParMatmul_RowSizes.extracted+0xaa0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
ADD %RCX,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV 0x28(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 4e610c <hypre_ParMatmul_RowSizes.extracted+0x92c>	1	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %R9,%RCX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RCX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
MOV -0x70(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%RAX,8),%R11	1	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4e618d <hypre_ParMatmul_RowSizes.extracted+0x9ad>	1	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0x30(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RDI,8),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RCX,%RDI,8),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JLE 4e6084 <hypre_ParMatmul_RowSizes.extracted+0x8a4>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP $0x4,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JAE 4e6340 <hypre_ParMatmul_RowSizes.extracted+0xb60>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV 0x60(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RSI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
CMP %RDI,%RSI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JAE 4e6080 <hypre_ParMatmul_RowSizes.extracted+0x8a0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
ADD %RSI,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV 0x38(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 4e630c <hypre_ParMatmul_RowSizes.extracted+0xb2c>	1	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x2,%R9	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
MOV -0xc0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%RAX,8),%R11	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x60(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
JMP 4e638d <hypre_ParMatmul_RowSizes.extracted+0xbad>	1	0	0	0	0	0	0	0	0	0	5.84	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code