OV - exec - Loop 3567

	Loop Id: 3567	Module: exec	Source: par_csr_matop.c:109-242 [...]	Coverage: 0.03%

0x4e5ac0 MOV	-0x98(%RBP),%RAX

0x4e5ac7 MOV	-0x68(%RBP),%RCX

0x4e5acb MOV	%R8,(%RAX,%RCX,8)

0x4e5acf MOV	-0x90(%RBP),%RAX

0x4e5ad6 MOV	%R10,(%RAX,%RCX,8)

0x4e5ada MOV	%RDX,%R10

0x4e5add MOV	%RBX,%R8

0x4e5ae0 MOV	-0xb8(%RBP),%RSI

0x4e5ae7 CMP	-0xa0(%RBP),%RSI

0x4e5aee LEA	0x1(%RSI),%RSI

0x4e5af2 JE	4e58a7

0x4e5af8 MOV	0x78(%RBP),%RAX

0x4e5afc TEST	%RAX,%RAX

0x4e5aff MOV	-0xa8(%RBP),%RCX

0x4e5b06 JE	4e5b14

0x4e5b08 LEA	(%RCX,%RSI,1),%RAX

0x4e5b0c MOV	%R8,(%R14,%RAX,8)

0x4e5b10 LEA	0x1(%R8),%RBX

0x4e5b14 ADD	%RSI,%RCX

0x4e5b17 CMPQ	$0,0x70(%RBP)

0x4e5b1c MOV	%RSI,-0xb8(%RBP)

0x4e5b23 MOV	%RCX,-0x68(%RBP)

0x4e5b27 JE	4e5fc0

0x4e5b2d MOV	0x10(%RBP),%RAX

0x4e5b31 MOV	(%RAX,%RCX,8),%RDI

0x4e5b35 MOV	0x8(%RAX,%RCX,8),%RDX

0x4e5b3a LEA	0x1(%RCX),%RSI

0x4e5b3e CMP	%RDX,%RDI

0x4e5b41 JGE	4e5fc4

0x4e5b47 MOV	%RSI,-0x88(%RBP)

0x4e5b4e MOV	%RDI,%RAX

0x4e5b51 NOT	%RAX

0x4e5b54 ADD	%RAX,%RDX

0x4e5b57 MOV	%RDX,-0x38(%RBP)

0x4e5b5b XOR	%R12D,%R12D

0x4e5b5e MOV	%R10,%RDX

0x4e5b61 MOV	%RDI,-0x30(%RBP)

0x4e5b65 JMP	4e5b96

  (3576) 0x4e5b80 MOV	-0x38(%RBP),%RSI

  (3576) 0x4e5b84 CMP	%RSI,%R12

  (3576) 0x4e5b87 LEA	0x1(%R12),%R12

  (3576) 0x4e5b8c MOV	-0x30(%RBP),%RDI

  (3576) 0x4e5b90 JE	4e6000

  (3576) 0x4e5b96 LEA	(%RDI,%R12,1),%RAX

  (3576) 0x4e5b9a MOV	0x18(%RBP),%RCX

  (3576) 0x4e5b9e MOV	(%RCX,%RAX,8),%RAX

  (3576) 0x4e5ba2 MOV	0x50(%RBP),%RCX

  (3576) 0x4e5ba6 MOV	(%RCX,%RAX,8),%R13

  (3576) 0x4e5baa MOV	0x8(%RCX,%RAX,8),%RDI

  (3576) 0x4e5baf MOV	%RDI,%R11

  (3576) 0x4e5bb2 SUB	%R13,%R11

  (3576) 0x4e5bb5 JLE	4e5c40

  (3576) 0x4e5bbb CMP	$0x8,%R11

  (3576) 0x4e5bbf JAE	4e5cc0

  (3576) 0x4e5bc5 MOV	%R11,%RCX

  (3576) 0x4e5bc8 AND	$-0x8,%RCX

  (3576) 0x4e5bcc CMP	%R11,%RCX

  (3576) 0x4e5bcf JAE	4e5c40

  (3576) 0x4e5bd1 ADD	%RCX,%R13

  (3576) 0x4e5bd4 MOV	0x58(%RBP),%RSI

  (3576) 0x4e5bd8 JMP	4e5c08

    (3579) 0x4e5c00 INC	%R13

    (3579) 0x4e5c03 CMP	%R13,%RDI

    (3579) 0x4e5c06 JE	4e5c40

    (3579) 0x4e5c08 MOV	(%RSI,%R13,8),%RCX

    (3579) 0x4e5c0c ADD	%R15,%RCX

    (3579) 0x4e5c0f CMP	%R10,(%R14,%RCX,8)

    (3579) 0x4e5c13 JGE	4e5c00

    (3579) 0x4e5c15 MOV	%RDX,(%R14,%RCX,8)

    (3579) 0x4e5c19 INC	%RDX

    (3579) 0x4e5c1c JMP	4e5c00

  (3576) 0x4e5c40 MOV	0x40(%RBP),%RCX

  (3576) 0x4e5c44 MOV	(%RCX,%RAX,8),%RDI

  (3576) 0x4e5c48 MOV	0x8(%RCX,%RAX,8),%RAX

  (3576) 0x4e5c4d MOV	%RAX,%R9

  (3576) 0x4e5c50 SUB	%RDI,%R9

  (3576) 0x4e5c53 JLE	4e5b80

  (3576) 0x4e5c59 CMP	$0x8,%R9

  (3576) 0x4e5c5d JAE	4e5e80

  (3576) 0x4e5c63 MOV	0x48(%RBP),%R13

  (3576) 0x4e5c67 MOV	%R9,%RCX

  (3576) 0x4e5c6a AND	$-0x8,%RCX

  (3576) 0x4e5c6e CMP	%R9,%RCX

  (3576) 0x4e5c71 JAE	4e5b80

  (3576) 0x4e5c77 ADD	%RCX,%RDI

  (3576) 0x4e5c7a MOV	-0x38(%RBP),%RSI

  (3576) 0x4e5c7e JMP	4e5c8c

    (3577) 0x4e5c80 INC	%RDI

    (3577) 0x4e5c83 CMP	%RDI,%RAX

    (3577) 0x4e5c86 JE	4e5b84

    (3577) 0x4e5c8c MOV	(%R13,%RDI,8),%RCX

    (3577) 0x4e5c91 CMP	%R8,(%R14,%RCX,8)

    (3577) 0x4e5c95 JGE	4e5c80

    (3577) 0x4e5c97 MOV	%RBX,(%R14,%RCX,8)

    (3577) 0x4e5c9b INC	%RBX

    (3577) 0x4e5c9e JMP	4e5c80

  (3576) 0x4e5cc0 MOV	%R11,%R9

  (3576) 0x4e5cc3 SHR	$0x3,%R9

  (3576) 0x4e5cc7 MOV	-0xd0(%RBP),%RCX

  (3576) 0x4e5cce LEA	(%RCX,%R13,8),%RCX

  (3576) 0x4e5cd2 JMP	4e5d0d

    (3580) 0x4e5d00 ADD	$0x40,%RCX

    (3580) 0x4e5d04 DEC	%R9

    (3580) 0x4e5d07 JE	4e5bc5

    (3580) 0x4e5d0d MOV	-0x38(%RCX),%RSI

    (3580) 0x4e5d11 ADD	%R15,%RSI

    (3580) 0x4e5d14 CMP	%R10,(%R14,%RSI,8)

    (3580) 0x4e5d18 JGE	4e5dc0

    (3580) 0x4e5d1e MOV	%RDX,(%R14,%RSI,8)

    (3580) 0x4e5d22 INC	%RDX

    (3580) 0x4e5d25 MOV	-0x30(%RCX),%RSI

    (3580) 0x4e5d29 ADD	%R15,%RSI

    (3580) 0x4e5d2c CMP	%R10,(%R14,%RSI,8)

    (3580) 0x4e5d30 JL	4e5dd1

    (3580) 0x4e5d36 MOV	-0x28(%RCX),%RSI

    (3580) 0x4e5d3a ADD	%R15,%RSI

    (3580) 0x4e5d3d CMP	%R10,(%R14,%RSI,8)

    (3580) 0x4e5d41 JGE	4e5de9

    (3580) 0x4e5d47 MOV	%RDX,(%R14,%RSI,8)

    (3580) 0x4e5d4b INC	%RDX

    (3580) 0x4e5d4e MOV	-0x20(%RCX),%RSI

    (3580) 0x4e5d52 ADD	%R15,%RSI

    (3580) 0x4e5d55 CMP	%R10,(%R14,%RSI,8)

    (3580) 0x4e5d59 JL	4e5dfa

    (3580) 0x4e5d5f MOV	-0x18(%RCX),%RSI

    (3580) 0x4e5d63 ADD	%R15,%RSI

    (3580) 0x4e5d66 CMP	%R10,(%R14,%RSI,8)

    (3580) 0x4e5d6a JGE	4e5e12

    (3580) 0x4e5d70 MOV	%RDX,(%R14,%RSI,8)

    (3580) 0x4e5d74 INC	%RDX

    (3580) 0x4e5d77 MOV	-0x10(%RCX),%RSI

    (3580) 0x4e5d7b ADD	%R15,%RSI

    (3580) 0x4e5d7e CMP	%R10,(%R14,%RSI,8)

    (3580) 0x4e5d82 JL	4e5e23

    (3580) 0x4e5d88 MOV	-0x8(%RCX),%RSI

    (3580) 0x4e5d8c ADD	%R15,%RSI

    (3580) 0x4e5d8f CMP	%R10,(%R14,%RSI,8)

    (3580) 0x4e5d93 JGE	4e5e3b

    (3580) 0x4e5d99 MOV	%RDX,(%R14,%RSI,8)

    (3580) 0x4e5d9d INC	%RDX

    (3580) 0x4e5da0 MOV	(%RCX),%RSI

    (3580) 0x4e5da3 ADD	%R15,%RSI

    (3580) 0x4e5da6 CMP	%R10,(%R14,%RSI,8)

    (3580) 0x4e5daa JGE	4e5d00

    (3580) 0x4e5db0 JMP	4e5e4b

    (3580) 0x4e5dc0 MOV	-0x30(%RCX),%RSI

    (3580) 0x4e5dc4 ADD	%R15,%RSI

    (3580) 0x4e5dc7 CMP	%R10,(%R14,%RSI,8)

    (3580) 0x4e5dcb JGE	4e5d36

    (3580) 0x4e5dd1 MOV	%RDX,(%R14,%RSI,8)

    (3580) 0x4e5dd5 INC	%RDX

    (3580) 0x4e5dd8 MOV	-0x28(%RCX),%RSI

    (3580) 0x4e5ddc ADD	%R15,%RSI

    (3580) 0x4e5ddf CMP	%R10,(%R14,%RSI,8)

    (3580) 0x4e5de3 JL	4e5d47

    (3580) 0x4e5de9 MOV	-0x20(%RCX),%RSI

    (3580) 0x4e5ded ADD	%R15,%RSI

    (3580) 0x4e5df0 CMP	%R10,(%R14,%RSI,8)

    (3580) 0x4e5df4 JGE	4e5d5f

    (3580) 0x4e5dfa MOV	%RDX,(%R14,%RSI,8)

    (3580) 0x4e5dfe INC	%RDX

    (3580) 0x4e5e01 MOV	-0x18(%RCX),%RSI

    (3580) 0x4e5e05 ADD	%R15,%RSI

    (3580) 0x4e5e08 CMP	%R10,(%R14,%RSI,8)

    (3580) 0x4e5e0c JL	4e5d70

    (3580) 0x4e5e12 MOV	-0x10(%RCX),%RSI

    (3580) 0x4e5e16 ADD	%R15,%RSI

    (3580) 0x4e5e19 CMP	%R10,(%R14,%RSI,8)

    (3580) 0x4e5e1d JGE	4e5d88

    (3580) 0x4e5e23 MOV	%RDX,(%R14,%RSI,8)

    (3580) 0x4e5e27 INC	%RDX

    (3580) 0x4e5e2a MOV	-0x8(%RCX),%RSI

    (3580) 0x4e5e2e ADD	%R15,%RSI

    (3580) 0x4e5e31 CMP	%R10,(%R14,%RSI,8)

    (3580) 0x4e5e35 JL	4e5d99

    (3580) 0x4e5e3b MOV	(%RCX),%RSI

    (3580) 0x4e5e3e ADD	%R15,%RSI

    (3580) 0x4e5e41 CMP	%R10,(%R14,%RSI,8)

    (3580) 0x4e5e45 JGE	4e5d00

    (3580) 0x4e5e4b MOV	%RDX,(%R14,%RSI,8)

    (3580) 0x4e5e4f INC	%RDX

    (3580) 0x4e5e52 JMP	4e5d00

  (3576) 0x4e5e80 MOV	%R9,%RCX

  (3576) 0x4e5e83 SHR	$0x3,%RCX

  (3576) 0x4e5e87 MOV	-0xc8(%RBP),%RSI

  (3576) 0x4e5e8e LEA	(%RSI,%RDI,8),%R11

  (3576) 0x4e5e92 MOV	0x48(%RBP),%R13

  (3576) 0x4e5e96 JMP	4e5ecd

    (3578) 0x4e5ec0 ADD	$0x40,%R11

    (3578) 0x4e5ec4 DEC	%RCX

    (3578) 0x4e5ec7 JE	4e5c67

    (3578) 0x4e5ecd MOV	-0x38(%R11),%RSI

    (3578) 0x4e5ed1 CMP	%R8,(%R14,%RSI,8)

    (3578) 0x4e5ed5 JGE	4e5f40

    (3578) 0x4e5ed7 MOV	%RBX,(%R14,%RSI,8)

    (3578) 0x4e5edb INC	%RBX

    (3578) 0x4e5ede MOV	-0x30(%R11),%RSI

    (3578) 0x4e5ee2 CMP	%R8,(%R14,%RSI,8)

    (3578) 0x4e5ee6 JL	4e5f4a

    (3578) 0x4e5ee8 MOV	-0x28(%R11),%RSI

    (3578) 0x4e5eec CMP	%R8,(%R14,%RSI,8)

    (3578) 0x4e5ef0 JGE	4e5f5b

    (3578) 0x4e5ef2 MOV	%RBX,(%R14,%RSI,8)

    (3578) 0x4e5ef6 INC	%RBX

    (3578) 0x4e5ef9 MOV	-0x20(%R11),%RSI

    (3578) 0x4e5efd CMP	%R8,(%R14,%RSI,8)

    (3578) 0x4e5f01 JL	4e5f65

    (3578) 0x4e5f03 MOV	-0x18(%R11),%RSI

    (3578) 0x4e5f07 CMP	%R8,(%R14,%RSI,8)

    (3578) 0x4e5f0b JGE	4e5f76

    (3578) 0x4e5f0d MOV	%RBX,(%R14,%RSI,8)

    (3578) 0x4e5f11 INC	%RBX

    (3578) 0x4e5f14 MOV	-0x10(%R11),%RSI

    (3578) 0x4e5f18 CMP	%R8,(%R14,%RSI,8)

    (3578) 0x4e5f1c JL	4e5f80

    (3578) 0x4e5f1e MOV	-0x8(%R11),%RSI

    (3578) 0x4e5f22 CMP	%R8,(%R14,%RSI,8)

    (3578) 0x4e5f26 JGE	4e5f91

    (3578) 0x4e5f28 MOV	%RBX,(%R14,%RSI,8)

    (3578) 0x4e5f2c INC	%RBX

    (3578) 0x4e5f2f MOV	(%R11),%RSI

    (3578) 0x4e5f32 CMP	%R8,(%R14,%RSI,8)

    (3578) 0x4e5f36 JGE	4e5ec0

    (3578) 0x4e5f38 JMP	4e5f9e

    (3578) 0x4e5f40 MOV	-0x30(%R11),%RSI

    (3578) 0x4e5f44 CMP	%R8,(%R14,%RSI,8)

    (3578) 0x4e5f48 JGE	4e5ee8

    (3578) 0x4e5f4a MOV	%RBX,(%R14,%RSI,8)

    (3578) 0x4e5f4e INC	%RBX

    (3578) 0x4e5f51 MOV	-0x28(%R11),%RSI

    (3578) 0x4e5f55 CMP	%R8,(%R14,%RSI,8)

    (3578) 0x4e5f59 JL	4e5ef2

    (3578) 0x4e5f5b MOV	-0x20(%R11),%RSI

    (3578) 0x4e5f5f CMP	%R8,(%R14,%RSI,8)

    (3578) 0x4e5f63 JGE	4e5f03

    (3578) 0x4e5f65 MOV	%RBX,(%R14,%RSI,8)

    (3578) 0x4e5f69 INC	%RBX

    (3578) 0x4e5f6c MOV	-0x18(%R11),%RSI

    (3578) 0x4e5f70 CMP	%R8,(%R14,%RSI,8)

    (3578) 0x4e5f74 JL	4e5f0d

    (3578) 0x4e5f76 MOV	-0x10(%R11),%RSI

    (3578) 0x4e5f7a CMP	%R8,(%R14,%RSI,8)

    (3578) 0x4e5f7e JGE	4e5f1e

    (3578) 0x4e5f80 MOV	%RBX,(%R14,%RSI,8)

    (3578) 0x4e5f84 INC	%RBX

    (3578) 0x4e5f87 MOV	-0x8(%R11),%RSI

    (3578) 0x4e5f8b CMP	%R8,(%R14,%RSI,8)

    (3578) 0x4e5f8f JL	4e5f28

    (3578) 0x4e5f91 MOV	(%R11),%RSI

    (3578) 0x4e5f94 CMP	%R8,(%R14,%RSI,8)

    (3578) 0x4e5f98 JGE	4e5ec0

    (3578) 0x4e5f9e MOV	%RBX,(%R14,%RSI,8)

    (3578) 0x4e5fa2 INC	%RBX

    (3578) 0x4e5fa5 JMP	4e5ec0

0x4e5fc0 LEA	0x1(%RCX),%RSI

0x4e5fc4 MOV	%R10,%RDX

0x4e5fc7 JMP	4e600b

0x4e6000 MOV	-0x68(%RBP),%RCX

0x4e6004 MOV	-0x88(%RBP),%RSI

0x4e600b MOV	-0xb0(%RBP),%RAX

0x4e6012 MOV	(%RAX,%RCX,8),%R13

0x4e6016 MOV	(%RAX,%RSI,8),%R11

0x4e601a CMP	%R11,%R13

0x4e601d JGE	4e5ac0

0x4e6023 MOV	%R13,%RAX

0x4e6026 NOT	%RAX

0x4e6029 ADD	%RAX,%R11

0x4e602c CMPQ	$0,0x88(%RBP)

0x4e6034 MOV	%R11,-0x30(%RBP)

0x4e6038 JE	4e6400

0x4e603e XOR	%R12D,%R12D

0x4e6041 MOV	%R13,-0x38(%RBP)

0x4e6045 JMP	4e6096

  (3571) 0x4e6080 MOV	-0x30(%RBP),%R11

  (3571) 0x4e6084 CMP	%R11,%R12

  (3571) 0x4e6087 LEA	0x1(%R12),%R12

  (3571) 0x4e608c MOV	-0x38(%RBP),%R13

  (3571) 0x4e6090 JE	4e5ac0

  (3571) 0x4e6096 LEA	(%R13,%R12,1),%RAX

  (3571) 0x4e609b MOV	-0x78(%RBP),%RCX

  (3571) 0x4e609f MOV	(%RCX,%RAX,8),%RDI

  (3571) 0x4e60a3 MOV	0x20(%RBP),%RCX

  (3571) 0x4e60a7 MOV	(%RCX,%RDI,8),%RAX

  (3571) 0x4e60ab MOV	0x8(%RCX,%RDI,8),%R13

  (3571) 0x4e60b0 MOV	%R13,%R9

  (3571) 0x4e60b3 SUB	%RAX,%R9

  (3571) 0x4e60b6 JLE	4e6284

  (3571) 0x4e60bc CMP	$0x8,%R9

  (3571) 0x4e60c0 JAE	4e6140

  (3571) 0x4e60c6 MOV	%R9,%RCX

  (3571) 0x4e60c9 AND	$-0x8,%RCX

  (3571) 0x4e60cd CMP	%R9,%RCX

  (3571) 0x4e60d0 JAE	4e6280

  (3571) 0x4e60d6 ADD	%RCX,%RAX

  (3571) 0x4e60d9 MOV	0x28(%RBP),%RSI

  (3571) 0x4e60dd MOV	-0x30(%RBP),%R11

  (3571) 0x4e60e1 JMP	4e610c

    (3574) 0x4e6100 INC	%RAX

    (3574) 0x4e6103 CMP	%RAX,%R13

    (3574) 0x4e6106 JE	4e6284

    (3574) 0x4e610c MOV	(%RSI,%RAX,8),%RCX

    (3574) 0x4e6110 CMP	%R8,(%R14,%RCX,8)

    (3574) 0x4e6114 JGE	4e6100

    (3574) 0x4e6116 MOV	%RBX,(%R14,%RCX,8)

    (3574) 0x4e611a INC	%RBX

    (3574) 0x4e611d JMP	4e6100

  (3571) 0x4e6140 MOV	%R9,%RCX

  (3571) 0x4e6143 SHR	$0x3,%RCX

  (3571) 0x4e6147 MOV	-0x70(%RBP),%RSI

  (3571) 0x4e614b LEA	(%RSI,%RAX,8),%R11

  (3571) 0x4e614f JMP	4e618d

    (3575) 0x4e6180 ADD	$0x40,%R11

    (3575) 0x4e6184 DEC	%RCX

    (3575) 0x4e6187 JE	4e60c6

    (3575) 0x4e618d MOV	-0x38(%R11),%RSI

    (3575) 0x4e6191 CMP	%R8,(%R14,%RSI,8)

    (3575) 0x4e6195 JGE	4e6200

    (3575) 0x4e6197 MOV	%RBX,(%R14,%RSI,8)

    (3575) 0x4e619b INC	%RBX

    (3575) 0x4e619e MOV	-0x30(%R11),%RSI

    (3575) 0x4e61a2 CMP	%R8,(%R14,%RSI,8)

    (3575) 0x4e61a6 JL	4e620a

    (3575) 0x4e61a8 MOV	-0x28(%R11),%RSI

    (3575) 0x4e61ac CMP	%R8,(%R14,%RSI,8)

    (3575) 0x4e61b0 JGE	4e621b

    (3575) 0x4e61b2 MOV	%RBX,(%R14,%RSI,8)

    (3575) 0x4e61b6 INC	%RBX

    (3575) 0x4e61b9 MOV	-0x20(%R11),%RSI

    (3575) 0x4e61bd CMP	%R8,(%R14,%RSI,8)

    (3575) 0x4e61c1 JL	4e6225

    (3575) 0x4e61c3 MOV	-0x18(%R11),%RSI

    (3575) 0x4e61c7 CMP	%R8,(%R14,%RSI,8)

    (3575) 0x4e61cb JGE	4e6236

    (3575) 0x4e61cd MOV	%RBX,(%R14,%RSI,8)

    (3575) 0x4e61d1 INC	%RBX

    (3575) 0x4e61d4 MOV	-0x10(%R11),%RSI

    (3575) 0x4e61d8 CMP	%R8,(%R14,%RSI,8)

    (3575) 0x4e61dc JL	4e6240

    (3575) 0x4e61de MOV	-0x8(%R11),%RSI

    (3575) 0x4e61e2 CMP	%R8,(%R14,%RSI,8)

    (3575) 0x4e61e6 JGE	4e6251

    (3575) 0x4e61e8 MOV	%RBX,(%R14,%RSI,8)

    (3575) 0x4e61ec INC	%RBX

    (3575) 0x4e61ef MOV	(%R11),%RSI

    (3575) 0x4e61f2 CMP	%R8,(%R14,%RSI,8)

    (3575) 0x4e61f6 JGE	4e6180

    (3575) 0x4e61f8 JMP	4e625e

    (3575) 0x4e6200 MOV	-0x30(%R11),%RSI

    (3575) 0x4e6204 CMP	%R8,(%R14,%RSI,8)

    (3575) 0x4e6208 JGE	4e61a8

    (3575) 0x4e620a MOV	%RBX,(%R14,%RSI,8)

    (3575) 0x4e620e INC	%RBX

    (3575) 0x4e6211 MOV	-0x28(%R11),%RSI

    (3575) 0x4e6215 CMP	%R8,(%R14,%RSI,8)

    (3575) 0x4e6219 JL	4e61b2

    (3575) 0x4e621b MOV	-0x20(%R11),%RSI

    (3575) 0x4e621f CMP	%R8,(%R14,%RSI,8)

    (3575) 0x4e6223 JGE	4e61c3

    (3575) 0x4e6225 MOV	%RBX,(%R14,%RSI,8)

    (3575) 0x4e6229 INC	%RBX

    (3575) 0x4e622c MOV	-0x18(%R11),%RSI

    (3575) 0x4e6230 CMP	%R8,(%R14,%RSI,8)

    (3575) 0x4e6234 JL	4e61cd

    (3575) 0x4e6236 MOV	-0x10(%R11),%RSI

    (3575) 0x4e623a CMP	%R8,(%R14,%RSI,8)

    (3575) 0x4e623e JGE	4e61de

    (3575) 0x4e6240 MOV	%RBX,(%R14,%RSI,8)

    (3575) 0x4e6244 INC	%RBX

    (3575) 0x4e6247 MOV	-0x8(%R11),%RSI

    (3575) 0x4e624b CMP	%R8,(%R14,%RSI,8)

    (3575) 0x4e624f JL	4e61e8

    (3575) 0x4e6251 MOV	(%R11),%RSI

    (3575) 0x4e6254 CMP	%R8,(%R14,%RSI,8)

    (3575) 0x4e6258 JGE	4e6180

    (3575) 0x4e625e MOV	%RBX,(%R14,%RSI,8)

    (3575) 0x4e6262 INC	%RBX

    (3575) 0x4e6265 JMP	4e6180

  (3571) 0x4e6280 MOV	-0x30(%RBP),%R11

  (3571) 0x4e6284 MOV	0x30(%RBP),%RCX

  (3571) 0x4e6288 MOV	(%RCX,%RDI,8),%RAX

  (3571) 0x4e628c MOV	0x8(%RCX,%RDI,8),%RCX

  (3571) 0x4e6291 MOV	%RCX,%RDI

  (3571) 0x4e6294 SUB	%RAX,%RDI

  (3571) 0x4e6297 JLE	4e6084

  (3571) 0x4e629d CMP	$0x4,%RDI

  (3571) 0x4e62a1 JAE	4e6340

  (3571) 0x4e62a7 MOV	0x60(%RBP),%R13

  (3571) 0x4e62ab MOV	%RDI,%RSI

  (3571) 0x4e62ae AND	$-0x4,%RSI

  (3571) 0x4e62b2 CMP	%RDI,%RSI

  (3571) 0x4e62b5 JAE	4e6080

  (3571) 0x4e62bb ADD	%RSI,%RAX

  (3571) 0x4e62be MOV	0x38(%RBP),%RDI

  (3571) 0x4e62c2 MOV	-0x30(%RBP),%R11

  (3571) 0x4e62c6 JMP	4e630c

    (3572) 0x4e6300 INC	%RAX

    (3572) 0x4e6303 CMP	%RAX,%RCX

    (3572) 0x4e6306 JE	4e6084

    (3572) 0x4e630c MOV	(%RDI,%RAX,8),%RSI

    (3572) 0x4e6310 MOV	(%R13,%RSI,8),%RSI

    (3572) 0x4e6315 ADD	%R15,%RSI

    (3572) 0x4e6318 CMP	%R10,(%R14,%RSI,8)

    (3572) 0x4e631c JGE	4e6300

    (3572) 0x4e631e MOV	%RDX,(%R14,%RSI,8)

    (3572) 0x4e6322 INC	%RDX

    (3572) 0x4e6325 JMP	4e6300

  (3571) 0x4e6340 MOV	%RDI,%R9

  (3571) 0x4e6343 SHR	$0x2,%R9

  (3571) 0x4e6347 MOV	-0xc0(%RBP),%RSI

  (3571) 0x4e634e LEA	(%RSI,%RAX,8),%R11

  (3571) 0x4e6352 MOV	0x60(%RBP),%R13

  (3571) 0x4e6356 JMP	4e638d

    (3573) 0x4e6380 ADD	$0x20,%R11

    (3573) 0x4e6384 DEC	%R9

    (3573) 0x4e6387 JE	4e62ab

    (3573) 0x4e638d MOV	-0x18(%R11),%RSI

    (3573) 0x4e6391 MOV	(%R13,%RSI,8),%RSI

    (3573) 0x4e6396 ADD	%R15,%RSI

    (3573) 0x4e6399 CMP	%R10,(%R14,%RSI,8)

    (3573) 0x4e639d JGE	4e63a6

    (3573) 0x4e639f MOV	%RDX,(%R14,%RSI,8)

    (3573) 0x4e63a3 INC	%RDX

    (3573) 0x4e63a6 MOV	-0x10(%R11),%RSI

    (3573) 0x4e63aa MOV	(%R13,%RSI,8),%RSI

    (3573) 0x4e63af ADD	%R15,%RSI

    (3573) 0x4e63b2 CMP	%R10,(%R14,%RSI,8)

    (3573) 0x4e63b6 JGE	4e63bf

    (3573) 0x4e63b8 MOV	%RDX,(%R14,%RSI,8)

    (3573) 0x4e63bc INC	%RDX

    (3573) 0x4e63bf MOV	-0x8(%R11),%RSI

    (3573) 0x4e63c3 MOV	(%R13,%RSI,8),%RSI

    (3573) 0x4e63c8 ADD	%R15,%RSI

    (3573) 0x4e63cb CMP	%R10,(%R14,%RSI,8)

    (3573) 0x4e63cf JGE	4e63d8

    (3573) 0x4e63d1 MOV	%RDX,(%R14,%RSI,8)

    (3573) 0x4e63d5 INC	%RDX

    (3573) 0x4e63d8 MOV	(%R11),%RSI

    (3573) 0x4e63db MOV	(%R13,%RSI,8),%RSI

    (3573) 0x4e63e0 ADD	%R15,%RSI

    (3573) 0x4e63e3 CMP	%R10,(%R14,%RSI,8)

    (3573) 0x4e63e7 JGE	4e6380

    (3573) 0x4e63e9 MOV	%RDX,(%R14,%RSI,8)

    (3573) 0x4e63ed INC	%RDX

    (3573) 0x4e63f0 JMP	4e6380

0x4e6400 XOR	%R12D,%R12D

0x4e6403 JMP	4e6452

  (3568) 0x4e6440 MOV	-0x30(%RBP),%R11

  (3568) 0x4e6444 CMP	%R11,%R12

  (3568) 0x4e6447 LEA	0x1(%R12),%R12

  (3568) 0x4e644c JE	4e5ac0

  (3568) 0x4e6452 LEA	(%R13,%R12,1),%RAX

  (3568) 0x4e6457 MOV	-0x78(%RBP),%RCX

  (3568) 0x4e645b MOV	(%RCX,%RAX,8),%RAX

  (3568) 0x4e645f MOV	0x20(%RBP),%RCX

  (3568) 0x4e6463 MOV	(%RCX,%RAX,8),%RDI

  (3568) 0x4e6467 MOV	0x8(%RCX,%RAX,8),%RAX

  (3568) 0x4e646c MOV	%RAX,%R9

  (3568) 0x4e646f SUB	%RDI,%R9

  (3568) 0x4e6472 JLE	4e6444

  (3568) 0x4e6474 CMP	$0x8,%R9

  (3568) 0x4e6478 JAE	4e6500

  (3568) 0x4e647e MOV	%R9,%RCX

  (3568) 0x4e6481 AND	$-0x8,%RCX

  (3568) 0x4e6485 CMP	%R9,%RCX

  (3568) 0x4e6488 JAE	4e6440

  (3568) 0x4e648a ADD	%RCX,%RDI

  (3568) 0x4e648d MOV	0x28(%RBP),%RSI

  (3568) 0x4e6491 MOV	-0x30(%RBP),%R11

  (3568) 0x4e6495 JMP	4e64cc

    (3569) 0x4e64c0 INC	%RDI

    (3569) 0x4e64c3 CMP	%RDI,%RAX

    (3569) 0x4e64c6 JE	4e6444

    (3569) 0x4e64cc MOV	(%RSI,%RDI,8),%RCX

    (3569) 0x4e64d0 CMP	%R8,(%R14,%RCX,8)

    (3569) 0x4e64d4 JGE	4e64c0

    (3569) 0x4e64d6 MOV	%RBX,(%R14,%RCX,8)

    (3569) 0x4e64da INC	%RBX

    (3569) 0x4e64dd JMP	4e64c0

  (3568) 0x4e6500 MOV	%R9,%RCX

  (3568) 0x4e6503 SHR	$0x3,%RCX

  (3568) 0x4e6507 MOV	-0x70(%RBP),%RSI

  (3568) 0x4e650b LEA	(%RSI,%RDI,8),%R11

  (3568) 0x4e650f JMP	4e654d

    (3570) 0x4e6540 ADD	$0x40,%R11

    (3570) 0x4e6544 DEC	%RCX

    (3570) 0x4e6547 JE	4e647e

    (3570) 0x4e654d MOV	-0x38(%R11),%RSI

    (3570) 0x4e6551 CMP	%R8,(%R14,%RSI,8)

    (3570) 0x4e6555 JGE	4e65c0

    (3570) 0x4e6557 MOV	%RBX,(%R14,%RSI,8)

    (3570) 0x4e655b INC	%RBX

    (3570) 0x4e655e MOV	-0x30(%R11),%RSI

    (3570) 0x4e6562 CMP	%R8,(%R14,%RSI,8)

    (3570) 0x4e6566 JL	4e65ca

    (3570) 0x4e6568 MOV	-0x28(%R11),%RSI

    (3570) 0x4e656c CMP	%R8,(%R14,%RSI,8)

    (3570) 0x4e6570 JGE	4e65db

    (3570) 0x4e6572 MOV	%RBX,(%R14,%RSI,8)

    (3570) 0x4e6576 INC	%RBX

    (3570) 0x4e6579 MOV	-0x20(%R11),%RSI

    (3570) 0x4e657d CMP	%R8,(%R14,%RSI,8)

    (3570) 0x4e6581 JL	4e65e5

    (3570) 0x4e6583 MOV	-0x18(%R11),%RSI

    (3570) 0x4e6587 CMP	%R8,(%R14,%RSI,8)

    (3570) 0x4e658b JGE	4e65f6

    (3570) 0x4e658d MOV	%RBX,(%R14,%RSI,8)

    (3570) 0x4e6591 INC	%RBX

    (3570) 0x4e6594 MOV	-0x10(%R11),%RSI

    (3570) 0x4e6598 CMP	%R8,(%R14,%RSI,8)

    (3570) 0x4e659c JL	4e6600

    (3570) 0x4e659e MOV	-0x8(%R11),%RSI

    (3570) 0x4e65a2 CMP	%R8,(%R14,%RSI,8)

    (3570) 0x4e65a6 JGE	4e6611

    (3570) 0x4e65a8 MOV	%RBX,(%R14,%RSI,8)

    (3570) 0x4e65ac INC	%RBX

    (3570) 0x4e65af MOV	(%R11),%RSI

    (3570) 0x4e65b2 CMP	%R8,(%R14,%RSI,8)

    (3570) 0x4e65b6 JGE	4e6540

    (3570) 0x4e65b8 JMP	4e661e

    (3570) 0x4e65c0 MOV	-0x30(%R11),%RSI

    (3570) 0x4e65c4 CMP	%R8,(%R14,%RSI,8)

    (3570) 0x4e65c8 JGE	4e6568

    (3570) 0x4e65ca MOV	%RBX,(%R14,%RSI,8)

    (3570) 0x4e65ce INC	%RBX

    (3570) 0x4e65d1 MOV	-0x28(%R11),%RSI

    (3570) 0x4e65d5 CMP	%R8,(%R14,%RSI,8)

    (3570) 0x4e65d9 JL	4e6572

    (3570) 0x4e65db MOV	-0x20(%R11),%RSI

    (3570) 0x4e65df CMP	%R8,(%R14,%RSI,8)

    (3570) 0x4e65e3 JGE	4e6583

    (3570) 0x4e65e5 MOV	%RBX,(%R14,%RSI,8)

    (3570) 0x4e65e9 INC	%RBX

    (3570) 0x4e65ec MOV	-0x18(%R11),%RSI

    (3570) 0x4e65f0 CMP	%R8,(%R14,%RSI,8)

    (3570) 0x4e65f4 JL	4e658d

    (3570) 0x4e65f6 MOV	-0x10(%R11),%RSI

    (3570) 0x4e65fa CMP	%R8,(%R14,%RSI,8)

    (3570) 0x4e65fe JGE	4e659e

    (3570) 0x4e6600 MOV	%RBX,(%R14,%RSI,8)

    (3570) 0x4e6604 INC	%RBX

    (3570) 0x4e6607 MOV	-0x8(%R11),%RSI

    (3570) 0x4e660b CMP	%R8,(%R14,%RSI,8)

    (3570) 0x4e660f JL	4e65a8

    (3570) 0x4e6611 MOV	(%R11),%RSI

    (3570) 0x4e6614 CMP	%R8,(%R14,%RSI,8)

    (3570) 0x4e6618 JGE	4e6540

    (3570) 0x4e661e MOV	%RBX,(%R14,%RSI,8)

    (3570) 0x4e6622 INC	%RBX

    (3570) 0x4e6625 JMP	4e6540

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 109 - 242

--------------------------------------------------------------------------------

109:     if (ii < rest)

[...]

127:     for (i1 = ns; i1 < ne; i1++)

[...]

135:       if ( allsquare ) {

136:          B_marker[i1] = jj_count_diag;

137:          jj_count_diag++;

[...]

144:       if (num_cols_offd_A)

145:       {

146:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

147:          {

148:             i2 = A_offd_j[jj2];

[...]

154:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

[...]

164:                if (B_marker[i3] < jj_row_begin_offd)

165:                {

166:                   B_marker[i3] = jj_count_offd;

167:                   jj_count_offd++;

168:                }

169:             }

170:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

171:             {

172:                i3 = B_ext_diag_j[jj3];

173:

174:                if (B_marker[i3] < jj_row_begin_diag)

175:                {

176:                   B_marker[i3] = jj_count_diag;

177:                   jj_count_diag++;

[...]

187:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

188:       {

189:          i2 = A_diag_j[jj2];

[...]

195:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

196:          {

197:             i3 = B_diag_j[jj3];

[...]

205:             if (B_marker[i3] < jj_row_begin_diag)

206:             {

207:                B_marker[i3] = jj_count_diag;

208:                jj_count_diag++;

[...]

216:          if (num_cols_offd_B)

217:          {

218:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

219:             {

220:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

228:                if (B_marker[i3] < jj_row_begin_offd)

229:                {

230:                   B_marker[i3] = jj_count_offd;

231:                   jj_count_offd++;

[...]

241:       (*C_diag_i)[i1] = jj_row_begin_diag;

242:       (*C_offd_i)[i1] = jj_row_begin_offd;

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	11.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.74
Bottlenecks	micro-operation queue,
Function	hypre_ParMatmul_RowSizes.extracted
Source	par_csr_matop.c:127-127,par_csr_matop.c:135-137,par_csr_matop.c:144-146,par_csr_matop.c:187-187,par_csr_matop.c:216-216,par_csr_matop.c:231-231,par_csr_matop.c:241-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.83
CQA cycles if no scalar integer	9.83
CQA cycles if FP arith vectorized	9.83
CQA cycles if fully vectorized	0.83
Front-end cycles	9.83
P0 cycles	3.40
P1 cycles	3.40
P2 cycles	5.67
P3 cycles	5.67
P4 cycles	5.00
P5 cycles	3.40
P6 cycles	3.40
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	3.40
P11 cycles	5.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	59.00
Nb uops	59.00
Nb loads	17.00
Nb stores	10.00
Nb stack references	14.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.97
Bytes prefetched	0.00
Bytes loaded	136.00
Bytes stored	80.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.81
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.80

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	11.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.74
Bottlenecks	micro-operation queue,
Function	hypre_ParMatmul_RowSizes.extracted
Source	par_csr_matop.c:127-127,par_csr_matop.c:135-137,par_csr_matop.c:144-146,par_csr_matop.c:187-187,par_csr_matop.c:216-216,par_csr_matop.c:231-231,par_csr_matop.c:241-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.83
CQA cycles if no scalar integer	9.83
CQA cycles if FP arith vectorized	9.83
CQA cycles if fully vectorized	0.83
Front-end cycles	9.83
P0 cycles	3.40
P1 cycles	3.40
P2 cycles	5.67
P3 cycles	5.67
P4 cycles	5.00
P5 cycles	3.40
P6 cycles	3.40
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	3.40
P11 cycles	5.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	59.00
Nb uops	59.00
Nb loads	17.00
Nb stores	10.00
Nb stack references	14.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.97
Bytes prefetched	0.00
Bytes loaded	136.00
Bytes stored	80.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.81
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.80

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul_RowSizes.extracted
Source file and lines	par_csr_matop.c:109-242
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:109,127,135-137,144-148,154,164-177,187-189,195-197,205-208,216-220,228-231,241-242.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135-137,144-146,187,216,231,241-242.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 9.83 to 0.83 cycles (11.80x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 136 bytes. The binary loop is storing 80 bytes.

General properties

nb instructions	59
nb uops	59
loop length	252
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.83 cycles
front end	9.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.40	3.40	5.67	5.67	5.00	3.40	3.40	5.00	5.00	5.00	3.40	5.67
cycles	3.40	3.40	5.67	5.67	5.00	3.40	3.40	5.00	5.00	5.00	3.40	5.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.83
Dispatch	5.67
Overall L1	9.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.83 cycles. At this rate:

7% of peak load performance is reached (13.83 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.14 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.83 to 5.67 cycles (1.74x speedup).

ASM code

In the binary file, the address of the loop is: 4e5af8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x98(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,(%RAX,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x90(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R10,(%RAX,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0xb8(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP -0xa0(%RBP),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RSI),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 4e58a7 <hypre_ParMatmul_RowSizes.extracted+0xc7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x78(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV -0xa8(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 4e5b14 <hypre_ParMatmul_RowSizes.extracted+0x334>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%RCX,%RSI,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,(%R14,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%R8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RSI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMPQ $0,0x70(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %RSI,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 4e5fc0 <hypre_ParMatmul_RowSizes.extracted+0x7e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x10(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%RCX,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%RAX,%RCX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RCX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RDX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4e5fc4 <hypre_ParMatmul_RowSizes.extracted+0x7e4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOT %RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RDX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDI,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 4e5b96 <hypre_ParMatmul_RowSizes.extracted+0x3b6>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
LEA 0x1(%RCX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 4e600b <hypre_ParMatmul_RowSizes.extracted+0x82b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0x68(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x88(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%RCX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RAX,%RSI,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %R11,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4e5ac0 <hypre_ParMatmul_RowSizes.extracted+0x2e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOT %RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RAX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMPQ $0,0x88(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %R11,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 4e6400 <hypre_ParMatmul_RowSizes.extracted+0xc20>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R13,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 4e6096 <hypre_ParMatmul_RowSizes.extracted+0x8b6>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 4e6452 <hypre_ParMatmul_RowSizes.extracted+0xc72>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Function	hypre_ParMatmul_RowSizes.extracted
Source file and lines	par_csr_matop.c:109-242
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 136 bytes. The binary loop is storing 80 bytes.

General properties

nb instructions	59
nb uops	59
loop length	252
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.83 cycles
front end	9.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.40	3.40	5.67	5.67	5.00	3.40	3.40	5.00	5.00	5.00	3.40	5.67
cycles	3.40	3.40	5.67	5.67	5.00	3.40	3.40	5.00	5.00	5.00	3.40	5.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.83
Dispatch	5.67
Overall L1	9.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.83 cycles. At this rate:

7% of peak load performance is reached (13.83 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.14 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4e5af8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x98(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,(%RAX,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x90(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R10,(%RAX,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0xb8(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP -0xa0(%RBP),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RSI),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 4e58a7 <hypre_ParMatmul_RowSizes.extracted+0xc7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x78(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV -0xa8(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 4e5b14 <hypre_ParMatmul_RowSizes.extracted+0x334>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%RCX,%RSI,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,(%R14,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%R8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RSI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMPQ $0,0x70(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %RSI,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 4e5fc0 <hypre_ParMatmul_RowSizes.extracted+0x7e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x10(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%RCX,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%RAX,%RCX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RCX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RDX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4e5fc4 <hypre_ParMatmul_RowSizes.extracted+0x7e4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOT %RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RDX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDI,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 4e5b96 <hypre_ParMatmul_RowSizes.extracted+0x3b6>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
LEA 0x1(%RCX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 4e600b <hypre_ParMatmul_RowSizes.extracted+0x82b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0x68(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x88(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%RCX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RAX,%RSI,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %R11,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4e5ac0 <hypre_ParMatmul_RowSizes.extracted+0x2e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOT %RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RAX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMPQ $0,0x88(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %R11,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 4e6400 <hypre_ParMatmul_RowSizes.extracted+0xc20>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R13,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 4e6096 <hypre_ParMatmul_RowSizes.extracted+0x8b6>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 4e6452 <hypre_ParMatmul_RowSizes.extracted+0xc72>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code