OV - exec - Loop 294

	Loop Id: 294	Module: exec	Source: par_coarsen.c:2327-2334	Coverage: 0.06%

0x42bc80 ADD	$0x40,%RDI

0x42bc84 DEC	%RSI

0x42bc87 JE	42bb9f

0x42bc8d MOV	-0x38(%RDI),%R8    [1]

0x42bc91 VUCOMISD	(%R15,%R8,8),%XMM0    [3]

0x42bc97 JB	42bd40

0x42bc9d MOV	-0x30(%RDI),%R8    [1]

0x42bca1 VUCOMISD	(%R15,%R8,8),%XMM0    [3]

0x42bca7 JB	42bd58

0x42bcad MOV	-0x28(%RDI),%R8    [1]

0x42bcb1 VUCOMISD	(%R15,%R8,8),%XMM0    [3]

0x42bcb7 JB	42bd70

0x42bcbd MOV	-0x20(%RDI),%R8    [1]

0x42bcc1 VUCOMISD	(%R15,%R8,8),%XMM0    [3]

0x42bcc7 JB	42bd88

0x42bccd MOV	-0x18(%RDI),%R8    [1]

0x42bcd1 VUCOMISD	(%R15,%R8,8),%XMM0    [3]

0x42bcd7 JB	42bda0

0x42bcdd MOV	-0x10(%RDI),%R8    [1]

0x42bce1 VUCOMISD	(%R15,%R8,8),%XMM0    [3]

0x42bce7 JB	42bdb8

0x42bced MOV	-0x8(%RDI),%R8    [1]

0x42bcf1 VUCOMISD	(%R15,%R8,8),%XMM0    [3]

0x42bcf7 JB	42bdd0

0x42bcfd MOV	(%RDI),%R8    [1]

0x42bd00 VUCOMISD	(%R15,%R8,8),%XMM0    [3]

0x42bd06 JAE	42bc80

0x42bd0c JMP	42bde7

0x42bd40 MOVQ	$0x1,(%R12,%R8,8)    [2]

0x42bd48 MOV	-0x30(%RDI),%R8    [1]

0x42bd4c VUCOMISD	(%R15,%R8,8),%XMM0    [3]

0x42bd52 JAE	42bcad

0x42bd58 MOVQ	$0x1,(%R12,%R8,8)    [2]

0x42bd60 MOV	-0x28(%RDI),%R8    [1]

0x42bd64 VUCOMISD	(%R15,%R8,8),%XMM0    [3]

0x42bd6a JAE	42bcbd

0x42bd70 MOVQ	$0x1,(%R12,%R8,8)    [2]

0x42bd78 MOV	-0x20(%RDI),%R8    [1]

0x42bd7c VUCOMISD	(%R15,%R8,8),%XMM0    [3]

0x42bd82 JAE	42bccd

0x42bd88 MOVQ	$0x1,(%R12,%R8,8)    [2]

0x42bd90 MOV	-0x18(%RDI),%R8    [1]

0x42bd94 VUCOMISD	(%R15,%R8,8),%XMM0    [3]

0x42bd9a JAE	42bcdd

0x42bda0 MOVQ	$0x1,(%R12,%R8,8)    [2]

0x42bda8 MOV	-0x10(%RDI),%R8    [1]

0x42bdac VUCOMISD	(%R15,%R8,8),%XMM0    [3]

0x42bdb2 JAE	42bced

0x42bdb8 MOVQ	$0x1,(%R12,%R8,8)    [2]

0x42bdc0 MOV	-0x8(%RDI),%R8    [1]

0x42bdc4 VUCOMISD	(%R15,%R8,8),%XMM0    [3]

0x42bdca JAE	42bcfd

0x42bdd0 MOVQ	$0x1,(%R12,%R8,8)    [2]

0x42bdd8 MOV	(%RDI),%R8    [1]

0x42bddb VUCOMISD	(%R15,%R8,8),%XMM0    [3]

0x42bde1 JAE	42bc80

0x42bde7 MOVQ	$0x1,(%R12,%R8,8)    [2]

0x42bdef JMP	42bc80

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2327 - 2334

--------------------------------------------------------------------------------

2327: #pragma omp parallel for private(ig, i) HYPRE_SMP_SCHEDULE

2328: #endif

2329:         for (ig = 0; ig < graph_size; ig++)

2330:         {

2331:            i = graph_array[ig];

2332:            if (measure_array[i] > 1)

2333:            {

2334:               CF_marker[i] = 1;

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.27
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.27
Bottlenecks	P0, P6,
Function	hypre_BoomerAMGCoarsenPMIS.extracted.25
Source	par_coarsen.c:2327-2334
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	15.50
CQA cycles if no scalar integer	15.50
CQA cycles if FP arith vectorized	15.50
CQA cycles if fully vectorized	1.88
Front-end cycles	12.17
P0 cycles	15.50
P1 cycles	0.00
P2 cycles	10.00
P3 cycles	10.00
P4 cycles	4.00
P5 cycles	0.00
P6 cycles	15.50
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.00
P11 cycles	10.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	58.00
Nb uops	73.00
Nb loads	30.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.61
Bytes prefetched	0.00
Bytes loaded	240.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.33
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.27
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.27
Bottlenecks	P0, P6,
Function	hypre_BoomerAMGCoarsenPMIS.extracted.25
Source	par_coarsen.c:2327-2334
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	15.50
CQA cycles if no scalar integer	15.50
CQA cycles if FP arith vectorized	15.50
CQA cycles if fully vectorized	1.88
Front-end cycles	12.17
P0 cycles	15.50
P1 cycles	0.00
P2 cycles	10.00
P3 cycles	10.00
P4 cycles	4.00
P5 cycles	0.00
P6 cycles	15.50
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.00
P11 cycles	10.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	58.00
Nb uops	73.00
Nb loads	30.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.61
Bytes prefetched	0.00
Bytes loaded	240.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.33
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCoarsenPMIS.extracted.25
Source file and lines	par_coarsen.c:2327-2334
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2327-2334.

It is main loop of related source loop which is unrolled by 8 (including vectorization).
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 256 paths individually, rerun with max-paths=256
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 256 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 15.50 to 1.87 cycles (8.27x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 15 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332

Type of elements and instruction set

15 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 240 bytes (30 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

General properties

nb instructions	58
nb uops	73
loop length	325
used x86 registers	5
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.17 cycles
front end	12.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	15.50	0.00	10.00	10.00	4.00	0.00	15.50	4.00	4.00	4.00	0.00	10.00
cycles	15.50	0.00	10.00	10.00	4.00	0.00	15.50	4.00	4.00	4.00	0.00	10.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.17
Dispatch	15.50
Overall L1	15.50

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.50 cycles. At this rate:

8% of peak load performance is reached (15.48 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.13 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42bc8d

Instruction	Nb FU	P0	P2	P3	P4	P6	P7	P8	P9	P11	Latency	Recip. throughput	Vectorization
ADD $0x40,%RDI	1	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %RSI	1	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 42bb9f <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x7f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOV -0x38(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JB 42bd40 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x220>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOV -0x30(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JB 42bd58 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x238>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOV -0x28(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JB 42bd70 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x250>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOV -0x20(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JB 42bd88 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x268>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOV -0x18(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JB 42bda0 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x280>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOV -0x10(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JB 42bdb8 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x298>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOV -0x8(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JB 42bdd0 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x2b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOV (%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42bc80 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x160>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
JMP 42bde7 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x2c7>	1	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOVQ $0x1,(%R12,%R8,8)	1	0	0	0	0.50	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOV -0x30(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42bcad <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x18d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R12,%R8,8)	1	0	0	0	0.50	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOV -0x28(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42bcbd <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x19d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R12,%R8,8)	1	0	0	0	0.50	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOV -0x20(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42bccd <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x1ad>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R12,%R8,8)	1	0	0	0	0.50	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOV -0x18(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42bcdd <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x1bd>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R12,%R8,8)	1	0	0	0	0.50	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOV -0x10(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42bced <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x1cd>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R12,%R8,8)	1	0	0	0	0.50	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOV -0x8(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42bcfd <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x1dd>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R12,%R8,8)	1	0	0	0	0.50	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOV (%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42bc80 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x160>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R12,%R8,8)	1	0	0	0	0.50	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
JMP 42bc80 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x160>	1	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	hypre_BoomerAMGCoarsenPMIS.extracted.25
Source file and lines	par_coarsen.c:2327-2334
Module	exec

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 256 paths individually, rerun with max-paths=256
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 15 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332

Type of elements and instruction set

15 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

General properties

nb instructions	58
nb uops	73
loop length	325
used x86 registers	5
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.17 cycles
front end	12.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	15.50	0.00	10.00	10.00	4.00	0.00	15.50	4.00	4.00	4.00	0.00	10.00
cycles	15.50	0.00	10.00	10.00	4.00	0.00	15.50	4.00	4.00	4.00	0.00	10.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.17
Dispatch	15.50
Overall L1	15.50

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.50 cycles. At this rate:

8% of peak load performance is reached (15.48 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.13 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42bc8d

Instruction	Nb FU	P0	P2	P3	P4	P6	P7	P8	P9	P11	Latency	Recip. throughput	Vectorization
ADD $0x40,%RDI	1	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %RSI	1	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 42bb9f <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x7f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOV -0x38(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JB 42bd40 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x220>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOV -0x30(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JB 42bd58 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x238>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOV -0x28(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JB 42bd70 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x250>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOV -0x20(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JB 42bd88 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x268>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOV -0x18(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JB 42bda0 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x280>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOV -0x10(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JB 42bdb8 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x298>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOV -0x8(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JB 42bdd0 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x2b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOV (%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42bc80 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x160>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
JMP 42bde7 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x2c7>	1	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOVQ $0x1,(%R12,%R8,8)	1	0	0	0	0.50	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOV -0x30(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42bcad <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x18d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R12,%R8,8)	1	0	0	0	0.50	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOV -0x28(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42bcbd <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x19d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R12,%R8,8)	1	0	0	0	0.50	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOV -0x20(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42bccd <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x1ad>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R12,%R8,8)	1	0	0	0	0.50	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOV -0x18(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42bcdd <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x1bd>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R12,%R8,8)	1	0	0	0	0.50	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOV -0x10(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42bced <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x1cd>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R12,%R8,8)	1	0	0	0	0.50	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOV -0x8(%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42bcfd <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x1dd>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R12,%R8,8)	1	0	0	0	0.50	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOV (%RDI),%R8	1	0	0.33	0.33	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%R15,%R8,8),%XMM0	2	1	0.33	0.33	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42bc80 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x160>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R12,%R8,8)	1	0	0	0	0.50	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
JMP 42bc80 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x160>	1	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code