OV - exec - Loop 2545

0x4ad700 INC	%R9

0x4ad703 MOV	-0x58(%RBP),%RSI

0x4ad707 CMP	0x8(%R13,%RSI,8),%R9

0x4ad70c MOV	-0x80(%RBP),%RBX

0x4ad710 JGE	4ad880

0x4ad716 MOV	(%R12,%R9,8),%R10

0x4ad71a MOV	-0x60(%RBP),%R11

0x4ad71e CMPQ	$0,(%R11,%R10,8)

0x4ad723 JLE	4ad742

0x4ad725 MOV	0x78(%RBP),%RSI

0x4ad729 MOV	(%RSI,%R10,8),%R11

0x4ad72d MOV	-0x40(%RBP),%RSI

0x4ad731 CMP	%RDX,(%RSI,%R11,8)

0x4ad735 JGE	4ad742

0x4ad737 MOV	%R8,(%RSI,%R11,8)

0x4ad73b INC	%R8

0x4ad73e MOV	%R8,-0x30(%RBP)

0x4ad742 MOV	(%R13,%R10,8),%R11

0x4ad747 MOV	0x8(%R13,%R10,8),%RBX

0x4ad74c JMP	4ad783

  (2547) 0x4ad780 INC	%R11

  (2547) 0x4ad783 CMP	%RBX,%R11

  (2547) 0x4ad786 JGE	4ad7c0

  (2547) 0x4ad788 MOV	(%R12,%R11,8),%R15

  (2547) 0x4ad78c MOV	-0x60(%RBP),%RSI

  (2547) 0x4ad790 CMPQ	$0,(%RSI,%R15,8)

  (2547) 0x4ad795 JLE	4ad780

  (2547) 0x4ad797 MOV	0x78(%RBP),%RSI

  (2547) 0x4ad79b MOV	(%RSI,%R15,8),%R15

  (2547) 0x4ad79f CMP	%RAX,%R15

  (2547) 0x4ad7a2 JE	4ad780

  (2547) 0x4ad7a4 MOV	-0x40(%RBP),%RSI

  (2547) 0x4ad7a8 CMP	%RDX,(%RSI,%R15,8)

  (2547) 0x4ad7ac JGE	4ad780

  (2547) 0x4ad7ae MOV	%R8,(%RSI,%R15,8)

  (2547) 0x4ad7b2 INC	%R8

  (2547) 0x4ad7b5 MOV	%R8,-0x30(%RBP)

  (2547) 0x4ad7b9 MOV	0x8(%R13,%R10,8),%RBX

  (2547) 0x4ad7be JMP	4ad780

0x4ad7c0 MOV	0x10(%RBP),%RSI

0x4ad7c4 MOV	(%RSI,%R10,8),%R11

0x4ad7c8 MOV	0x8(%RSI,%R10,8),%RBX

0x4ad7cd JMP	4ad803

  (2546) 0x4ad800 INC	%R11

  (2546) 0x4ad803 CMP	%RBX,%R11

  (2546) 0x4ad806 JGE	4ad700

  (2546) 0x4ad80c MOV	0x18(%RBP),%RSI

  (2546) 0x4ad810 MOV	(%RSI,%R11,8),%R15

  (2546) 0x4ad814 MOV	0x70(%RBP),%RSI

  (2546) 0x4ad818 CMPQ	$0,(%RSI,%R15,8)

  (2546) 0x4ad81d JLE	4ad800

  (2546) 0x4ad81f MOV	0x80(%RBP),%RSI

  (2546) 0x4ad826 MOV	(%RSI,%R15,8),%R15

  (2546) 0x4ad82a CMP	%RCX,(%R14,%R15,8)

  (2546) 0x4ad82e JGE	4ad800

  (2546) 0x4ad830 MOV	%RDI,(%R14,%R15,8)

  (2546) 0x4ad834 INC	%RDI

  (2546) 0x4ad837 MOV	%RDI,-0x38(%RBP)

  (2546) 0x4ad83b MOV	0x10(%RBP),%RSI

  (2546) 0x4ad83f MOV	0x8(%RSI,%R10,8),%RBX

  (2546) 0x4ad844 JMP	4ad800

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1731 - 1765

--------------------------------------------------------------------------------

1731:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

1732:              {

1733:                  i2 = S_diag_j[jj1];

1734:                  if (CF_marker[i2] > 0)

1735:                  {

1736:                     index = fine_to_coarse[i2];

1737:                     if (S_marker[index] < jj_row_begin_diag)

1738:                     {

1739:                        S_marker[index] = num_nonzeros_diag;

1740:                        num_nonzeros_diag++;

1741:                     }

1742:                  }

1743:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

1744:                  {

1745:                     i3 = S_diag_j[jj2];

1746:                     if (CF_marker[i3] > 0)

1747:                     {

1748:                        index = fine_to_coarse[i3];

1749:                        if (index != ic && S_marker[index] < jj_row_begin_diag)

1750:                        {

1751:                           S_marker[index] = num_nonzeros_diag;

1752:                           num_nonzeros_diag++;

1753:                        }

1754:                     }

1755:                  }

1756:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

1757:                  {

1758:                     i3 = S_offd_j[jj2];

1759:                     if (CF_marker_offd[i3] > 0)

1760:                     {

1761:                        index = map_S_to_C[i3];

1762:                        if (S_marker_offd[index] < jj_row_begin_offd)

1763:                        {

1764:                           S_marker_offd[index] = num_nonzeros_offd;

1765:                           num_nonzeros_offd++;

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15
Bottlenecks	P2, P3, P11,
Function	hypre_BoomerAMGCreate2ndS.extracted.17
Source	par_strength.c:1731-1740,par_strength.c:1743-1743,par_strength.c:1756-1756
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	0.63
Front-end cycles	4.33
P0 cycles	1.50
P1 cycles	1.00
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	1.50
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	1.00
P11 cycles	5.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	24.00
Nb loads	15.00
Nb stores	2.00
Nb stack references	7.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.20
Bytes prefetched	0.00
Bytes loaded	120.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15
Bottlenecks	P2, P3, P11,
Function	hypre_BoomerAMGCreate2ndS.extracted.17
Source	par_strength.c:1731-1740,par_strength.c:1743-1743,par_strength.c:1756-1756
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	0.63
Front-end cycles	4.33
P0 cycles	1.50
P1 cycles	1.00
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	1.50
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	1.00
P11 cycles	5.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	24.00
Nb loads	15.00
Nb stores	2.00
Nb stack references	7.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.20
Bytes prefetched	0.00
Bytes loaded	120.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCreate2ndS.extracted.17
Source file and lines	par_strength.c:1731-1765
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1731-1765.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1731-1740,1743,1756.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=24
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 24 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.00 to 0.62 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by reading data from caches/RAM (load units are a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.00 to 4.33 cycles (1.15x speedup).

Workaround

Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 120 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	24
nb uops	24
loop length	93
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.33 cycles
front end	4.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.50	1.00	5.00	5.00	1.00	1.00	1.50	1.00	1.00	1.00	1.00	5.00
cycles	1.50	1.00	5.00	5.00	1.00	1.00	1.50	1.00	1.00	1.00	1.00	5.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.33
Dispatch	5.00
Overall L1	5.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

12% of peak load performance is reached (24.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.20 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4ad716

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x58(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP 0x8(%R13,%RSI,8),%R9	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x80(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JGE 4ad880 <hypre_BoomerAMGCreate2ndS.extracted.17+0x3c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R12,%R9,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x60(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0,(%R11,%R10,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JLE 4ad742 <hypre_BoomerAMGCreate2ndS.extracted.17+0x282>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x78(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RSI,%R10,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x40(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDX,(%RSI,%R11,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 4ad742 <hypre_BoomerAMGCreate2ndS.extracted.17+0x282>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,(%RSI,%R11,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%R13,%R10,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R13,%R10,8),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 4ad783 <hypre_BoomerAMGCreate2ndS.extracted.17+0x2c3>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV 0x10(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RSI,%R10,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RSI,%R10,8),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 4ad803 <hypre_BoomerAMGCreate2ndS.extracted.17+0x343>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Function	hypre_BoomerAMGCreate2ndS.extracted.17
Source file and lines	par_strength.c:1731-1765
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1731-1765.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1731-1740,1743,1756.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=24
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 24 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.00 to 0.62 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by reading data from caches/RAM (load units are a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.00 to 4.33 cycles (1.15x speedup).

Workaround

Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 120 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	24
nb uops	24
loop length	93
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.33 cycles
front end	4.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.50	1.00	5.00	5.00	1.00	1.00	1.50	1.00	1.00	1.00	1.00	5.00
cycles	1.50	1.00	5.00	5.00	1.00	1.00	1.50	1.00	1.00	1.00	1.00	5.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.33
Dispatch	5.00
Overall L1	5.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

12% of peak load performance is reached (24.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.20 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4ad716

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x58(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP 0x8(%R13,%RSI,8),%R9	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x80(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JGE 4ad880 <hypre_BoomerAMGCreate2ndS.extracted.17+0x3c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R12,%R9,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x60(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0,(%R11,%R10,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JLE 4ad742 <hypre_BoomerAMGCreate2ndS.extracted.17+0x282>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x78(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RSI,%R10,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x40(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDX,(%RSI,%R11,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 4ad742 <hypre_BoomerAMGCreate2ndS.extracted.17+0x282>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,(%RSI,%R11,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%R13,%R10,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R13,%R10,8),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 4ad783 <hypre_BoomerAMGCreate2ndS.extracted.17+0x2c3>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV 0x10(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RSI,%R10,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RSI,%R10,8),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 4ad803 <hypre_BoomerAMGCreate2ndS.extracted.17+0x343>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code