OV - exec - Loop 2450

0x4ac640 CMP	%RAX,%RDX

0x4ac643 MOV	0x10(%RBP),%RBX

0x4ac647 JE	4ac780

0x4ac64d MOV	%RDX,%R9

0x4ac650 MOV	0x50(%RBP),%RDX

0x4ac654 LEA	(%RDX,%R9,8),%RDX

0x4ac658 ADD	%RDI,(%RDX)

0x4ac65b MOV	0x60(%RBP),%RDX

0x4ac65f ADD	%R8,(%RDX,%R9,8)

0x4ac663 MOV	(%RBX,%R9,8),%R10

0x4ac667 MOV	0x8(%RBX,%R9,8),%R11

0x4ac66c LEA	0x1(%R9),%RDX

0x4ac670 CMP	%R11,%R10

0x4ac673 JGE	4ac700

0x4ac679 MOV	0x50(%RBP),%RBX

0x4ac67d LEA	(%RBX,%R9,8),%RBX

0x4ac681 MOV	(%RBX),%R15

0x4ac684 JMP	4ac6c8

  (2452) 0x4ac6c0 INC	%R10

  (2452) 0x4ac6c3 CMP	%R11,%R10

  (2452) 0x4ac6c6 JGE	4ac700

  (2452) 0x4ac6c8 MOV	(%R12,%R10,8),%RBX

  (2452) 0x4ac6cc TEST	%RBX,%RBX

  (2452) 0x4ac6cf JS	4ac6c0

  (2452) 0x4ac6d1 MOV	%RBX,(%RSI,%R15,8)

  (2452) 0x4ac6d5 INC	%R15

  (2452) 0x4ac6d8 MOV	0x10(%RBP),%R11

  (2452) 0x4ac6dc MOV	(%R11,%RDX,8),%R11

  (2452) 0x4ac6e0 JMP	4ac6c0

0x4ac700 MOV	0x20(%RBP),%R11

0x4ac704 MOV	(%R11,%R9,8),%R10

0x4ac708 MOV	(%R11,%RDX,8),%R11

0x4ac70c CMP	%R11,%R10

0x4ac70f JGE	4ac640

0x4ac715 MOV	0x60(%RBP),%RBX

0x4ac719 MOV	(%RBX,%R9,8),%R9

0x4ac71d JMP	4ac74c

  (2451) 0x4ac740 INC	%R10

  (2451) 0x4ac743 CMP	%R11,%R10

  (2451) 0x4ac746 JGE	4ac640

  (2451) 0x4ac74c MOV	(%R13,%R10,8),%RBX

  (2451) 0x4ac751 TEST	%RBX,%RBX

  (2451) 0x4ac754 JS	4ac740

  (2451) 0x4ac756 MOV	%RBX,(%RCX,%R9,8)

  (2451) 0x4ac75a INC	%R9

  (2451) 0x4ac75d MOV	0x20(%RBP),%R11

  (2451) 0x4ac761 MOV	(%R11,%RDX,8),%R11

  (2451) 0x4ac765 JMP	4ac740

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 492 - 513

--------------------------------------------------------------------------------

492:    for (i = start; i < stop; i++)

493:    {

494:       S_diag_i[i] += jS_diag;

495:       S_offd_i[i] += jS_offd;

496:

497:       jS = S_diag_i[i];

498:       for (jA = A_diag_i[i]; jA < A_diag_i[i+1]; jA++)

499:       {

500:          if (S_temp_diag_j[jA] > -1)

501:          {

502:             S_diag_j[jS]    = S_temp_diag_j[jA];

503:             jS++;

504:          }

505:       }

506:

507:       jS = S_offd_i[i];

508:       for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

509:       {

510:          if (S_temp_offd_j[jA] > -1)

511:          {

512:             S_offd_j[jS]    = S_temp_offd_j[jA];

513:             jS++;

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.75
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGCreateS.extracted
Source	par_strength.c:492-498,par_strength.c:507-508
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.67
CQA cycles if no scalar integer	4.67
CQA cycles if FP arith vectorized	4.67
CQA cycles if fully vectorized	0.58
Front-end cycles	4.67
P0 cycles	1.70
P1 cycles	1.60
P2 cycles	4.67
P3 cycles	4.67
P4 cycles	1.00
P5 cycles	1.60
P6 cycles	1.50
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	1.60
P11 cycles	4.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	28.00
Nb loads	14.00
Nb stores	2.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.43
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.75
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGCreateS.extracted
Source	par_strength.c:492-498,par_strength.c:507-508
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.67
CQA cycles if no scalar integer	4.67
CQA cycles if FP arith vectorized	4.67
CQA cycles if fully vectorized	0.58
Front-end cycles	4.67
P0 cycles	1.70
P1 cycles	1.60
P2 cycles	4.67
P3 cycles	4.67
P4 cycles	1.00
P5 cycles	1.60
P6 cycles	1.50
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	1.60
P11 cycles	4.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	28.00
Nb loads	14.00
Nb stores	2.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.43
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCreateS.extracted
Source file and lines	par_strength.c:492-513
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:492-513.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:492-498,507-508.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=9
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 9 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.67 to 0.58 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:494
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:495

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 112 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	26
nb uops	28
loop length	101
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.67 cycles
front end	4.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.70	1.60	4.67	4.67	1.00	1.60	1.50	1.00	1.00	1.00	1.60	4.67
cycles	1.70	1.60	4.67	4.67	1.00	1.60	1.50	1.00	1.00	1.00	1.60	4.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.67
Dispatch	4.67
Overall L1	4.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.67 cycles. At this rate:

12% of peak load performance is reached (24.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.43 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.67 to 1.70 cycles (2.75x speedup).

ASM code

In the binary file, the address of the loop is: 4ac64d

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
CMP %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x10(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 4ac780 <hypre_BoomerAMGCreateS.extracted+0x13d0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x50(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%R9,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RDI,(%RDX)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV 0x60(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R8,(%RDX,%R9,8)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV (%RBX,%R9,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RBX,%R9,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%R9),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R11,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4ac700 <hypre_BoomerAMGCreateS.extracted+0x1350>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x50(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RBX,%R9,8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 4ac6c8 <hypre_BoomerAMGCreateS.extracted+0x1318>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV 0x20(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R11,%R9,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R11,%RDX,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R11,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JGE 4ac640 <hypre_BoomerAMGCreateS.extracted+0x1290>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x60(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX,%R9,8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 4ac74c <hypre_BoomerAMGCreateS.extracted+0x139c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Function	hypre_BoomerAMGCreateS.extracted
Source file and lines	par_strength.c:492-513
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:492-513.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:492-498,507-508.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=9
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 9 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.67 to 0.58 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:494
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:495

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 112 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	26
nb uops	28
loop length	101
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.67 cycles
front end	4.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.70	1.60	4.67	4.67	1.00	1.60	1.50	1.00	1.00	1.00	1.60	4.67
cycles	1.70	1.60	4.67	4.67	1.00	1.60	1.50	1.00	1.00	1.00	1.60	4.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.67
Dispatch	4.67
Overall L1	4.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.67 cycles. At this rate:

12% of peak load performance is reached (24.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.43 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.67 to 1.70 cycles (2.75x speedup).

ASM code

In the binary file, the address of the loop is: 4ac64d

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
CMP %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x10(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 4ac780 <hypre_BoomerAMGCreateS.extracted+0x13d0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x50(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%R9,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RDI,(%RDX)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV 0x60(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R8,(%RDX,%R9,8)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV (%RBX,%R9,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RBX,%R9,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%R9),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R11,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4ac700 <hypre_BoomerAMGCreateS.extracted+0x1350>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x50(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RBX,%R9,8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 4ac6c8 <hypre_BoomerAMGCreateS.extracted+0x1318>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV 0x20(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R11,%R9,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R11,%RDX,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R11,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JGE 4ac640 <hypre_BoomerAMGCreateS.extracted+0x1290>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x60(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX,%R9,8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 4ac74c <hypre_BoomerAMGCreateS.extracted+0x139c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code