OV - exec - Loop 1321

	Loop Id: 1321	Module: exec	Source: par_lr_interp.c:1624-1627	Coverage: 0.11%

0x467b40 ADD	$0x20,%RAX

0x467b44 DEC	%R12

0x467b47 JE	467829

0x467b4d MOV	-0xb0(%RBP),%RDX    [9]

0x467b54 MOV	-0x18(%RDX,%RAX,1),%RDX    [8]

0x467b59 XOR	%R11D,%R11D

0x467b5c CMP	%RDI,(%RBX,%RDX,8)    [10]

0x467b60 SETGE	%R11B

0x467b64 XOR	%R15D,%R15D

0x467b67 CMP	%R13,%RDX

0x467b6a SETE	%R15B

0x467b6e CMP	%R11B,%R15B

0x467b71 CMOVA	%R15D,%R11D

0x467b75 CMP	$0x1,%R11B

0x467b79 JNE	467b9a

0x467b7b MOV	-0x48(%RBP),%RDX    [9]

0x467b7f VMOVSD	-0x18(%RDX,%RAX,1),%XMM8    [7]

0x467b85 VMULSD	%XMM6,%XMM8,%XMM9

0x467b89 VADDSD	%XMM5,%XMM8,%XMM8

0x467b8d VCMPSD	$0x1,%XMM7,%XMM9,%K1

0x467b94 VMOVSD	%XMM8,%XMM5,%XMM5{%K1}

0x467b9a MOV	-0xb0(%RBP),%RDX    [9]

0x467ba1 MOV	-0x10(%RDX,%RAX,1),%RDX    [6]

0x467ba6 XOR	%R11D,%R11D

0x467ba9 CMP	%RDI,(%RBX,%RDX,8)    [10]

0x467bad SETGE	%R11B

0x467bb1 XOR	%R15D,%R15D

0x467bb4 CMP	%R13,%RDX

0x467bb7 SETE	%R15B

0x467bbb CMP	%R11B,%R15B

0x467bbe CMOVA	%R15D,%R11D

0x467bc2 CMP	$0x1,%R11B

0x467bc6 JNE	467be7

0x467bc8 MOV	-0x48(%RBP),%RDX    [9]

0x467bcc VMOVSD	-0x10(%RDX,%RAX,1),%XMM8    [5]

0x467bd2 VMULSD	%XMM6,%XMM8,%XMM9

0x467bd6 VADDSD	%XMM5,%XMM8,%XMM8

0x467bda VCMPSD	$0x1,%XMM7,%XMM9,%K1

0x467be1 VMOVSD	%XMM8,%XMM5,%XMM5{%K1}

0x467be7 MOV	-0xb0(%RBP),%RDX    [9]

0x467bee MOV	-0x8(%RDX,%RAX,1),%RDX    [4]

0x467bf3 XOR	%R11D,%R11D

0x467bf6 CMP	%RDI,(%RBX,%RDX,8)    [10]

0x467bfa SETGE	%R11B

0x467bfe XOR	%R15D,%R15D

0x467c01 CMP	%R13,%RDX

0x467c04 SETE	%R15B

0x467c08 CMP	%R11B,%R15B

0x467c0b CMOVA	%R15D,%R11D

0x467c0f CMP	$0x1,%R11B

0x467c13 JNE	467c34

0x467c15 MOV	-0x48(%RBP),%RDX    [9]

0x467c19 VMOVSD	-0x8(%RDX,%RAX,1),%XMM8    [3]

0x467c1f VMULSD	%XMM6,%XMM8,%XMM9

0x467c23 VADDSD	%XMM5,%XMM8,%XMM8

0x467c27 VCMPSD	$0x1,%XMM7,%XMM9,%K1

0x467c2e VMOVSD	%XMM8,%XMM5,%XMM5{%K1}

0x467c34 MOV	-0xb0(%RBP),%RDX    [9]

0x467c3b MOV	(%RDX,%RAX,1),%RDX    [2]

0x467c3f XOR	%R11D,%R11D

0x467c42 CMP	%RDI,(%RBX,%RDX,8)    [10]

0x467c46 SETGE	%R11B

0x467c4a XOR	%R15D,%R15D

0x467c4d CMP	%R13,%RDX

0x467c50 SETE	%R15B

0x467c54 CMP	%R11B,%R15B

0x467c57 CMOVA	%R15D,%R11D

0x467c5b CMP	$0x1,%R11B

0x467c5f JNE	467b40

0x467c65 MOV	-0x48(%RBP),%RDX    [9]

0x467c69 VMOVSD	(%RDX,%RAX,1),%XMM8    [1]

0x467c6e VMULSD	%XMM6,%XMM8,%XMM9

0x467c72 VADDSD	%XMM5,%XMM8,%XMM8

0x467c76 VCMPSD	$0x1,%XMM7,%XMM9,%K1

0x467c7d VMOVSD	%XMM8,%XMM5,%XMM5{%K1}

0x467c83 JMP	467b40

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1624 - 1627

--------------------------------------------------------------------------------

1624:                for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1625:                {

1626:                  i2 = A_diag_j[jj1];

1627:                  if((P_marker[i2] >= jj_begin_row || i2 == i) && (sgn*A_diag_data[jj1]) < 0)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	2.05
CQA speedup if FP arith vectorized	3.12
CQA speedup if fully vectorized	12.04
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.31
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildExtPIInterp.extracted
Source	par_lr_interp.c:1624-1627
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	14.00
CQA cycles if no scalar integer	6.83
CQA cycles if FP arith vectorized	4.49
CQA cycles if fully vectorized	1.16
Front-end cycles	14.00
P0 cycles	10.70
P1 cycles	10.60
P2 cycles	6.67
P3 cycles	6.67
P4 cycles	0.00
P5 cycles	10.60
P6 cycles	10.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	10.60
P11 cycles	6.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	76.00
Nb uops	80.00
Nb loads	20.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.57
Nb FLOP add-sub	4.00
Nb FLOP mul	4.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.43
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.74
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.25

Metric	Value
CQA speedup if no scalar integer	2.05
CQA speedup if FP arith vectorized	3.12
CQA speedup if fully vectorized	12.04
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.31
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildExtPIInterp.extracted
Source	par_lr_interp.c:1624-1627
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	14.00
CQA cycles if no scalar integer	6.83
CQA cycles if FP arith vectorized	4.49
CQA cycles if fully vectorized	1.16
Front-end cycles	14.00
P0 cycles	10.70
P1 cycles	10.60
P2 cycles	6.67
P3 cycles	6.67
P4 cycles	0.00
P5 cycles	10.60
P6 cycles	10.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	10.60
P11 cycles	6.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	76.00
Nb uops	80.00
Nb loads	20.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.57
Nb FLOP add-sub	4.00
Nb FLOP mul	4.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.43
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.74
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildExtPIInterp.extracted
Source file and lines	par_lr_interp.c:1624-1627
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1624-1627.

It is main loop of related source loop which is unrolled by 4 (including vectorization).
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 16 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.00 to 6.83 cycles (2.05x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 14.00 to 1.16 cycles (12.04x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVA: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1627
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1627
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1627
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1627

Type of elements and instruction set

12 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction
4: multiply

The binary loop is loading 160 bytes (20 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	76
nb uops	80
loop length	328
used x86 registers	9
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.00 cycles
front end	14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.70	10.60	6.67	6.67	0.00	10.60	10.50	0.00	0.00	0.00	10.60	6.67
cycles	10.70	10.60	6.67	6.67	0.00	10.60	10.50	0.00	0.00	0.00	10.60	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.00
Dispatch	10.70
Overall L1	14.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.00 cycles. At this rate:

5% of peak load performance is reached (11.43 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 14.00 to 10.70 cycles (1.31x speedup).

ASM code

In the binary file, the address of the loop is: 467b4d

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
ADD $0x20,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %R12	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 467829 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1cc9>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0xb0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x18(%RDX,%RAX,1),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RDI,(%RBX,%RDX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
SETGE %R11B	1	0.50	0	0	0	0	0.50	0	0	1	0.50	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CMP %R13,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SETE %R15B	1	0.50	0	0	0	0	0.50	0	0	1	0.50	N/A
CMP %R11B,%R15B	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
CMOVA %R15D,%R11D	2	1	0	0	0	0	1	0	0	1-2	1	N/A
CMP $0x1,%R11B	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 467b9a <hypre_BoomerAMGBuildExtPIInterp.extracted+0x203a>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x18(%RDX,%RAX,1),%XMM8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM6,%XMM8,%XMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM5,%XMM8,%XMM8	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VCMPSD $0x1,%XMM7,%XMM9,%K1	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM8,%XMM5,%XMM5{%K1}	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	scal (12.5%)
MOV -0xb0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x10(%RDX,%RAX,1),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RDI,(%RBX,%RDX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
SETGE %R11B	1	0.50	0	0	0	0	0.50	0	0	1	0.50	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CMP %R13,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SETE %R15B	1	0.50	0	0	0	0	0.50	0	0	1	0.50	N/A
CMP %R11B,%R15B	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
CMOVA %R15D,%R11D	2	1	0	0	0	0	1	0	0	1-2	1	N/A
CMP $0x1,%R11B	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 467be7 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x2087>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x10(%RDX,%RAX,1),%XMM8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM6,%XMM8,%XMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM5,%XMM8,%XMM8	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VCMPSD $0x1,%XMM7,%XMM9,%K1	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM8,%XMM5,%XMM5{%K1}	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	scal (12.5%)
MOV -0xb0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x8(%RDX,%RAX,1),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RDI,(%RBX,%RDX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
SETGE %R11B	1	0.50	0	0	0	0	0.50	0	0	1	0.50	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CMP %R13,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SETE %R15B	1	0.50	0	0	0	0	0.50	0	0	1	0.50	N/A
CMP %R11B,%R15B	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
CMOVA %R15D,%R11D	2	1	0	0	0	0	1	0	0	1-2	1	N/A
CMP $0x1,%R11B	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 467c34 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x20d4>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x8(%RDX,%RAX,1),%XMM8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM6,%XMM8,%XMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM5,%XMM8,%XMM8	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VCMPSD $0x1,%XMM7,%XMM9,%K1	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM8,%XMM5,%XMM5{%K1}	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	scal (12.5%)
MOV -0xb0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RAX,1),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RDI,(%RBX,%RDX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
SETGE %R11B	1	0.50	0	0	0	0	0.50	0	0	1	0.50	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CMP %R13,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SETE %R15B	1	0.50	0	0	0	0	0.50	0	0	1	0.50	N/A
CMP %R11B,%R15B	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
CMOVA %R15D,%R11D	2	1	0	0	0	0	1	0	0	1-2	1	N/A
CMP $0x1,%R11B	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 467b40 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1fe0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RDX,%RAX,1),%XMM8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM6,%XMM8,%XMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM5,%XMM8,%XMM8	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VCMPSD $0x1,%XMM7,%XMM9,%K1	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM8,%XMM5,%XMM5{%K1}	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	scal (12.5%)
JMP 467b40 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1fe0>	1	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	hypre_BoomerAMGBuildExtPIInterp.extracted
Source file and lines	par_lr_interp.c:1624-1627
Module	exec

Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.00 to 6.83 cycles (2.05x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVA: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1627
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1627
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1627
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1627

Type of elements and instruction set

12 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction
4: multiply

The binary loop is loading 160 bytes (20 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	76
nb uops	80
loop length	328
used x86 registers	9
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.00 cycles
front end	14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.70	10.60	6.67	6.67	0.00	10.60	10.50	0.00	0.00	0.00	10.60	6.67
cycles	10.70	10.60	6.67	6.67	0.00	10.60	10.50	0.00	0.00	0.00	10.60	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.00
Dispatch	10.70
Overall L1	14.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.00 cycles. At this rate:

5% of peak load performance is reached (11.43 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 467b4d

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
ADD $0x20,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %R12	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 467829 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1cc9>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0xb0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x18(%RDX,%RAX,1),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RDI,(%RBX,%RDX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
SETGE %R11B	1	0.50	0	0	0	0	0.50	0	0	1	0.50	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CMP %R13,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SETE %R15B	1	0.50	0	0	0	0	0.50	0	0	1	0.50	N/A
CMP %R11B,%R15B	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
CMOVA %R15D,%R11D	2	1	0	0	0	0	1	0	0	1-2	1	N/A
CMP $0x1,%R11B	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 467b9a <hypre_BoomerAMGBuildExtPIInterp.extracted+0x203a>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x18(%RDX,%RAX,1),%XMM8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM6,%XMM8,%XMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM5,%XMM8,%XMM8	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VCMPSD $0x1,%XMM7,%XMM9,%K1	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM8,%XMM5,%XMM5{%K1}	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	scal (12.5%)
MOV -0xb0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x10(%RDX,%RAX,1),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RDI,(%RBX,%RDX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
SETGE %R11B	1	0.50	0	0	0	0	0.50	0	0	1	0.50	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CMP %R13,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SETE %R15B	1	0.50	0	0	0	0	0.50	0	0	1	0.50	N/A
CMP %R11B,%R15B	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
CMOVA %R15D,%R11D	2	1	0	0	0	0	1	0	0	1-2	1	N/A
CMP $0x1,%R11B	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 467be7 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x2087>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x10(%RDX,%RAX,1),%XMM8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM6,%XMM8,%XMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM5,%XMM8,%XMM8	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VCMPSD $0x1,%XMM7,%XMM9,%K1	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM8,%XMM5,%XMM5{%K1}	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	scal (12.5%)
MOV -0xb0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x8(%RDX,%RAX,1),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RDI,(%RBX,%RDX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
SETGE %R11B	1	0.50	0	0	0	0	0.50	0	0	1	0.50	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CMP %R13,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SETE %R15B	1	0.50	0	0	0	0	0.50	0	0	1	0.50	N/A
CMP %R11B,%R15B	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
CMOVA %R15D,%R11D	2	1	0	0	0	0	1	0	0	1-2	1	N/A
CMP $0x1,%R11B	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 467c34 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x20d4>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x8(%RDX,%RAX,1),%XMM8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM6,%XMM8,%XMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM5,%XMM8,%XMM8	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VCMPSD $0x1,%XMM7,%XMM9,%K1	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM8,%XMM5,%XMM5{%K1}	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	scal (12.5%)
MOV -0xb0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RAX,1),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RDI,(%RBX,%RDX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
SETGE %R11B	1	0.50	0	0	0	0	0.50	0	0	1	0.50	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CMP %R13,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SETE %R15B	1	0.50	0	0	0	0	0.50	0	0	1	0.50	N/A
CMP %R11B,%R15B	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
CMOVA %R15D,%R11D	2	1	0	0	0	0	1	0	0	1-2	1	N/A
CMP $0x1,%R11B	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 467b40 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1fe0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RDX,%RAX,1),%XMM8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM6,%XMM8,%XMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM5,%XMM8,%XMM8	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VCMPSD $0x1,%XMM7,%XMM9,%K1	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM8,%XMM5,%XMM5{%K1}	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	scal (12.5%)
JMP 467b40 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1fe0>	1	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code