OV - exec - Loop 1314

	Loop Id: 1314	Module: exec	Source: par_lr_interp.c:1221-1675 [...]	Coverage: 0.06%

0x467780 MOV	-0x80(%RBP),%RCX

0x467784 MOV	(%RCX),%RCX

0x467787 VMOVSD	(%RCX,%RAX,8),%XMM5

0x46778c MOV	-0x48(%RBP),%RDX

0x467790 VADDSD	(%RDX,%R9,8),%XMM5,%XMM5

0x467796 VMOVSD	%XMM5,(%RCX,%RAX,8)

0x46779b INC	%R9

0x46779e CMP	-0x98(%RBP),%R9

0x4677a5 JE	4676ad

0x4677ab MOV	-0xb0(%RBP),%RAX

0x4677b2 MOV	(%RAX,%R9,8),%R10

0x4677b6 MOV	(%RBX,%R10,8),%RAX

0x4677ba CMP	%RDI,%RAX

0x4677bd JGE	467780

0x4677bf CMP	%R12,%RAX

0x4677c2 JNE	467900

0x4677c8 MOV	-0x180(%RBP),%RCX

0x4677cf MOV	(%RCX,%R10,8),%R11

0x4677d3 VPXOR	%XMM5,%XMM5,%XMM5

0x4677d7 XOR	%EAX,%EAX

0x4677d9 MOV	-0x48(%RBP),%RDX

0x4677dd VUCOMISD	(%RDX,%R11,8),%XMM5

0x4677e3 MOV	%R10,-0xa8(%RBP)

0x4677ea MOV	0x8(%RCX,%R10,8),%RCX

0x4677ef SETBE	%AL

0x4677f2 LEA	-0x1(%RAX,%RAX,1),%RAX

0x4677f7 MOV	%RAX,-0x70(%RBP)

0x4677fb LEA	0x1(%R11),%R10

0x4677ff CMP	%RCX,%R10

0x467802 MOV	%R11,-0x68(%RBP)

0x467806 JGE	467940

0x46780c VCVTSI2SDQ	-0x70(%RBP),%XMM10,%XMM6

0x467812 NOT	%R11

0x467815 ADD	%RCX,%R11

0x467818 MOV	%R11,-0xd0(%RBP)

0x46781f CMP	$0x4,%R11

0x467823 JAE	467b00

0x467829 MOV	-0xd0(%RBP),%RDX

0x467830 MOV	%RDX,%RAX

0x467833 AND	$-0x4,%RAX

0x467837 CMP	%RDX,%RAX

0x46783a JAE	467940

0x467840 MOV	-0x68(%RBP),%RDX

0x467844 LEA	0x1(%RDX,%RAX,1),%RAX

0x467849 JMP	46788c

  (1320) 0x467880 INC	%RAX

  (1320) 0x467883 CMP	%RAX,%RCX

  (1320) 0x467886 JE	467940

  (1320) 0x46788c MOV	-0xb0(%RBP),%RDX

  (1320) 0x467893 MOV	(%RDX,%RAX,8),%RDX

  (1320) 0x467897 XOR	%R11D,%R11D

  (1320) 0x46789a CMP	%RDI,(%RBX,%RDX,8)

  (1320) 0x46789e SETGE	%R11B

  (1320) 0x4678a2 XOR	%R15D,%R15D

  (1320) 0x4678a5 CMP	%R13,%RDX

  (1320) 0x4678a8 SETE	%R15B

  (1320) 0x4678ac CMP	%R11B,%R15B

  (1320) 0x4678af CMOVA	%R15D,%R11D

  (1320) 0x4678b3 CMP	$0x1,%R11B

  (1320) 0x4678b7 JNE	467880

  (1320) 0x4678b9 MOV	-0x48(%RBP),%RDX

  (1320) 0x4678bd VMOVSD	(%RDX,%RAX,8),%XMM7

  (1320) 0x4678c2 VMULSD	%XMM6,%XMM7,%XMM8

  (1320) 0x4678c6 VADDSD	%XMM5,%XMM7,%XMM7

  (1320) 0x4678ca VCMPSD	$0x1,%XMM0,%XMM8,%K1

  (1320) 0x4678d1 VMOVSD	%XMM7,%XMM5,%XMM5{%K1}

  (1320) 0x4678d7 JMP	467880

0x467900 MOV	-0xe0(%RBP),%RAX

0x467907 CMPQ	$-0x3,(%RAX,%R10,8)

0x46790c JE	46779b

0x467912 CMPQ	$0x1,-0x178(%RBP)

0x46791a JE	467931

0x46791c MOV	-0x170(%RBP),%RCX

0x467923 MOV	(%RCX,%R13,8),%RAX

0x467927 CMP	(%RCX,%R10,8),%RAX

0x46792b JNE	46779b

0x467931 MOV	-0x48(%RBP),%RAX

0x467935 VADDSD	(%RAX,%R9,8),%XMM4,%XMM4

0x46793b JMP	46779b

0x467940 MOV	-0xb8(%RBP),%RAX

0x467947 MOV	(%RAX),%RAX

0x46794a MOV	%RAX,-0xd0(%RBP)

0x467951 CMP	$0x2,%RAX

0x467955 JL	467a00

0x46795b MOV	-0x150(%RBP),%RDX

0x467962 MOV	-0xa8(%RBP),%R11

0x467969 MOV	(%RDX,%R11,8),%RAX

0x46796d MOV	0x8(%RDX,%R11,8),%R12

0x467972 MOV	%R12,%R15

0x467975 SUB	%RAX,%R15

0x467978 JLE	467a00

0x46797e VCVTSI2SDQ	-0x70(%RBP),%XMM10,%XMM6

0x467984 CMP	$0x4,%R15

0x467988 MOV	%R15,-0xe8(%RBP)

0x46798f JAE	467cc0

0x467995 MOV	-0xe8(%RBP),%R11

0x46799c MOV	%R11,%RDX

0x46799f AND	$-0x4,%RDX

0x4679a3 CMP	%R11,%RDX

0x4679a6 JAE	467a00

0x4679a8 ADD	%RDX,%RAX

0x4679ab JMP	4679c8

  (1318) 0x4679c0 INC	%RAX

  (1318) 0x4679c3 CMP	%RAX,%R12

  (1318) 0x4679c6 JE	467a00

  (1318) 0x4679c8 MOV	-0x88(%RBP),%RDX

  (1318) 0x4679cf MOV	(%RDX,%RAX,8),%RDX

  (1318) 0x4679d3 CMP	%RSI,(%R14,%RDX,8)

  (1318) 0x4679d7 JL	4679c0

  (1318) 0x4679d9 MOV	-0x50(%RBP),%RDX

  (1318) 0x4679dd VMOVSD	(%RDX,%RAX,8),%XMM7

  (1318) 0x4679e2 VMULSD	%XMM6,%XMM7,%XMM8

  (1318) 0x4679e6 VADDSD	%XMM5,%XMM7,%XMM7

  (1318) 0x4679ea VCMPSD	$0x1,%XMM0,%XMM8,%K1

  (1318) 0x4679f1 VMOVSD	%XMM7,%XMM5,%XMM5{%K1}

  (1318) 0x4679f7 JMP	4679c0

0x467a00 VUCOMISD	%XMM0,%XMM5

0x467a04 MOV	-0x48(%RBP),%RAX

0x467a08 VMOVSD	(%RAX,%R9,8),%XMM6

0x467a0e JE	467ac0

0x467a14 VDIVSD	%XMM5,%XMM6,%XMM5

0x467a18 CMP	%RCX,%R10

0x467a1b MOV	-0x40(%RBP),%R12

0x467a1f JGE	467e91

0x467a25 VCVTSI2SDQ	-0x70(%RBP),%XMM10,%XMM6

0x467a2b MOV	-0x68(%RBP),%RDX

0x467a2f MOV	%EDX,%EAX

0x467a31 NOT	%EAX

0x467a33 ADD	%ECX,%EAX

0x467a35 TEST	$0x1,%AL

0x467a37 JE	467e88

0x467a3d MOV	-0xb0(%RBP),%RAX

0x467a44 MOV	0x8(%RAX,%RDX,8),%RAX

0x467a49 MOV	(%RBX,%RAX,8),%RDX

0x467a4d CMP	%RDI,%RDX

0x467a50 JL	467a7e

0x467a52 MOV	-0x48(%RBP),%R10

0x467a56 MOV	-0x68(%RBP),%R11

0x467a5a VMOVSD	0x8(%R10,%R11,8),%XMM7

0x467a61 VMULSD	%XMM6,%XMM7,%XMM8

0x467a65 VUCOMISD	%XMM0,%XMM8

0x467a69 JAE	467a7e

0x467a6b MOV	-0x80(%RBP),%R10

0x467a6f MOV	(%R10),%R10

0x467a72 VFMADD213SD	(%R10,%RDX,8),%XMM5,%XMM7

0x467a78 VMOVSD	%XMM7,(%R10,%RDX,8)

0x467a7e CMP	%R13,%RAX

0x467a81 JNE	467e80

0x467a87 MOV	-0x48(%RBP),%RAX

0x467a8b MOV	-0x68(%RBP),%RDX

0x467a8f VMOVSD	0x8(%RAX,%RDX,8),%XMM7

0x467a95 VMULSD	%XMM6,%XMM7,%XMM8

0x467a99 VFMADD213SD	%XMM4,%XMM5,%XMM7

0x467a9e VCMPSD	$0x1,%XMM0,%XMM8,%K1

0x467aa5 VMOVSD	%XMM7,%XMM4,%XMM4{%K1}

0x467aab JMP	467e84

0x467ac0 VADDSD	%XMM4,%XMM6,%XMM4

0x467ac4 MOV	-0x40(%RBP),%R12

0x467ac8 JMP	46779b

0x467b00 MOV	-0xd0(%RBP),%R12

0x467b07 SHR	$0x2,%R12

0x467b0b MOV	-0x68(%RBP),%RAX

0x467b0f LEA	0x20(,%RAX,8),%RAX

0x467b17 VXORPD	%XMM7,%XMM7,%XMM7

0x467b1b JMP	467b4d

  (1321) 0x467b40 ADD	$0x20,%RAX

  (1321) 0x467b44 DEC	%R12

  (1321) 0x467b47 JE	467829

  (1321) 0x467b4d MOV	-0xb0(%RBP),%RDX

  (1321) 0x467b54 MOV	-0x18(%RDX,%RAX,1),%RDX

  (1321) 0x467b59 XOR	%R11D,%R11D

  (1321) 0x467b5c CMP	%RDI,(%RBX,%RDX,8)

  (1321) 0x467b60 SETGE	%R11B

  (1321) 0x467b64 XOR	%R15D,%R15D

  (1321) 0x467b67 CMP	%R13,%RDX

  (1321) 0x467b6a SETE	%R15B

  (1321) 0x467b6e CMP	%R11B,%R15B

  (1321) 0x467b71 CMOVA	%R15D,%R11D

  (1321) 0x467b75 CMP	$0x1,%R11B

  (1321) 0x467b79 JNE	467b9a

  (1321) 0x467b7b MOV	-0x48(%RBP),%RDX

  (1321) 0x467b7f VMOVSD	-0x18(%RDX,%RAX,1),%XMM8

  (1321) 0x467b85 VMULSD	%XMM6,%XMM8,%XMM9

  (1321) 0x467b89 VADDSD	%XMM5,%XMM8,%XMM8

  (1321) 0x467b8d VCMPSD	$0x1,%XMM7,%XMM9,%K1

  (1321) 0x467b94 VMOVSD	%XMM8,%XMM5,%XMM5{%K1}

  (1321) 0x467b9a MOV	-0xb0(%RBP),%RDX

  (1321) 0x467ba1 MOV	-0x10(%RDX,%RAX,1),%RDX

  (1321) 0x467ba6 XOR	%R11D,%R11D

  (1321) 0x467ba9 CMP	%RDI,(%RBX,%RDX,8)

  (1321) 0x467bad SETGE	%R11B

  (1321) 0x467bb1 XOR	%R15D,%R15D

  (1321) 0x467bb4 CMP	%R13,%RDX

  (1321) 0x467bb7 SETE	%R15B

  (1321) 0x467bbb CMP	%R11B,%R15B

  (1321) 0x467bbe CMOVA	%R15D,%R11D

  (1321) 0x467bc2 CMP	$0x1,%R11B

  (1321) 0x467bc6 JNE	467be7

  (1321) 0x467bc8 MOV	-0x48(%RBP),%RDX

  (1321) 0x467bcc VMOVSD	-0x10(%RDX,%RAX,1),%XMM8

  (1321) 0x467bd2 VMULSD	%XMM6,%XMM8,%XMM9

  (1321) 0x467bd6 VADDSD	%XMM5,%XMM8,%XMM8

  (1321) 0x467bda VCMPSD	$0x1,%XMM7,%XMM9,%K1

  (1321) 0x467be1 VMOVSD	%XMM8,%XMM5,%XMM5{%K1}

  (1321) 0x467be7 MOV	-0xb0(%RBP),%RDX

  (1321) 0x467bee MOV	-0x8(%RDX,%RAX,1),%RDX

  (1321) 0x467bf3 XOR	%R11D,%R11D

  (1321) 0x467bf6 CMP	%RDI,(%RBX,%RDX,8)

  (1321) 0x467bfa SETGE	%R11B

  (1321) 0x467bfe XOR	%R15D,%R15D

  (1321) 0x467c01 CMP	%R13,%RDX

  (1321) 0x467c04 SETE	%R15B

  (1321) 0x467c08 CMP	%R11B,%R15B

  (1321) 0x467c0b CMOVA	%R15D,%R11D

  (1321) 0x467c0f CMP	$0x1,%R11B

  (1321) 0x467c13 JNE	467c34

  (1321) 0x467c15 MOV	-0x48(%RBP),%RDX

  (1321) 0x467c19 VMOVSD	-0x8(%RDX,%RAX,1),%XMM8

  (1321) 0x467c1f VMULSD	%XMM6,%XMM8,%XMM9

  (1321) 0x467c23 VADDSD	%XMM5,%XMM8,%XMM8

  (1321) 0x467c27 VCMPSD	$0x1,%XMM7,%XMM9,%K1

  (1321) 0x467c2e VMOVSD	%XMM8,%XMM5,%XMM5{%K1}

  (1321) 0x467c34 MOV	-0xb0(%RBP),%RDX

  (1321) 0x467c3b MOV	(%RDX,%RAX,1),%RDX

  (1321) 0x467c3f XOR	%R11D,%R11D

  (1321) 0x467c42 CMP	%RDI,(%RBX,%RDX,8)

  (1321) 0x467c46 SETGE	%R11B

  (1321) 0x467c4a XOR	%R15D,%R15D

  (1321) 0x467c4d CMP	%R13,%RDX

  (1321) 0x467c50 SETE	%R15B

  (1321) 0x467c54 CMP	%R11B,%R15B

  (1321) 0x467c57 CMOVA	%R15D,%R11D

  (1321) 0x467c5b CMP	$0x1,%R11B

  (1321) 0x467c5f JNE	467b40

  (1321) 0x467c65 MOV	-0x48(%RBP),%RDX

  (1321) 0x467c69 VMOVSD	(%RDX,%RAX,1),%XMM8

  (1321) 0x467c6e VMULSD	%XMM6,%XMM8,%XMM9

  (1321) 0x467c72 VADDSD	%XMM5,%XMM8,%XMM8

  (1321) 0x467c76 VCMPSD	$0x1,%XMM7,%XMM9,%K1

  (1321) 0x467c7d VMOVSD	%XMM8,%XMM5,%XMM5{%K1}

  (1321) 0x467c83 JMP	467b40

0x467cc0 SHR	$0x2,%R15

0x467cc4 LEA	0x18(,%RAX,8),%RDX

0x467ccc JMP	467d0d

  (1319) 0x467d00 ADD	$0x20,%RDX

  (1319) 0x467d04 DEC	%R15

  (1319) 0x467d07 JE	467995

  (1319) 0x467d0d MOV	-0x88(%RBP),%R11

  (1319) 0x467d14 MOV	-0x18(%R11,%RDX,1),%R11

  (1319) 0x467d19 CMP	%RSI,(%R14,%R11,8)

  (1319) 0x467d1d JGE	467d80

  (1319) 0x467d1f MOV	-0x88(%RBP),%R11

  (1319) 0x467d26 MOV	-0x10(%R11,%RDX,1),%R11

  (1319) 0x467d2b CMP	%RSI,(%R14,%R11,8)

  (1319) 0x467d2f JGE	467db6

  (1319) 0x467d35 MOV	-0x88(%RBP),%R11

  (1319) 0x467d3c MOV	-0x8(%R11,%RDX,1),%R11

  (1319) 0x467d41 CMP	%RSI,(%R14,%R11,8)

  (1319) 0x467d45 JGE	467dec

  (1319) 0x467d4b MOV	-0x88(%RBP),%R11

  (1319) 0x467d52 MOV	(%R11,%RDX,1),%R11

  (1319) 0x467d56 CMP	%RSI,(%R14,%R11,8)

  (1319) 0x467d5a JL	467d00

  (1319) 0x467d5c JMP	467e21

  (1319) 0x467d80 MOV	-0x50(%RBP),%R11

  (1319) 0x467d84 VMOVSD	-0x18(%R11,%RDX,1),%XMM7

  (1319) 0x467d8b VMULSD	%XMM6,%XMM7,%XMM8

  (1319) 0x467d8f VADDSD	%XMM5,%XMM7,%XMM7

  (1319) 0x467d93 VCMPSD	$0x1,%XMM0,%XMM8,%K1

  (1319) 0x467d9a VMOVSD	%XMM7,%XMM5,%XMM5{%K1}

  (1319) 0x467da0 MOV	-0x88(%RBP),%R11

  (1319) 0x467da7 MOV	-0x10(%R11,%RDX,1),%R11

  (1319) 0x467dac CMP	%RSI,(%R14,%R11,8)

  (1319) 0x467db0 JL	467d35

  (1319) 0x467db6 MOV	-0x50(%RBP),%R11

  (1319) 0x467dba VMOVSD	-0x10(%R11,%RDX,1),%XMM7

  (1319) 0x467dc1 VMULSD	%XMM6,%XMM7,%XMM8

  (1319) 0x467dc5 VADDSD	%XMM5,%XMM7,%XMM7

  (1319) 0x467dc9 VCMPSD	$0x1,%XMM0,%XMM8,%K1

  (1319) 0x467dd0 VMOVSD	%XMM7,%XMM5,%XMM5{%K1}

  (1319) 0x467dd6 MOV	-0x88(%RBP),%R11

  (1319) 0x467ddd MOV	-0x8(%R11,%RDX,1),%R11

  (1319) 0x467de2 CMP	%RSI,(%R14,%R11,8)

  (1319) 0x467de6 JL	467d4b

  (1319) 0x467dec MOV	-0x50(%RBP),%R11

  (1319) 0x467df0 VMOVSD	-0x8(%R11,%RDX,1),%XMM7

  (1319) 0x467df7 VMULSD	%XMM6,%XMM7,%XMM8

  (1319) 0x467dfb VADDSD	%XMM5,%XMM7,%XMM7

  (1319) 0x467dff VCMPSD	$0x1,%XMM0,%XMM8,%K1

  (1319) 0x467e06 VMOVSD	%XMM7,%XMM5,%XMM5{%K1}

  (1319) 0x467e0c MOV	-0x88(%RBP),%R11

  (1319) 0x467e13 MOV	(%R11,%RDX,1),%R11

  (1319) 0x467e17 CMP	%RSI,(%R14,%R11,8)

  (1319) 0x467e1b JL	467d00

  (1319) 0x467e21 MOV	-0x50(%RBP),%R11

  (1319) 0x467e25 VMOVSD	(%R11,%RDX,1),%XMM7

  (1319) 0x467e2b VMULSD	%XMM6,%XMM7,%XMM8

  (1319) 0x467e2f VADDSD	%XMM5,%XMM7,%XMM7

  (1319) 0x467e33 VCMPSD	$0x1,%XMM0,%XMM8,%K1

  (1319) 0x467e3a VMOVSD	%XMM7,%XMM5,%XMM5{%K1}

  (1319) 0x467e40 JMP	467d00

0x467e80 MOV	-0x68(%RBP),%RDX

0x467e84 LEA	0x2(%RDX),%R10

0x467e88 LEA	-0x2(%RCX),%RAX

0x467e8c CMP	%RDX,%RAX

0x467e8f JNE	467f09

0x467e91 CMPQ	$0x2,-0xd0(%RBP)

0x467e99 JL	46779b

0x467e9f MOV	-0x150(%RBP),%RCX

0x467ea6 MOV	-0xa8(%RBP),%RDX

0x467ead MOV	(%RCX,%RDX,8),%RAX

0x467eb1 MOV	0x8(%RCX,%RDX,8),%RCX

0x467eb6 MOV	%RCX,%R10

0x467eb9 SUB	%RAX,%R10

0x467ebc JLE	46779b

0x467ec2 VCVTSI2SDQ	-0x70(%RBP),%XMM10,%XMM6

0x467ec8 CMP	$0x4,%R10

0x467ecc JAE	468080

0x467ed2 MOV	%R10,%RDX

0x467ed5 AND	$-0x4,%RDX

0x467ed9 CMP	%R10,%RDX

0x467edc JAE	468200

0x467ee2 ADD	%RDX,%RAX

0x467ee5 MOV	-0x40(%RBP),%R12

0x467ee9 JMP	46800c

  (1317) 0x467f00 ADD	$0x2,%R10

  (1317) 0x467f04 CMP	%R10,%RCX

  (1317) 0x467f07 JE	467e91

  (1317) 0x467f09 MOV	-0xb0(%RBP),%RAX

  (1317) 0x467f10 MOV	(%RAX,%R10,8),%RAX

  (1317) 0x467f14 MOV	(%RBX,%RAX,8),%RDX

  (1317) 0x467f18 CMP	%RDI,%RDX

  (1317) 0x467f1b JL	467f44

  (1317) 0x467f1d MOV	-0x48(%RBP),%R11

  (1317) 0x467f21 VMOVSD	(%R11,%R10,8),%XMM7

  (1317) 0x467f27 VMULSD	%XMM6,%XMM7,%XMM8

  (1317) 0x467f2b VUCOMISD	%XMM0,%XMM8

  (1317) 0x467f2f JAE	467f44

  (1317) 0x467f31 MOV	-0x80(%RBP),%R11

  (1317) 0x467f35 MOV	(%R11),%R15

  (1317) 0x467f38 VFMADD213SD	(%R15,%RDX,8),%XMM5,%XMM7

  (1317) 0x467f3e VMOVSD	%XMM7,(%R15,%RDX,8)

  (1317) 0x467f44 CMP	%R13,%RAX

  (1317) 0x467f47 JNE	467f69

  (1317) 0x467f49 MOV	-0x48(%RBP),%RAX

  (1317) 0x467f4d VMOVSD	(%RAX,%R10,8),%XMM7

  (1317) 0x467f53 VMULSD	%XMM6,%XMM7,%XMM8

  (1317) 0x467f57 VFMADD213SD	%XMM4,%XMM5,%XMM7

  (1317) 0x467f5c VCMPSD	$0x1,%XMM0,%XMM8,%K1

  (1317) 0x467f63 VMOVSD	%XMM7,%XMM4,%XMM4{%K1}

  (1317) 0x467f69 MOV	-0xb0(%RBP),%RAX

  (1317) 0x467f70 MOV	0x8(%RAX,%R10,8),%RAX

  (1317) 0x467f75 MOV	(%RBX,%RAX,8),%RDX

  (1317) 0x467f79 CMP	%RDI,%RDX

  (1317) 0x467f7c JL	467fa6

  (1317) 0x467f7e MOV	-0x48(%RBP),%R11

  (1317) 0x467f82 VMOVSD	0x8(%R11,%R10,8),%XMM7

  (1317) 0x467f89 VMULSD	%XMM6,%XMM7,%XMM8

  (1317) 0x467f8d VUCOMISD	%XMM0,%XMM8

  (1317) 0x467f91 JAE	467fa6

  (1317) 0x467f93 MOV	-0x80(%RBP),%R11

  (1317) 0x467f97 MOV	(%R11),%R15

  (1317) 0x467f9a VFMADD213SD	(%R15,%RDX,8),%XMM5,%XMM7

  (1317) 0x467fa0 VMOVSD	%XMM7,(%R15,%RDX,8)

  (1317) 0x467fa6 CMP	%R13,%RAX

  (1317) 0x467fa9 JNE	467f00

  (1317) 0x467faf MOV	-0x48(%RBP),%RAX

  (1317) 0x467fb3 VMOVSD	0x8(%RAX,%R10,8),%XMM7

  (1317) 0x467fba VMULSD	%XMM6,%XMM7,%XMM8

  (1317) 0x467fbe VFMADD213SD	%XMM4,%XMM5,%XMM7

  (1317) 0x467fc3 VCMPSD	$0x1,%XMM0,%XMM8,%K1

  (1317) 0x467fca VMOVSD	%XMM7,%XMM4,%XMM4{%K1}

  (1317) 0x467fd0 JMP	467f00

  (1315) 0x468000 INC	%RAX

  (1315) 0x468003 CMP	%RAX,%RCX

  (1315) 0x468006 JE	46779b

  (1315) 0x46800c MOV	-0x88(%RBP),%RDX

  (1315) 0x468013 MOV	(%RDX,%RAX,8),%RDX

  (1315) 0x468017 MOV	(%R14,%RDX,8),%RDX

  (1315) 0x46801b CMP	%RSI,%RDX

  (1315) 0x46801e JL	468000

  (1315) 0x468020 MOV	-0x50(%RBP),%R10

  (1315) 0x468024 VMOVSD	(%R10,%RAX,8),%XMM7

  (1315) 0x46802a VMULSD	%XMM6,%XMM7,%XMM8

  (1315) 0x46802e VUCOMISD	%XMM0,%XMM8

  (1315) 0x468032 JAE	468000

  (1315) 0x468034 MOV	-0x60(%RBP),%R10

  (1315) 0x468038 MOV	(%R10),%R10

  (1315) 0x46803b VFMADD213SD	(%R10,%RDX,8),%XMM5,%XMM7

  (1315) 0x468041 VMOVSD	%XMM7,(%R10,%RDX,8)

  (1315) 0x468047 JMP	468000

0x468080 MOV	%R10,%RDX

0x468083 SHR	$0x2,%RDX

0x468087 LEA	0x18(,%RAX,8),%R11

0x46808f JMP	4680cd

  (1316) 0x4680c0 ADD	$0x20,%R11

  (1316) 0x4680c4 DEC	%RDX

  (1316) 0x4680c7 JE	467ed2

  (1316) 0x4680cd MOV	-0x88(%RBP),%R15

  (1316) 0x4680d4 MOV	-0x18(%R15,%R11,1),%R15

  (1316) 0x4680d9 MOV	(%R14,%R15,8),%R15

  (1316) 0x4680dd CMP	%RSI,%R15

  (1316) 0x4680e0 JL	46810b

  (1316) 0x4680e2 MOV	-0x50(%RBP),%R12

  (1316) 0x4680e6 VMOVSD	-0x18(%R12,%R11,1),%XMM7

  (1316) 0x4680ed VMULSD	%XMM6,%XMM7,%XMM8

  (1316) 0x4680f1 VUCOMISD	%XMM0,%XMM8

  (1316) 0x4680f5 JAE	46810b

  (1316) 0x4680f7 MOV	-0x60(%RBP),%R12

  (1316) 0x4680fb MOV	(%R12),%R12

  (1316) 0x4680ff VFMADD213SD	(%R12,%R15,8),%XMM5,%XMM7

  (1316) 0x468105 VMOVSD	%XMM7,(%R12,%R15,8)

  (1316) 0x46810b MOV	-0x88(%RBP),%R15

  (1316) 0x468112 MOV	-0x10(%R15,%R11,1),%R15

  (1316) 0x468117 MOV	(%R14,%R15,8),%R15

  (1316) 0x46811b CMP	%RSI,%R15

  (1316) 0x46811e JL	468149

  (1316) 0x468120 MOV	-0x50(%RBP),%R12

  (1316) 0x468124 VMOVSD	-0x10(%R12,%R11,1),%XMM7

  (1316) 0x46812b VMULSD	%XMM6,%XMM7,%XMM8

  (1316) 0x46812f VUCOMISD	%XMM0,%XMM8

  (1316) 0x468133 JAE	468149

  (1316) 0x468135 MOV	-0x60(%RBP),%R12

  (1316) 0x468139 MOV	(%R12),%R12

  (1316) 0x46813d VFMADD213SD	(%R12,%R15,8),%XMM5,%XMM7

  (1316) 0x468143 VMOVSD	%XMM7,(%R12,%R15,8)

  (1316) 0x468149 MOV	-0x88(%RBP),%R15

  (1316) 0x468150 MOV	-0x8(%R15,%R11,1),%R15

  (1316) 0x468155 MOV	(%R14,%R15,8),%R15

  (1316) 0x468159 CMP	%RSI,%R15

  (1316) 0x46815c JL	468187

  (1316) 0x46815e MOV	-0x50(%RBP),%R12

  (1316) 0x468162 VMOVSD	-0x8(%R12,%R11,1),%XMM7

  (1316) 0x468169 VMULSD	%XMM6,%XMM7,%XMM8

  (1316) 0x46816d VUCOMISD	%XMM0,%XMM8

  (1316) 0x468171 JAE	468187

  (1316) 0x468173 MOV	-0x60(%RBP),%R12

  (1316) 0x468177 MOV	(%R12),%R12

  (1316) 0x46817b VFMADD213SD	(%R12,%R15,8),%XMM5,%XMM7

  (1316) 0x468181 VMOVSD	%XMM7,(%R12,%R15,8)

  (1316) 0x468187 MOV	-0x88(%RBP),%R15

  (1316) 0x46818e MOV	(%R15,%R11,1),%R15

  (1316) 0x468192 MOV	(%R14,%R15,8),%R15

  (1316) 0x468196 CMP	%RSI,%R15

  (1316) 0x468199 JL	4680c0

  (1316) 0x46819f MOV	-0x50(%RBP),%R12

  (1316) 0x4681a3 VMOVSD	(%R12,%R11,1),%XMM7

  (1316) 0x4681a9 VMULSD	%XMM6,%XMM7,%XMM8

  (1316) 0x4681ad VUCOMISD	%XMM0,%XMM8

  (1316) 0x4681b1 JAE	4680c0

  (1316) 0x4681b7 MOV	-0x60(%RBP),%R12

  (1316) 0x4681bb MOV	(%R12),%R12

  (1316) 0x4681bf VFMADD213SD	(%R12,%R15,8),%XMM5,%XMM7

  (1316) 0x4681c5 VMOVSD	%XMM7,(%R12,%R15,8)

  (1316) 0x4681cb JMP	4680c0

0x468200 MOV	-0x40(%RBP),%R12

0x468204 JMP	46779b

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1221 - 1675

--------------------------------------------------------------------------------

1221:        if (n_fine)

[...]

1609:            for (jj = A_diag_i[i]+1; jj < A_diag_i[i+1]; jj++)

1610:            { /* i1 is a c-point and strongly influences i, accumulate

1611:               * a_(i,i1) into interpolation weight */

1612:              i1 = A_diag_j[jj];

1613:              if (P_marker[i1] >= jj_begin_row)

1614:              {

1615:                P_diag_data[P_marker[i1]] += A_diag_data[jj];

1616:              }

1617:              else if(P_marker[i1] == strong_f_marker)

1618:              {

1619:                sum = zero;

1620:                sgn = 1;

1621:                if(A_diag_data[A_diag_i[i1]] < 0) sgn = -1;

1622:                /* Loop over row of A for point i1 and calculate the sum

1623:                 * of the connections to c-points that strongly influence i. */

1624:                for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1625:                {

1626:                  i2 = A_diag_j[jj1];

1627:                  if((P_marker[i2] >= jj_begin_row || i2 == i) && (sgn*A_diag_data[jj1]) < 0)

1628:                    sum += A_diag_data[jj1];

1629:                }

1630:                if(num_procs > 1)

1631:                {

1632:                  for(jj1 = A_offd_i[i1]; jj1< A_offd_i[i1+1]; jj1++)

1633:                  {

1634:                    i2 = A_offd_j[jj1];

1635:                    if(P_marker_offd[i2] >= jj_begin_row_offd &&

1636:                       (sgn*A_offd_data[jj1]) < 0)

1637:                       sum += A_offd_data[jj1];

1638:                  }

1639:                }

1640:                if(sum != 0)

1641:                {

1642:                  distribute = A_diag_data[jj]/sum;

1643:                  /* Loop over row of A for point i1 and do the distribution */

1644:                  for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1645:                  {

1646:                    i2 = A_diag_j[jj1];

1647:                    if(P_marker[i2] >= jj_begin_row && (sgn*A_diag_data[jj1]) < 0)

1648:                       P_diag_data[P_marker[i2]] +=

1649:                       distribute*A_diag_data[jj1];

1650:                        if(i2 == i && (sgn*A_diag_data[jj1]) < 0)

1651:                          diagonal += distribute*A_diag_data[jj1];

1652:                  }

1653:                  if(num_procs > 1)

1654:                  {

1655:                    for(jj1 = A_offd_i[i1]; jj1 < A_offd_i[i1+1]; jj1++)

1656:                    {

1657:                      i2 = A_offd_j[jj1];

1658:                      if(P_marker_offd[i2] >= jj_begin_row_offd &&

1659:                                 (sgn*A_offd_data[jj1]) < 0)

1660:                        P_offd_data[P_marker_offd[i2]] +=

[...]

1667:                  diagonal += A_diag_data[jj];

1668:                }

1669:              }

1670:              /* neighbor i1 weakly influences i, accumulate a_(i,i1) into

1671:               * diagonal */

1672:              else if (CF_marker[i1] != -3)

1673:              {

1674:                if(num_functions == 1 || dof_func[i] == dof_func[i1])

1675:                  diagonal += A_diag_data[jj];

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.83
CQA speedup if FP arith vectorized	2.55
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildExtPIInterp.extracted
Source	par_lr_interp.c:1221-1221,par_lr_interp.c:1609-1609,par_lr_interp.c:1612-1617,par_lr_interp.c:1621-1621,par_lr_interp.c:1624-1624,par_lr_interp.c:1627-1627,par_lr_interp.c:1630-1632,par_lr_interp.c:1635-1636,par_lr_interp.c:1640-1650,par_lr_interp.c:1653-1655,par_lr_interp.c:1659-1660,par_lr_interp.c:1667-1667,par_lr_interp.c:1672-1675
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.00
CQA cycles if no scalar integer	15.33
CQA cycles if FP arith vectorized	10.99
CQA cycles if fully vectorized	3.50
Front-end cycles	28.00
P0 cycles	16.50
P1 cycles	15.20
P2 cycles	20.67
P3 cycles	20.67
P4 cycles	4.00
P5 cycles	15.40
P6 cycles	16.50
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	15.40
P11 cycles	20.67
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	162.00
Nb uops	164.00
Nb loads	62.00
Nb stores	8.00
Nb stack references	16.00
FLOP/cycle	0.36
Nb FLOP add-sub	3.00
Nb FLOP mul	2.00
Nb FLOP fma	2.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.00
Bytes prefetched	0.00
Bytes loaded	496.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	3.33
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	6.06
Vector-efficiency ratio all	12.92
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	13.26

Metric	Value
CQA speedup if no scalar integer	1.83
CQA speedup if FP arith vectorized	2.55
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildExtPIInterp.extracted
Source	par_lr_interp.c:1221-1221,par_lr_interp.c:1609-1609,par_lr_interp.c:1612-1617,par_lr_interp.c:1621-1621,par_lr_interp.c:1624-1624,par_lr_interp.c:1627-1627,par_lr_interp.c:1630-1632,par_lr_interp.c:1635-1636,par_lr_interp.c:1640-1650,par_lr_interp.c:1653-1655,par_lr_interp.c:1659-1660,par_lr_interp.c:1667-1667,par_lr_interp.c:1672-1675
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.00
CQA cycles if no scalar integer	15.33
CQA cycles if FP arith vectorized	10.99
CQA cycles if fully vectorized	3.50
Front-end cycles	28.00
P0 cycles	16.50
P1 cycles	15.20
P2 cycles	20.67
P3 cycles	20.67
P4 cycles	4.00
P5 cycles	15.40
P6 cycles	16.50
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	15.40
P11 cycles	20.67
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	162.00
Nb uops	164.00
Nb loads	62.00
Nb stores	8.00
Nb stack references	16.00
FLOP/cycle	0.36
Nb FLOP add-sub	3.00
Nb FLOP mul	2.00
Nb FLOP fma	2.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.00
Bytes prefetched	0.00
Bytes loaded	496.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	3.33
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	6.06
Vector-efficiency ratio all	12.92
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	13.26

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildExtPIInterp.extracted
Source file and lines	par_lr_interp.c:1221-1675
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1221,1609-1660,1667-1675.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1221,1609,1612-1617,1621,1624,1627,1630-1632,1635-1636,1640-1650,1653-1655,1659-1660,1667,1672-1675.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 28.00 to 15.33 cycles (1.83x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 28.00 to 3.50 cycles (8.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 2 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

SETBE: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1621
VUCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1621

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSI2SD (INT32/64 to FP64, scalar): 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1627
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1636
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1647
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1659

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

12 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 10 FP arithmetical operations:

5: addition or subtraction (2 inside FMA instructions)
4: multiply (2 inside FMA instructions)
1: divide

The binary loop is loading 496 bytes (62 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	162
nb uops	164
loop length	744
used x86 registers	12
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	16
ADD-SUB / MUL ratio	1.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	28.00 cycles
front end	28.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	16.50	15.20	20.67	20.67	4.00	15.40	16.50	4.00	4.00	4.00	15.40	20.67
cycles	16.50	15.20	20.67	20.67	4.00	15.40	16.50	4.00	4.00	4.00	15.40	20.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	28.00
Dispatch	20.67
DIV/SQRT	4.00
Overall L1	28.00

Vectorization ratios

INT

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	3%

all	5%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	16%

INT+FP

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	6%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	13%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	14%

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	13%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.00 cycles. At this rate:

9% of peak load performance is reached (17.71 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.29 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 28.00 to 20.67 cycles (1.35x speedup).

ASM code

In the binary file, the address of the loop is: 4677ab

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x80(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RCX,%RAX,8),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VADDSD (%RDX,%R9,8),%XMM5,%XMM5	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM5,(%RCX,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP -0x98(%RBP),%R9	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 4676ad <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1b4d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R9,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX,%R10,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 467780 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1c20>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R12,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 467900 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1da0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x180(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%R10,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VPXOR %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%RDX,%R11,8),%XMM5	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
MOV %R10,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x8(%RCX,%R10,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SETBE %AL	2	1	0	0	0	0	0	1	0	0	0	0	0	1-2	1	N/A
LEA -0x1(%RAX,%RAX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%R11),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RCX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R11,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JGE 467940 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1de0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VCVTSI2SDQ -0x70(%RBP),%XMM10,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	7	0.50	scal (12.5%)
NOT %R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R11,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP $0x4,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 467b00 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1fa0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xd0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 467940 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1de0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x68(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%RDX,%RAX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
JMP 46788c <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1d2c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0xe0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $-0x3,(%RAX,%R10,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46779b <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1c3b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPQ $0x1,-0x178(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 467931 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1dd1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x170(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%R13,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP (%RCX,%R10,8),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JNE 46779b <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1c3b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VADDSD (%RAX,%R9,8),%XMM4,%XMM4	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
JMP 46779b <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1c3b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0xb8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP $0x2,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 467a00 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1ea0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x150(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xa8(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%R11,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RDX,%R11,8),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R12,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RAX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 467a00 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1ea0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VCVTSI2SDQ -0x70(%RBP),%XMM10,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	7	0.50	scal (12.5%)
CMP $0x4,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R15,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JAE 467cc0 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x2160>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xe8(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %R11,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 467a00 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1ea0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 4679c8 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1e68>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
VUCOMISD %XMM0,%XMM5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RAX,%R9,8),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JE 467ac0 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1f60>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VDIVSD %XMM5,%XMM6,%XMM5	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
CMP %RCX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x40(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JGE 467e91 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x2331>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VCVTSI2SDQ -0x70(%RBP),%XMM10,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	7	0.50	scal (12.5%)
MOV -0x68(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOT %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
TEST $0x1,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 467e88 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x2328>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX,%RDX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 467a7e <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1f1e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x48(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x8(%R10,%R11,8),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM6,%XMM7,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VUCOMISD %XMM0,%XMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JAE 467a7e <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1f1e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x80(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R10),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VFMADD213SD (%R10,%RDX,8),%XMM5,%XMM7	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM7,(%R10,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %R13,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 467e80 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x2320>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x8(%RAX,%RDX,8),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM6,%XMM7,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM4,%XMM5,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCMPSD $0x1,%XMM0,%XMM8,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM7,%XMM4,%XMM4{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
JMP 467e84 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x2324>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VADDSD %XMM4,%XMM6,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
MOV -0x40(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 46779b <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1c3b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0xd0(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
SHR $0x2,%R12	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV -0x68(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x20(,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 467b4d <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1fed>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
SHR $0x2,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
LEA 0x18(,%RAX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 467d0d <hypre_BoomerAMGBuildExtPIInterp.extracted+0x21ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0x68(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x2(%RDX),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2(%RCX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 467f09 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x23a9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPQ $0x2,-0xd0(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JL 46779b <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1c3b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x150(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xa8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RDX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RCX,%RDX,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JLE 46779b <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1c3b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VCVTSI2SDQ -0x70(%RBP),%XMM10,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	7	0.50	scal (12.5%)
CMP $0x4,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 468080 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x2520>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %R10,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 468200 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x26a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x40(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 46800c <hypre_BoomerAMGBuildExtPIInterp.extracted+0x24ac>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %R10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x2,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA 0x18(,%RAX,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4680cd <hypre_BoomerAMGBuildExtPIInterp.extracted+0x256d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0x40(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 46779b <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1c3b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	hypre_BoomerAMGBuildExtPIInterp.extracted
Source file and lines	par_lr_interp.c:1221-1675
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 2 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

SETBE: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1621
VUCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1621

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSI2SD (INT32/64 to FP64, scalar): 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1627
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1636
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1647
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1659

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

12 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 10 FP arithmetical operations:

5: addition or subtraction (2 inside FMA instructions)
4: multiply (2 inside FMA instructions)
1: divide

The binary loop is loading 496 bytes (62 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	162
nb uops	164
loop length	744
used x86 registers	12
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	16
ADD-SUB / MUL ratio	1.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	28.00 cycles
front end	28.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	16.50	15.20	20.67	20.67	4.00	15.40	16.50	4.00	4.00	4.00	15.40	20.67
cycles	16.50	15.20	20.67	20.67	4.00	15.40	16.50	4.00	4.00	4.00	15.40	20.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	28.00
Dispatch	20.67
DIV/SQRT	4.00
Overall L1	28.00

Vectorization ratios

INT

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	3%

all	5%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	16%

INT+FP

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	6%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	13%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	14%

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	13%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.00 cycles. At this rate:

9% of peak load performance is reached (17.71 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.29 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4677ab

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x80(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RCX,%RAX,8),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VADDSD (%RDX,%R9,8),%XMM5,%XMM5	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM5,(%RCX,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP -0x98(%RBP),%R9	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 4676ad <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1b4d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R9,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX,%R10,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 467780 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1c20>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R12,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 467900 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1da0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x180(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%R10,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VPXOR %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VUCOMISD (%RDX,%R11,8),%XMM5	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
MOV %R10,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x8(%RCX,%R10,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SETBE %AL	2	1	0	0	0	0	0	1	0	0	0	0	0	1-2	1	N/A
LEA -0x1(%RAX,%RAX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%R11),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RCX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R11,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JGE 467940 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1de0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VCVTSI2SDQ -0x70(%RBP),%XMM10,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	7	0.50	scal (12.5%)
NOT %R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R11,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP $0x4,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 467b00 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1fa0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xd0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 467940 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1de0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x68(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%RDX,%RAX,1),%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
JMP 46788c <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1d2c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0xe0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $-0x3,(%RAX,%R10,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46779b <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1c3b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPQ $0x1,-0x178(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 467931 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1dd1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x170(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%R13,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP (%RCX,%R10,8),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JNE 46779b <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1c3b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VADDSD (%RAX,%R9,8),%XMM4,%XMM4	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
JMP 46779b <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1c3b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0xb8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP $0x2,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 467a00 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1ea0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x150(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xa8(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%R11,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RDX,%R11,8),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R12,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RAX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 467a00 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1ea0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VCVTSI2SDQ -0x70(%RBP),%XMM10,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	7	0.50	scal (12.5%)
CMP $0x4,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R15,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JAE 467cc0 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x2160>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xe8(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %R11,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 467a00 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1ea0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 4679c8 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1e68>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
VUCOMISD %XMM0,%XMM5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RAX,%R9,8),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JE 467ac0 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1f60>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VDIVSD %XMM5,%XMM6,%XMM5	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
CMP %RCX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x40(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JGE 467e91 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x2331>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VCVTSI2SDQ -0x70(%RBP),%XMM10,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	7	0.50	scal (12.5%)
MOV -0x68(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOT %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
TEST $0x1,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 467e88 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x2328>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX,%RDX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 467a7e <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1f1e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x48(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x8(%R10,%R11,8),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM6,%XMM7,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VUCOMISD %XMM0,%XMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JAE 467a7e <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1f1e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x80(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R10),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VFMADD213SD (%R10,%RDX,8),%XMM5,%XMM7	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM7,(%R10,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %R13,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 467e80 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x2320>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x8(%RAX,%RDX,8),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM6,%XMM7,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM4,%XMM5,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCMPSD $0x1,%XMM0,%XMM8,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD %XMM7,%XMM4,%XMM4{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
JMP 467e84 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x2324>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VADDSD %XMM4,%XMM6,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
MOV -0x40(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 46779b <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1c3b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0xd0(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
SHR $0x2,%R12	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV -0x68(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x20(,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 467b4d <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1fed>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
SHR $0x2,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
LEA 0x18(,%RAX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 467d0d <hypre_BoomerAMGBuildExtPIInterp.extracted+0x21ad>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0x68(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x2(%RDX),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2(%RCX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 467f09 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x23a9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPQ $0x2,-0xd0(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JL 46779b <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1c3b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x150(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xa8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RDX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RCX,%RDX,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JLE 46779b <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1c3b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VCVTSI2SDQ -0x70(%RBP),%XMM10,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	7	0.50	scal (12.5%)
CMP $0x4,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 468080 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x2520>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %R10,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 468200 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x26a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x40(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 46800c <hypre_BoomerAMGBuildExtPIInterp.extracted+0x24ac>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %R10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x2,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA 0x18(,%RAX,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4680cd <hypre_BoomerAMGBuildExtPIInterp.extracted+0x256d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0x40(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 46779b <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1c3b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

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Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code