OV - exec - Loop 1007

0x451f40 MOV	-0xd0(%RBP),%RSI

0x451f47 INC	%RSI

0x451f4a CMP	-0xc8(%RBP),%RSI

0x451f51 JGE	4525c4

0x451f57 MOV	-0x88(%RBP),%RDX

0x451f5e MOV	%RSI,-0xd0(%RBP)

0x451f65 MOV	(%RDX,%RSI,8),%RDI

0x451f69 MOV	-0x90(%RBP),%RDX

0x451f70 MOV	%RAX,(%RDX,%RDI,8)

0x451f74 MOV	-0x98(%RBP),%RDX

0x451f7b MOV	%RCX,(%RDX,%RDI,8)

0x451f7f MOV	-0xa8(%RBP),%RDX

0x451f86 MOV	(%RDX,%RDI,8),%R8

0x451f8a JMP	451fce

  (1010) 0x451fc0 MOV	-0x38(%RBP),%R10

  (1010) 0x451fc4 INC	%R8

  (1010) 0x451fc7 MOV	-0xa8(%RBP),%RDX

  (1010) 0x451fce CMP	0x8(%RDX,%RDI,8),%R8

  (1010) 0x451fd3 JGE	452380

  (1010) 0x451fd9 MOV	-0x128(%RBP),%RDX

  (1010) 0x451fe0 MOV	(%RDX,%R8,8),%R9

  (1010) 0x451fe4 MOV	-0x118(%RBP),%RDX

  (1010) 0x451feb CMP	%R10,(%RDX,%R9,8)

  (1010) 0x451fef JNE	451fc4

  (1010) 0x451ff1 MOV	-0x58(%RBP),%RDX

  (1010) 0x451ff5 MOV	0x8(%RDX,%R9,8),%RSI

  (1010) 0x451ffa TEST	%RSI,%RSI

  (1010) 0x451ffd JLE	4520c0

  (1010) 0x452003 MOV	-0x90(%RBP),%RDX

  (1010) 0x45200a MOV	(%RDX,%R9,8),%R10

  (1010) 0x45200e ADD	%R10,%RSI

  (1010) 0x452011 MOV	-0x40(%RBP),%RDX

  (1010) 0x452015 MOV	-0x8(%RDX,%R12,8),%R11

  (1010) 0x45201a LEA	0x1(%R10),%RDX

  (1010) 0x45201e CMP	%RDX,%RSI

  (1010) 0x452021 CMOVLE	%RDX,%RSI

  (1010) 0x452025 MOV	%RSI,%RDX

  (1010) 0x452028 SUB	%R10,%RDX

  (1010) 0x45202b CMP	$0x4,%RDX

  (1010) 0x45202f MOV	%RDX,-0x30(%RBP)

  (1010) 0x452033 JAE	452180

  (1010) 0x452039 MOV	-0x30(%RBP),%R14

  (1010) 0x45203d MOV	%R14,%RDX

  (1010) 0x452040 AND	$-0x4,%RDX

  (1010) 0x452044 CMP	%R14,%RDX

  (1010) 0x452047 JAE	4520c0

  (1010) 0x45204d ADD	%RDX,%R10

  (1010) 0x452050 JMP	452088

    (1013) 0x452080 INC	%R10

    (1013) 0x452083 CMP	%R10,%RSI

    (1013) 0x452086 JE	4520c0

    (1013) 0x452088 MOV	(%R11,%R10,8),%RDX

    (1013) 0x45208c CMP	%RDI,(%RBX,%RDX,8)

    (1013) 0x452090 JE	452080

    (1013) 0x452092 INC	%RAX

    (1013) 0x452095 MOV	-0x58(%RBP),%R14

    (1013) 0x452099 INCQ	0x8(%R14,%RDI,8)

    (1013) 0x45209e MOV	%RDI,(%RBX,%RDX,8)

    (1013) 0x4520a2 JMP	452080

  (1010) 0x4520c0 MOV	-0x60(%RBP),%RDX

  (1010) 0x4520c4 MOV	0x8(%RDX,%R9,8),%RSI

  (1010) 0x4520c9 TEST	%RSI,%RSI

  (1010) 0x4520cc JLE	451fc0

  (1010) 0x4520d2 MOV	-0x98(%RBP),%RDX

  (1010) 0x4520d9 MOV	(%RDX,%R9,8),%R9

  (1010) 0x4520dd ADD	%R9,%RSI

  (1010) 0x4520e0 MOV	-0x48(%RBP),%RDX

  (1010) 0x4520e4 MOV	-0x8(%RDX,%R12,8),%R10

  (1010) 0x4520e9 LEA	0x1(%R9),%RDX

  (1010) 0x4520ed CMP	%RDX,%RSI

  (1010) 0x4520f0 CMOVLE	%RDX,%RSI

  (1010) 0x4520f4 MOV	%RSI,%R11

  (1010) 0x4520f7 SUB	%R9,%R11

  (1010) 0x4520fa CMP	$0x4,%R11

  (1010) 0x4520fe MOV	%R11,-0x30(%RBP)

  (1010) 0x452102 JAE	452280

  (1010) 0x452108 MOV	-0x30(%RBP),%RDX

  (1010) 0x45210c MOV	%RDX,%R11

  (1010) 0x45210f AND	$-0x4,%R11

  (1010) 0x452113 CMP	%RDX,%R11

  (1010) 0x452116 JAE	451fc0

  (1010) 0x45211c ADD	%R11,%R9

  (1010) 0x45211f JMP	45214c

    (1011) 0x452140 INC	%R9

    (1011) 0x452143 CMP	%R9,%RSI

    (1011) 0x452146 JE	451fc0

    (1011) 0x45214c MOV	(%R10,%R9,8),%RDX

    (1011) 0x452150 CMP	%RDI,(%R15,%RDX,8)

    (1011) 0x452154 JE	452140

    (1011) 0x452156 INC	%RCX

    (1011) 0x452159 MOV	-0x60(%RBP),%R11

    (1011) 0x45215d INCQ	0x8(%R11,%RDI,8)

    (1011) 0x452162 MOV	%RDI,(%R15,%RDX,8)

    (1011) 0x452166 JMP	452140

  (1010) 0x452180 MOV	%RDX,%R14

  (1010) 0x452183 SHR	$0x2,%R14

  (1010) 0x452187 LEA	0x18(%R11,%R10,8),%R13

  (1010) 0x45218c JMP	4521d1

    (1014) 0x4521c0 MOV	-0x50(%RBP),%R12

    (1014) 0x4521c4 ADD	$0x20,%R13

    (1014) 0x4521c8 DEC	%R14

    (1014) 0x4521cb JE	452039

    (1014) 0x4521d1 MOV	-0x18(%R13),%RDX

    (1014) 0x4521d5 CMP	%RDI,(%RBX,%RDX,8)

    (1014) 0x4521d9 JNE	452200

    (1014) 0x4521db MOV	-0x10(%R13),%RDX

    (1014) 0x4521df CMP	%RDI,(%RBX,%RDX,8)

    (1014) 0x4521e3 JNE	45221a

    (1014) 0x4521e5 MOV	-0x8(%R13),%RDX

    (1014) 0x4521e9 CMP	%RDI,(%RBX,%RDX,8)

    (1014) 0x4521ed JNE	452234

    (1014) 0x4521ef MOV	(%R13),%RDX

    (1014) 0x4521f3 CMP	%RDI,(%RBX,%RDX,8)

    (1014) 0x4521f7 JE	4521c0

    (1014) 0x4521f9 JMP	452252

    (1014) 0x452200 INC	%RAX

    (1014) 0x452203 MOV	-0x58(%RBP),%R12

    (1014) 0x452207 INCQ	0x8(%R12,%RDI,8)

    (1014) 0x45220c MOV	%RDI,(%RBX,%RDX,8)

    (1014) 0x452210 MOV	-0x10(%R13),%RDX

    (1014) 0x452214 CMP	%RDI,(%RBX,%RDX,8)

    (1014) 0x452218 JE	4521e5

    (1014) 0x45221a INC	%RAX

    (1014) 0x45221d MOV	-0x58(%RBP),%R12

    (1014) 0x452221 INCQ	0x8(%R12,%RDI,8)

    (1014) 0x452226 MOV	%RDI,(%RBX,%RDX,8)

    (1014) 0x45222a MOV	-0x8(%R13),%RDX

    (1014) 0x45222e CMP	%RDI,(%RBX,%RDX,8)

    (1014) 0x452232 JE	4521ef

    (1014) 0x452234 INC	%RAX

    (1014) 0x452237 MOV	-0x58(%RBP),%R12

    (1014) 0x45223b INCQ	0x8(%R12,%RDI,8)

    (1014) 0x452240 MOV	%RDI,(%RBX,%RDX,8)

    (1014) 0x452244 MOV	(%R13),%RDX

    (1014) 0x452248 CMP	%RDI,(%RBX,%RDX,8)

    (1014) 0x45224c JE	4521c0

    (1014) 0x452252 INC	%RAX

    (1014) 0x452255 MOV	-0x58(%RBP),%R12

    (1014) 0x452259 INCQ	0x8(%R12,%RDI,8)

    (1014) 0x45225e MOV	%RDI,(%RBX,%RDX,8)

    (1014) 0x452262 JMP	4521c0

  (1010) 0x452280 SHR	$0x2,%R11

  (1010) 0x452284 LEA	0x18(%R10,%R9,8),%R14

  (1010) 0x452289 JMP	4522cd

    (1012) 0x4522c0 ADD	$0x20,%R14

    (1012) 0x4522c4 DEC	%R11

    (1012) 0x4522c7 JE	452108

    (1012) 0x4522cd MOV	-0x18(%R14),%R13

    (1012) 0x4522d1 CMP	%RDI,(%R15,%R13,8)

    (1012) 0x4522d5 JNE	452300

    (1012) 0x4522d7 MOV	-0x10(%R14),%R13

    (1012) 0x4522db CMP	%RDI,(%R15,%R13,8)

    (1012) 0x4522df JNE	45231a

    (1012) 0x4522e1 MOV	-0x8(%R14),%R13

    (1012) 0x4522e5 CMP	%RDI,(%R15,%R13,8)

    (1012) 0x4522e9 JNE	452334

    (1012) 0x4522eb MOV	(%R14),%R13

    (1012) 0x4522ee CMP	%RDI,(%R15,%R13,8)

    (1012) 0x4522f2 JE	4522c0

    (1012) 0x4522f4 JMP	452351

    (1012) 0x452300 INC	%RCX

    (1012) 0x452303 MOV	-0x60(%RBP),%RDX

    (1012) 0x452307 INCQ	0x8(%RDX,%RDI,8)

    (1012) 0x45230c MOV	%RDI,(%R15,%R13,8)

    (1012) 0x452310 MOV	-0x10(%R14),%R13

    (1012) 0x452314 CMP	%RDI,(%R15,%R13,8)

    (1012) 0x452318 JE	4522e1

    (1012) 0x45231a INC	%RCX

    (1012) 0x45231d MOV	-0x60(%RBP),%RDX

    (1012) 0x452321 INCQ	0x8(%RDX,%RDI,8)

    (1012) 0x452326 MOV	%RDI,(%R15,%R13,8)

    (1012) 0x45232a MOV	-0x8(%R14),%R13

    (1012) 0x45232e CMP	%RDI,(%R15,%R13,8)

    (1012) 0x452332 JE	4522eb

    (1012) 0x452334 INC	%RCX

    (1012) 0x452337 MOV	-0x60(%RBP),%RDX

    (1012) 0x45233b INCQ	0x8(%RDX,%RDI,8)

    (1012) 0x452340 MOV	%RDI,(%R15,%R13,8)

    (1012) 0x452344 MOV	(%R14),%R13

    (1012) 0x452347 CMP	%RDI,(%R15,%R13,8)

    (1012) 0x45234b JE	4522c0

    (1012) 0x452351 INC	%RCX

    (1012) 0x452354 MOV	-0x60(%RBP),%RDX

    (1012) 0x452358 INCQ	0x8(%RDX,%RDI,8)

    (1012) 0x45235d MOV	%RDI,(%R15,%R13,8)

    (1012) 0x452361 JMP	4522c0

0x452380 MOV	-0xa0(%RBP),%RDX

0x452387 MOV	(%RDX,%RDI,8),%R8

0x45238b MOV	0x8(%RDX,%RDI,8),%RDX

0x452390 CMP	%RDX,%R8

0x452393 JL	4523cc

0x452395 JMP	451f40

  (1008) 0x4523c0 INC	%R8

  (1008) 0x4523c3 CMP	%RDX,%R8

  (1008) 0x4523c6 JGE	451f40

  (1008) 0x4523cc MOV	-0x130(%RBP),%RSI

  (1008) 0x4523d3 MOV	(%RSI,%R8,8),%R9

  (1008) 0x4523d7 MOV	-0x120(%RBP),%RSI

  (1008) 0x4523de CMP	%R10,(%RSI,%R9,8)

  (1008) 0x4523e2 JNE	4523c0

  (1008) 0x4523e4 MOV	-0x110(%RBP),%RSI

  (1008) 0x4523eb MOV	0x8(%RSI,%R9,8),%RSI

  (1008) 0x4523f0 TEST	%RSI,%RSI

  (1008) 0x4523f3 JLE	4523c0

  (1008) 0x4523f5 MOV	-0x100(%RBP),%RDX

  (1008) 0x4523fc MOV	(%RDX,%R9,8),%R9

  (1008) 0x452400 ADD	%R9,%RSI

  (1008) 0x452403 MOV	-0x108(%RBP),%RDX

  (1008) 0x45240a MOV	(%RDX,%R12,8),%R13

  (1008) 0x45240e LEA	0x1(%R9),%R10

  (1008) 0x452412 CMP	%R10,%RSI

  (1008) 0x452415 CMOVLE	%R10,%RSI

  (1008) 0x452419 MOV	%RSI,%R11

  (1008) 0x45241c SUB	%R9,%R11

  (1008) 0x45241f CMP	%R10,%RSI

  (1008) 0x452422 MOV	%R11,-0x30(%RBP)

  (1008) 0x452426 JNE	452480

  (1008) 0x452428 XOR	%ESI,%ESI

  (1008) 0x45242a TESTB	$0x1,-0x30(%RBP)

  (1008) 0x45242e MOV	-0x38(%RBP),%R10

  (1008) 0x452432 JE	45259c

  (1008) 0x452438 ADD	%RSI,%R9

  (1008) 0x45243b MOV	(%R13,%R9,8),%RDX

  (1008) 0x452440 TEST	%RDX,%RDX

  (1008) 0x452443 JS	452580

  (1008) 0x452449 CMP	%RDI,(%R15,%RDX,8)

  (1008) 0x45244d JE	45259c

  (1008) 0x452453 LEA	(%R15,%RDX,8),%RDX

  (1008) 0x452457 INC	%RCX

  (1008) 0x45245a MOV	-0x60(%RBP),%RSI

  (1008) 0x45245e JMP	452594

  (1008) 0x452480 AND	$-0x2,%R11

  (1008) 0x452484 LEA	0x8(%R13,%R9,8),%R10

  (1008) 0x452489 XOR	%ESI,%ESI

  (1008) 0x45248b MOV	%R13,%RDX

  (1008) 0x45248e JMP	4524d8

    (1009) 0x4524c0 INCQ	0x8(%R13,%RDI,8)

    (1009) 0x4524c5 MOV	%RDI,(%R14)

    (1009) 0x4524c8 MOV	%RDX,%R13

    (1009) 0x4524cb ADD	$0x2,%RSI

    (1009) 0x4524cf CMP	%RSI,%R11

    (1009) 0x4524d2 JE	45242a

    (1009) 0x4524d8 MOV	-0x8(%R10,%RSI,8),%R14

    (1009) 0x4524dd TEST	%R14,%R14

    (1009) 0x4524e0 JS	452500

    (1009) 0x4524e2 CMP	%RDI,(%R15,%R14,8)

    (1009) 0x4524e6 JE	45251f

    (1009) 0x4524e8 LEA	(%R15,%R14,8),%R14

    (1009) 0x4524ec INC	%RCX

    (1009) 0x4524ef MOV	-0x60(%RBP),%R13

    (1009) 0x4524f3 JMP	452514

    (1009) 0x452500 NOT	%R14

    (1009) 0x452503 CMP	%RDI,(%RBX,%R14,8)

    (1009) 0x452507 JE	45251f

    (1009) 0x452509 LEA	(%RBX,%R14,8),%R14

    (1009) 0x45250d INC	%RAX

    (1009) 0x452510 MOV	-0x58(%RBP),%R13

    (1009) 0x452514 INCQ	0x8(%R13,%RDI,8)

    (1009) 0x452519 MOV	%RDI,(%R14)

    (1009) 0x45251c MOV	%RDX,%R13

    (1009) 0x45251f MOV	(%R10,%RSI,8),%R14

    (1009) 0x452523 TEST	%R14,%R14

    (1009) 0x452526 JS	452540

    (1009) 0x452528 CMP	%RDI,(%R15,%R14,8)

    (1009) 0x45252c JE	4524cb

    (1009) 0x45252e LEA	(%R15,%R14,8),%R14

    (1009) 0x452532 INC	%RCX

    (1009) 0x452535 MOV	-0x60(%RBP),%R13

    (1009) 0x452539 JMP	4524c0

    (1009) 0x452540 NOT	%R14

    (1009) 0x452543 CMP	%RDI,(%RBX,%R14,8)

    (1009) 0x452547 JE	4524cb

    (1009) 0x452549 LEA	(%RBX,%R14,8),%R14

    (1009) 0x45254d INC	%RAX

    (1009) 0x452550 MOV	-0x58(%RBP),%R13

    (1009) 0x452554 JMP	4524c0

  (1008) 0x452580 NOT	%RDX

  (1008) 0x452583 CMP	%RDI,(%RBX,%RDX,8)

  (1008) 0x452587 JE	45259c

  (1008) 0x452589 LEA	(%RBX,%RDX,8),%RDX

  (1008) 0x45258d INC	%RAX

  (1008) 0x452590 MOV	-0x58(%RBP),%RSI

  (1008) 0x452594 INCQ	0x8(%RSI,%RDI,8)

  (1008) 0x452599 MOV	%RDI,(%RDX)

  (1008) 0x45259c MOV	-0xa0(%RBP),%RDX

  (1008) 0x4525a3 MOV	0x8(%RDX,%RDI,8),%RDX

  (1008) 0x4525a8 INC	%R8

  (1008) 0x4525ab CMP	%RDX,%R8

  (1008) 0x4525ae JL	4523cc

0x4525b4 JMP	451f40

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 917 - 997

--------------------------------------------------------------------------------

917:           for (i=0; i < n_coarse; i++)

[...]

939:           for (i=thread_start; i < thread_stop; i++)

940:           {

941:              i1 = pass_array[i];

942:              P_diag_start[i1] = cnt_nz;

943:              P_offd_start[i1] = cnt_nz_offd;

944:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

945:              {

946:                 j1 = S_diag_j[j];

947:                 if (assigned[j1] == pass-1)

948:                 {

949:                    j_start = P_diag_start[j1];

950:                    j_end = j_start+P_diag_i[j1+1];

951:                    for (k=j_start; k < j_end; k++)

952:                    {

953:                       k1 = P_diag_pass[pass-1][k];

954:                       if (P_marker[k1] != i1)

955:                       {

956:                          cnt_nz++;

957:                          P_diag_i[i1+1]++;

958:                          P_marker[k1] = i1;

959:                       }

960:                    }

961:                    j_start = P_offd_start[j1];

962:                    j_end = j_start+P_offd_i[j1+1];

963:                    for (k=j_start; k < j_end; k++)

964:                    {

965:                       k1 = P_offd_pass[pass-1][k];

966:                       if (P_marker_offd[k1] != i1)

967:                       {

968:                          cnt_nz_offd++;

969:                          P_offd_i[i1+1]++;

970:                          P_marker_offd[k1] = i1;

[...]

976:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

977:              {

978:                 j1 = S_offd_j[j];

979:                 if (assigned_offd[j1] == pass-1)

980:                 {

981:                    j_start = Pext_start[j1];

982:                    j_end = j_start+Pext_i[j1+1];

983:                    for (k=j_start; k < j_end; k++)

984:                    {

985:                       k1 = Pext_pass[pass][k];

986:                       if (k1 < 0)

987:                       {

988:                          if (P_marker[-k1-1] != i1)

989:                          {

990:                             cnt_nz++;

991:                             P_diag_i[i1+1]++;

992:                             P_marker[-k1-1] = i1;

993:                          }

994:                       }

995:                       else if (P_marker_offd[k1] != i1)

996:                       {

997:                          cnt_nz_offd++;

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P2, P3, P11,
Function	hypre_BoomerAMGBuildMultipass.extracted.34
Source	par_multi_interp.c:939-944,par_multi_interp.c:947-947,par_multi_interp.c:970-970,par_multi_interp.c:976-976
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.67
CQA cycles if no scalar integer	3.67
CQA cycles if FP arith vectorized	3.67
CQA cycles if fully vectorized	0.46
Front-end cycles	3.50
P0 cycles	1.00
P1 cycles	0.80
P2 cycles	3.67
P3 cycles	3.67
P4 cycles	1.50
P5 cycles	0.60
P6 cycles	1.00
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	0.60
P11 cycles	3.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	11.00
Nb stores	3.00
Nb stack references	7.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.55
Bytes prefetched	0.00
Bytes loaded	88.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P2, P3, P11,
Function	hypre_BoomerAMGBuildMultipass.extracted.34
Source	par_multi_interp.c:939-944,par_multi_interp.c:947-947,par_multi_interp.c:970-970,par_multi_interp.c:976-976
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.67
CQA cycles if no scalar integer	3.67
CQA cycles if FP arith vectorized	3.67
CQA cycles if fully vectorized	0.46
Front-end cycles	3.50
P0 cycles	1.00
P1 cycles	0.80
P2 cycles	3.67
P3 cycles	3.67
P4 cycles	1.50
P5 cycles	0.60
P6 cycles	1.00
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	0.60
P11 cycles	3.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	11.00
Nb stores	3.00
Nb stack references	7.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.55
Bytes prefetched	0.00
Bytes loaded	88.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass.extracted.34
Source file and lines	par_multi_interp.c:917-997
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:917,939-970,976-997.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-944,947,970,976.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 2793 paths individually, rerun with max-paths=2793
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 2793 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.67 to 0.46 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by reading data from caches/RAM (load units are a bottleneck).

Workaround

Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 88 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	21
nb uops	21
loop length	107
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.00	0.80	3.67	3.67	1.50	0.60	1.00	1.50	1.50	1.50	0.60	3.67
cycles	1.00	0.80	3.67	3.67	1.50	0.60	1.00	1.50	1.50	1.50	0.60	3.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.50
Dispatch	3.67
Overall L1	3.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.67 cycles. At this rate:

12% of peak load performance is reached (24.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.55 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 451f57

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0xd0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP -0xc8(%RBP),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 4525c4 <hypre_BoomerAMGBuildMultipass.extracted.34+0x9a4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x88(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDX,%RSI,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x90(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,(%RDX,%RDI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x98(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,(%RDX,%RDI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xa8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RDI,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 451fce <hypre_BoomerAMGBuildMultipass.extracted.34+0x3ae>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0xa0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RDI,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RDX,%RDI,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JL 4523cc <hypre_BoomerAMGBuildMultipass.extracted.34+0x7ac>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 451f40 <hypre_BoomerAMGBuildMultipass.extracted.34+0x320>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 451f40 <hypre_BoomerAMGBuildMultipass.extracted.34+0x320>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	hypre_BoomerAMGBuildMultipass.extracted.34
Source file and lines	par_multi_interp.c:917-997
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:917,939-970,976-997.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-944,947,970,976.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 2793 paths individually, rerun with max-paths=2793
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 2793 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.67 to 0.46 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by reading data from caches/RAM (load units are a bottleneck).

Workaround

Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 88 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	21
nb uops	21
loop length	107
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.00	0.80	3.67	3.67	1.50	0.60	1.00	1.50	1.50	1.50	0.60	3.67
cycles	1.00	0.80	3.67	3.67	1.50	0.60	1.00	1.50	1.50	1.50	0.60	3.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.50
Dispatch	3.67
Overall L1	3.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.67 cycles. At this rate:

12% of peak load performance is reached (24.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.55 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 451f57

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0xd0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP -0xc8(%RBP),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 4525c4 <hypre_BoomerAMGBuildMultipass.extracted.34+0x9a4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x88(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDX,%RSI,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x90(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,(%RDX,%RDI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x98(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,(%RDX,%RDI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xa8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RDI,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 451fce <hypre_BoomerAMGBuildMultipass.extracted.34+0x3ae>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0xa0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RDI,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RDX,%RDI,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JL 4523cc <hypre_BoomerAMGBuildMultipass.extracted.34+0x7ac>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 451f40 <hypre_BoomerAMGBuildMultipass.extracted.34+0x320>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 451f40 <hypre_BoomerAMGBuildMultipass.extracted.34+0x320>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code