OV - exec - Function hypre_CSRMatrixMatvecT.extracted.49

	Function: hypre_CSRMatrixMatvecT.extracted.49	Module: exec	Source: csr_matvec.c:554-579 [...]	Coverage (incl. loops): 1.26% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 554 - 579

--------------------------------------------------------------------------------

554: #pragma omp parallel private(i,jj,j,my_thread_num,offset)

555: #endif

556:          {

557:             my_thread_num = hypre_GetThreadNum();

558:             offset =  y_size*my_thread_num;

559: #ifdef HYPRE_USING_OPENMP

560: #pragma omp for HYPRE_SMP_SCHEDULE

561: #endif

562:             for (i = 0; i < num_rows; i++)

563:             {

564:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

565:                {

566:                   j = A_j[jj];

567:                   y_data_expand[offset + j] += A_data[jj] * x_data[i];

[...]

573: #pragma omp for HYPRE_SMP_SCHEDULE

574: #endif

575:             for (i = 0; i < y_size; i++)

576:             {

577:                for (j = 0; j < num_threads; j++)

578:                {

579:                   y_data[i] += y_data_expand[j*y_size + i];

0x512940 PUSH	%RBP

0x512941 MOV	%RSP,%RBP

0x512944 PUSH	%R15

0x512946 PUSH	%R14

0x512948 PUSH	%R13

0x51294a PUSH	%R12

0x51294c PUSH	%RBX

0x51294d SUB	$0x78,%RSP

0x512951 MOV	%R9,-0x30(%RBP)

0x512955 MOV	%R8,%R14

0x512958 MOV	%RCX,-0x90(%RBP)

0x51295f MOV	%RDX,%R12

0x512962 MOV	%RDI,%R13

0x512965 MOV	0x30(%RBP),%RAX

0x512969 MOV	%RAX,-0x80(%RBP)

0x51296d MOV	0x28(%RBP),%RBX

0x512971 MOV	0x20(%RBP),%RAX

0x512975 MOV	%RAX,-0x38(%RBP)

0x512979 MOV	0x18(%RBP),%RAX

0x51297d MOV	%RAX,-0x50(%RBP)

0x512981 MOV	0x10(%RBP),%R15

0x512985 CALL	51da60 <hypre_GetThreadNum>

0x51298a MOV	-0x30(%RBP),%RDX

0x51298e MOV	%R13,%RCX

0x512991 TEST	%RDX,%RDX

0x512994 JLE	512a14

0x512996 MOV	%RAX,%R13

0x512999 DEC	%RDX

0x51299c MOVL	$0,-0x44(%RBP)

0x5129a3 MOV	%RCX,-0x78(%RBP)

0x5129a7 MOV	(%RCX),%ESI

0x5129a9 MOVQ	$0,-0x70(%RBP)

0x5129b1 MOV	%RDX,-0x68(%RBP)

0x5129b5 MOVQ	$0x1,-0xa0(%RBP)

0x5129c0 SUB	$0x8,%RSP

0x5129c4 LEA	-0xa0(%RBP),%RAX

0x5129cb LEA	-0x44(%RBP),%RCX

0x5129cf LEA	-0x70(%RBP),%R8

0x5129d3 LEA	-0x68(%RBP),%R9

0x5129d7 MOV	$0x560ff0,%EDI

0x5129dc MOV	%ESI,-0x3c(%RBP)

0x5129df MOV	$0x22,%EDX

0x5129e4 PUSH	$0x1

0x5129e6 PUSH	$0x1

0x5129e8 PUSH	%RAX

0x5129e9 CALL	410430 <__kmpc_for_static_init_8@plt>

0x5129ee ADD	$0x20,%RSP

0x5129f2 MOV	-0x70(%RBP),%RCX

0x5129f6 MOV	-0x68(%RBP),%R11

0x5129fa SUB	%RCX,%R11

0x5129fd JAE	512b80

0x512a03 MOV	$0x561010,%EDI

0x512a08 MOV	-0x3c(%RBP),%ESI

0x512a0b CALL	410180 <__kmpc_for_static_fini@plt>

0x512a10 MOV	-0x78(%RBP),%RCX

0x512a14 MOV	(%RCX),%ESI

0x512a16 MOV	%RCX,%R12

0x512a19 MOV	$0x561030,%EDI

0x512a1e CALL	410570 <__kmpc_barrier@plt>

0x512a23 MOV	-0x38(%RBP),%R15

0x512a27 TEST	%R15,%R15

0x512a2a JLE	512b40

0x512a30 LEA	-0x1(%R15),%RAX

0x512a34 MOVL	$0,-0x40(%RBP)

0x512a3b MOV	(%R12),%R14D

0x512a3f MOVQ	$0,-0x60(%RBP)

0x512a47 MOV	%RAX,-0x58(%RBP)

0x512a4b MOVQ	$0x1,-0x98(%RBP)

0x512a56 SUB	$0x8,%RSP

0x512a5a LEA	-0x98(%RBP),%RAX

0x512a61 LEA	-0x40(%RBP),%RCX

0x512a65 LEA	-0x60(%RBP),%R8

0x512a69 LEA	-0x58(%RBP),%R9

0x512a6d MOV	$0x560f90,%EDI

0x512a72 MOV	%R14D,%ESI

0x512a75 MOV	$0x22,%EDX

0x512a7a PUSH	$0x1

0x512a7c PUSH	$0x1

0x512a7e PUSH	%RAX

0x512a7f CALL	410430 <__kmpc_for_static_init_8@plt>

0x512a84 ADD	$0x20,%RSP

0x512a88 MOV	-0x60(%RBP),%RAX

0x512a8c MOV	-0x58(%RBP),%RDX

0x512a90 MOV	%RDX,%RCX

0x512a93 SUB	%RAX,%RCX

0x512a96 MOV	-0x80(%RBP),%R13

0x512a9a MOV	-0x50(%RBP),%R11

0x512a9e JB	512b30

0x512aa4 LEA	(%R11,%RDX,8),%RDI

0x512aa8 MOV	%R15,%R8

0x512aab SAR	$0x3f,%R8

0x512aaf AND	%R15,%R8

0x512ab2 MOV	%RAX,%RSI

0x512ab5 SUB	%R8,%RSI

0x512ab8 IMUL	%R13,%R8

0x512abc ADD	%RSI,%R8

0x512abf XOR	%ESI,%ESI

0x512ac1 TEST	%R15,%R15

0x512ac4 LEA	(%RBX,%R8,8),%R8

0x512ac8 CMOVG	%R15,%RSI

0x512acc CMP	%R8,%RDI

0x512acf JB	512d80

0x512ad5 SUB	%RSI,%RDX

0x512ad8 IMUL	%R13,%RSI

0x512adc ADD	%RDX,%RSI

0x512adf LEA	(%RBX,%RSI,8),%RDX

0x512ae3 LEA	(%R11,%RAX,8),%RSI

0x512ae7 CMP	%RSI,%RDX

0x512aea JB	512d80

0x512af0 LEA	(%RBX,%RAX,8),%RDX

0x512af4 SAL	$0x3,%R15

0x512af8 XOR	%ESI,%ESI

0x512afa NOPW	(%RAX,%RAX,1)

(4357) 0x512b00 LEA	(%RAX,%RSI,1),%RDI

(4357) 0x512b04 VMOVSD	(%R11,%RDI,8),%XMM0

(4357) 0x512b0a MOV	%RDX,%R8

(4357) 0x512b0d MOV	%R13,%R9

  (4356) 0x512b10 VADDSD	(%R8),%XMM0,%XMM0

  (4356) 0x512b15 VMOVSD	%XMM0,(%R11,%RDI,8)

  (4356) 0x512b1b ADD	%R15,%R8

  (4356) 0x512b1e DEC	%R9

  (4356) 0x512b21 JNE	512b10

(4357) 0x512b23 ADD	$0x8,%RDX

(4357) 0x512b27 CMP	%RCX,%RSI

(4357) 0x512b2a LEA	0x1(%RSI),%RSI

(4357) 0x512b2e JNE	512b00

0x512b30 MOV	$0x560fb0,%EDI

0x512b35 MOV	%R14D,%ESI

0x512b38 VZEROUPPER

0x512b3b CALL	410180 <__kmpc_for_static_fini@plt>

0x512b40 MOV	(%R12),%ESI

0x512b44 MOV	$0x560fd0,%EDI

0x512b49 ADD	$0x78,%RSP

0x512b4d POP	%RBX

0x512b4e POP	%R12

0x512b50 POP	%R13

0x512b52 POP	%R14

0x512b54 POP	%R15

0x512b56 POP	%RBP

0x512b57 JMP	410570

0x512b5c NOPW	%CS:(%RAX,%RAX,1)

0x512b6b NOPW	%CS:(%RAX,%RAX,1)

0x512b7a NOPW	(%RAX,%RAX,1)

0x512b80 IMUL	-0x38(%RBP),%R13

0x512b85 XOR	%EDX,%EDX

0x512b87 MOV	%RCX,-0x30(%RBP)

0x512b8b MOV	%R11,-0x88(%RBP)

0x512b92 JMP	512bcd

0x512b94 NOPW	%CS:(%RAX,%RAX,1)

0x512ba3 NOPW	%CS:(%RAX,%RAX,1)

0x512bb2 NOPW	%CS:(%RAX,%RAX,1)

(4358) 0x512bc0 CMP	%R11,%RDX

(4358) 0x512bc3 LEA	0x1(%RDX),%RDX

(4358) 0x512bc7 JE	512a03

(4358) 0x512bcd LEA	(%RCX,%RDX,1),%RSI

(4358) 0x512bd1 MOV	-0x90(%RBP),%RAX

(4358) 0x512bd8 MOV	(%RAX,%RSI,8),%RDI

(4358) 0x512bdc MOV	0x8(%RAX,%RSI,8),%R8

(4358) 0x512be1 MOV	%R8,%R10

(4358) 0x512be4 SUB	%RDI,%R10

(4358) 0x512be7 JLE	512bc0

(4358) 0x512be9 MOV	%R10,%R9

(4358) 0x512bec AND	$-0x4,%R9

(4358) 0x512bf0 JE	512c40

(4358) 0x512bf2 LEA	-0x1(%R9),%RAX

(4358) 0x512bf6 XOR	%R11D,%R11D

(4358) 0x512bf9 NOPL	(%RAX)

  (4362) 0x512c00 ADD	$0x4,%R11

  (4362) 0x512c04 CMP	%RAX,%R11

  (4362) 0x512c07 JBE	512c00

(4358) 0x512c09 MOV	%R9,%RAX

(4358) 0x512c0c CMP	%R9,%R10

(4358) 0x512c0f JNE	512c42

(4358) 0x512c11 JMP	512c55

0x512c13 NOPW	%CS:(%RAX,%RAX,1)

0x512c22 NOPW	%CS:(%RAX,%RAX,1)

0x512c31 NOPW	%CS:(%RAX,%RAX,1)

(4358) 0x512c40 XOR	%EAX,%EAX

(4358) 0x512c42 ADD	%RDI,%RAX

(4358) 0x512c45 SUB	%R8,%RAX

(4358) 0x512c48 NOPL	(%RAX,%RAX,1)

  (4359) 0x512c50 INC	%RAX

  (4359) 0x512c53 JNE	512c50

(4358) 0x512c55 CMP	$0x4,%R10

(4358) 0x512c59 JB	512cfb

(4358) 0x512c5f MOV	%R10,%R11

(4358) 0x512c62 SHR	$0x2,%R11

(4358) 0x512c66 LEA	0x18(,%RDI,8),%RAX

(4358) 0x512c6e XCHG	%AX,%AX

  (4361) 0x512c70 VMOVSD	(%R15,%RSI,8),%XMM0

  (4361) 0x512c76 VMOVSD	-0x18(%R12,%RAX,1),%XMM1

  (4361) 0x512c7d MOV	-0x18(%R14,%RAX,1),%RCX

  (4361) 0x512c82 ADD	%R13,%RCX

  (4361) 0x512c85 VFMADD213SD	(%RBX,%RCX,8),%XMM0,%XMM1

  (4361) 0x512c8b VMOVSD	%XMM1,(%RBX,%RCX,8)

  (4361) 0x512c90 VMOVSD	(%R15,%RSI,8),%XMM0

  (4361) 0x512c96 VMOVSD	-0x10(%R12,%RAX,1),%XMM1

  (4361) 0x512c9d MOV	-0x10(%R14,%RAX,1),%RCX

  (4361) 0x512ca2 ADD	%R13,%RCX

  (4361) 0x512ca5 VFMADD213SD	(%RBX,%RCX,8),%XMM0,%XMM1

  (4361) 0x512cab VMOVSD	%XMM1,(%RBX,%RCX,8)

  (4361) 0x512cb0 VMOVSD	(%R15,%RSI,8),%XMM0

  (4361) 0x512cb6 VMOVSD	-0x8(%R12,%RAX,1),%XMM1

  (4361) 0x512cbd MOV	-0x8(%R14,%RAX,1),%RCX

  (4361) 0x512cc2 ADD	%R13,%RCX

  (4361) 0x512cc5 VFMADD213SD	(%RBX,%RCX,8),%XMM0,%XMM1

  (4361) 0x512ccb VMOVSD	%XMM1,(%RBX,%RCX,8)

  (4361) 0x512cd0 VMOVSD	(%R15,%RSI,8),%XMM0

  (4361) 0x512cd6 VMOVSD	(%R12,%RAX,1),%XMM1

  (4361) 0x512cdc MOV	(%R14,%RAX,1),%RCX

  (4361) 0x512ce0 ADD	%R13,%RCX

  (4361) 0x512ce3 VFMADD213SD	(%RBX,%RCX,8),%XMM0,%XMM1

  (4361) 0x512ce9 VMOVSD	%XMM1,(%RBX,%RCX,8)

  (4361) 0x512cee ADD	$0x20,%RAX

  (4361) 0x512cf2 DEC	%R11

  (4361) 0x512cf5 JNE	512c70

(4358) 0x512cfb CMP	%R10,%R9

(4358) 0x512cfe MOV	-0x30(%RBP),%RCX

(4358) 0x512d02 MOV	-0x88(%RBP),%R11

(4358) 0x512d09 JAE	512bc0

(4358) 0x512d0f ADD	%R9,%RDI

(4358) 0x512d12 NOPW	%CS:(%RAX,%RAX,1)

  (4360) 0x512d20 VMOVSD	(%R15,%RSI,8),%XMM0

  (4360) 0x512d26 VMOVSD	(%R12,%RDI,8),%XMM1

  (4360) 0x512d2c MOV	(%R14,%RDI,8),%RAX

  (4360) 0x512d30 ADD	%R13,%RAX

  (4360) 0x512d33 VFMADD213SD	(%RBX,%RAX,8),%XMM0,%XMM1

  (4360) 0x512d39 VMOVSD	%XMM1,(%RBX,%RAX,8)

  (4360) 0x512d3e INC	%RDI

  (4360) 0x512d41 CMP	%RDI,%R8

  (4360) 0x512d44 JNE	512d20

(4358) 0x512d46 JMP	512bc0

0x512d4b NOPW	%CS:(%RAX,%RAX,1)

0x512d5a NOPW	%CS:(%RAX,%RAX,1)

0x512d69 NOPW	%CS:(%RAX,%RAX,1)

0x512d78 NOPL	(%RAX,%RAX,1)

0x512d80 MOV	%R13,%RDX

0x512d83 AND	$-0x4,%RDX

0x512d87 LEA	-0x1(%RDX),%RSI

0x512d8b VPBROADCASTQ	%R15,%YMM0

0x512d91 LEA	(,%R15,8),%RDI

0x512d99 XOR	%R8D,%R8D

0x512d9c VMOVDQU	0x172dc(%RIP),%YMM1

0x512da4 MOV	%RAX,%R9

0x512da7 JMP	512dda

0x512da9 NOPW	%CS:(%RAX,%RAX,1)

0x512db8 NOPL	(%RAX,%RAX,1)

(4354) 0x512dc0 MOV	-0x50(%RBP),%R11

(4354) 0x512dc4 VMOVSD	%XMM2,(%R11,%R10,8)

(4354) 0x512dca INC	%R9

(4354) 0x512dcd CMP	%RCX,%R8

(4354) 0x512dd0 LEA	0x1(%R8),%R8

(4354) 0x512dd4 JE	512b30

(4354) 0x512dda LEA	(%RAX,%R8,1),%R10

(4354) 0x512dde VMOVSD	(%R11,%R10,8),%XMM2

(4354) 0x512de4 TEST	%RDX,%RDX

(4354) 0x512de7 JE	512e80

(4354) 0x512ded VPBROADCASTQ	%R10,%YMM4

(4354) 0x512df3 VXORPD	%XMM3,%XMM3,%XMM3

(4354) 0x512df7 XOR	%R11D,%R11D

(4354) 0x512dfa NOPW	(%RAX,%RAX,1)

  (4355) 0x512e00 VPBROADCASTQ	%R11,%YMM5

  (4355) 0x512e06 VPADDQ	%YMM1,%YMM5,%YMM5

  (4355) 0x512e0a VPMULLQ	%YMM5,%YMM0,%YMM5

  (4355) 0x512e10 VPADDQ	%YMM5,%YMM4,%YMM5

  (4355) 0x512e14 VXORPD	%XMM6,%XMM6,%XMM6

  (4355) 0x512e18 KXNORW	%K0,%K0,%K1

  (4355) 0x512e1c VGATHERQPD	(%RBX,%YMM5,8),%YMM6{%K1}

  (4355) 0x512e23 VADDPD	%YMM6,%YMM3,%YMM3

  (4355) 0x512e27 ADD	$0x4,%R11

  (4355) 0x512e2b CMP	%RSI,%R11

  (4355) 0x512e2e JLE	512e00

(4354) 0x512e30 VEXTRACTF128	$0x1,%YMM3,%XMM4

(4354) 0x512e36 VADDPD	%XMM4,%XMM3,%XMM3

(4354) 0x512e3a VSHUFPD	$0x1,%XMM3,%XMM3,%XMM4

(4354) 0x512e3f VADDSD	%XMM4,%XMM3,%XMM3

(4354) 0x512e43 VADDSD	%XMM3,%XMM2,%XMM2

(4354) 0x512e47 MOV	%RDX,%R15

(4354) 0x512e4a CMP	%R13,%RDX

(4354) 0x512e4d JE	512dc0

(4354) 0x512e53 JMP	512e83

0x512e55 NOPW	%CS:(%RAX,%RAX,1)

0x512e64 NOPW	%CS:(%RAX,%RAX,1)

0x512e73 NOPW	%CS:(%RAX,%RAX,1)

(4354) 0x512e80 XOR	%R15D,%R15D

(4354) 0x512e83 MOV	%R13,%R11

(4354) 0x512e86 SUB	%R15,%R11

(4354) 0x512e89 IMUL	-0x38(%RBP),%R15

(4354) 0x512e8e ADD	%R9,%R15

(4354) 0x512e91 LEA	(%RBX,%R15,8),%R15

(4354) 0x512e95 NOPW	%CS:(%RAX,%RAX,1)

  (4353) 0x512ea0 VADDSD	(%R15),%XMM2,%XMM2

  (4353) 0x512ea5 ADD	%RDI,%R15

  (4353) 0x512ea8 DEC	%R11

  (4353) 0x512eab JNE	512ea0

(4354) 0x512ead JMP	512dc0

0x512eb2 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_4

Source file and lines	csr_matvec.c:554-579
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:554-567,573-579.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 27.83 to 3.00 cycles (9.28x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_barrier@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560
__kmpc_for_static_fini@plt: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:573
__kmpc_for_static_init_8@plt: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:573
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:557

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:573

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 172 bytes. The binary function is storing 124 bytes.

General properties

nb instructions	160
nb uops	167
loop length	811
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	0
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	27.83 cycles
front end	27.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.90	6.80	9.00	9.00	17.50	6.80	6.70	17.50	17.50	17.50	6.80	9.00
cycles	6.90	7.20	9.00	9.00	17.50	6.80	6.70	17.50	17.50	17.50	6.80	9.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	27.83
Dispatch	17.50
Overall L1	27.83

Vectorization ratios

all	5%
load	25%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Vector efficiency ratios

all	11%
load	20%
store	9%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 27.83 cycles. At this rate:

3% of peak load performance is reached (6.18 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.46 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 27.83 to 17.50 cycles (1.59x speedup).

ASM code

In the binary file, the address of the function is: 512940

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 51da60 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R13,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 512a14 <hypre_CSRMatrixMatvecT.extracted.49+0xd4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
DEC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVL $0,-0x44(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RCX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RCX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVQ $0,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RDX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0xa0(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x44(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x70(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x68(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x560ff0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 410430 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x70(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JAE 512b80 <hypre_CSRMatrixMatvecT.extracted.49+0x240>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x561010,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV -0x3c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 410180 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x78(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x561030,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 410570 <__kmpc_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %R15,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 512b40 <hypre_CSRMatrixMatvecT.extracted.49+0x200>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%R15),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%R12),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x98(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x60(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x58(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x560f90,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 410430 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x58(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x80(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x50(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JB 512b30 <hypre_CSRMatrixMatvecT.extracted.49+0x1f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%R11,%RDX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAR $0x3f,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND %R15,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R8,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %R13,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RSI,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %R15,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
LEA (%RBX,%R8,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMOVG %R15,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
CMP %R8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 512d80 <hypre_CSRMatrixMatvecT.extracted.49+0x440>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %R13,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RBX,%RSI,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R11,%RAX,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 512d80 <hypre_CSRMatrixMatvecT.extracted.49+0x440>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%RBX,%RAX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x560fb0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 410180 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV (%R12),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x560fd0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 410570 <__kmpc_barrier@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL -0x38(%RBP),%R13	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 512bcd <hypre_CSRMatrixMatvecT.extracted.49+0x28d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R13,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA -0x1(%RDX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %R15,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA (,%R15,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVDQU 0x172dc(%RIP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 512dda <hypre_CSRMatrixMatvecT.extracted.49+0x49a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_4

Source file and lines	csr_matvec.c:554-579
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:554-567,573-579.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 27.83 to 3.00 cycles (9.28x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

__kmpc_barrier@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560
__kmpc_for_static_fini@plt: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:573
__kmpc_for_static_init_8@plt: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:573
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:557

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:573

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 172 bytes. The binary function is storing 124 bytes.

General properties

nb instructions	160
nb uops	167
loop length	811
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	0
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	27.83 cycles
front end	27.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.90	6.80	9.00	9.00	17.50	6.80	6.70	17.50	17.50	17.50	6.80	9.00
cycles	6.90	7.20	9.00	9.00	17.50	6.80	6.70	17.50	17.50	17.50	6.80	9.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	27.83
Dispatch	17.50
Overall L1	27.83

Vectorization ratios

all	5%
load	25%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Vector efficiency ratios

all	11%
load	20%
store	9%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 27.83 cycles. At this rate:

3% of peak load performance is reached (6.18 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.46 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 512940

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 51da60 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R13,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 512a14 <hypre_CSRMatrixMatvecT.extracted.49+0xd4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
DEC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVL $0,-0x44(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RCX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RCX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVQ $0,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RDX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0xa0(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x44(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x70(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x68(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x560ff0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 410430 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x70(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JAE 512b80 <hypre_CSRMatrixMatvecT.extracted.49+0x240>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x561010,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV -0x3c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 410180 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x78(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x561030,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 410570 <__kmpc_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %R15,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 512b40 <hypre_CSRMatrixMatvecT.extracted.49+0x200>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%R15),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%R12),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x98(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x60(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x58(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x560f90,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 410430 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x58(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x80(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x50(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JB 512b30 <hypre_CSRMatrixMatvecT.extracted.49+0x1f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%R11,%RDX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAR $0x3f,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND %R15,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R8,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %R13,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RSI,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %R15,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
LEA (%RBX,%R8,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMOVG %R15,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
CMP %R8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 512d80 <hypre_CSRMatrixMatvecT.extracted.49+0x440>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %R13,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RBX,%RSI,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R11,%RAX,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 512d80 <hypre_CSRMatrixMatvecT.extracted.49+0x440>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%RBX,%RAX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x560fb0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 410180 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV (%R12),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x560fd0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 410570 <__kmpc_barrier@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL -0x38(%RBP),%R13	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 512bcd <hypre_CSRMatrixMatvecT.extracted.49+0x28d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R13,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA -0x1(%RDX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %R15,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA (,%R15,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVDQU 0x172dc(%RIP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 512dda <hypre_CSRMatrixMatvecT.extracted.49+0x49a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMatvecT.extracted.49–	1.26	0.67
▼Loop 4358 - csr_matvec.c:560-567 - exec–	0.60	0.26
○Loop 4360 - csr_matvec.c:564-567 - exec	0.49	0.21
○Loop 4361 - csr_matvec.c:564-567 - exec	0.10	0.04
○Loop 4359 - csr_matvec.c:564-564 - exec	0.02	0.01
○Loop 4362 - csr_matvec.c:564-564 - exec	0.01	0.01
▼Loop 4354 - csr_matvec.c:560-579 - exec–	0.00	0.01
○Loop 4355 - csr_matvec.c:577-579 - exec	0.03	0.02
○Loop 4353 - csr_matvec.c:577-579 - exec	0.00	0.00
▼Loop 4357 - csr_matvec.c:573-579 - exec–	0.00	0.00
○Loop 4356 - csr_matvec.c:577-579 - exec	0.00	0.00

Report Configuration

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Execution units bottlenecks

512-bits vectorization

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CALL instructions

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Complex instructions

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Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code