OV - exec - Function hypre_CSRMatrixMatvecOutOfPlace.extracted.19

	Function: hypre_CSRMatrixMatvecOutOfPlace.extracted.19	Module: exec	Source: csr_matvec.c:178-204 [...]	Coverage (incl. loops): 0.04% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 178 - 204

--------------------------------------------------------------------------------

178: #pragma omp parallel for private(i,j,jj,m,tempx) HYPRE_SMP_SCHEDULE

179: #endif

180:

181:          for (i = 0; i < num_rownnz; i++)

182:          {

183:             m = A_rownnz[i];

[...]

191:             if ( num_vectors==1 )

192:             {

193:                tempx = 0;

194:                for (jj = A_i[m]; jj < A_i[m+1]; jj++)

195:                   tempx +=  A_data[jj] * x_data[A_j[jj]];

196:                y_data[m] += tempx;

197:             }

198:             else

199:                for ( j=0; j<num_vectors; ++j )

200:                {

201:                   tempx = 0;

202:                   for (jj = A_i[m]; jj < A_i[m+1]; jj++)

203:                      tempx +=  A_data[jj] * x_data[ j*vecstride_x + A_j[jj]*idxstride_x ];

204:                   y_data[ j*vecstride_y + m*idxstride_y] += tempx;

0x5120e0 PUSH	%RBP

0x5120e1 MOV	%RSP,%RBP

0x5120e4 PUSH	%R15

0x5120e6 PUSH	%R14

0x5120e8 PUSH	%R13

0x5120ea PUSH	%R12

0x5120ec PUSH	%RBX

0x5120ed SUB	$0x78,%RSP

0x5120f1 MOV	0x40(%RBP),%RAX

0x5120f5 MOV	%RAX,-0x70(%RBP)

0x5120f9 MOV	0x38(%RBP),%R12

0x5120fd MOV	0x30(%RBP),%RAX

0x512101 MOV	%RAX,-0x98(%RBP)

0x512108 MOV	0x28(%RBP),%RAX

0x51210c MOV	%RAX,-0x80(%RBP)

0x512110 MOV	0x20(%RBP),%RBX

0x512114 MOV	0x18(%RBP),%RAX

0x512118 MOV	%RAX,-0x68(%RBP)

0x51211c MOV	0x10(%RBP),%R14

0x512120 MOVL	$0,-0x30(%RBP)

0x512127 MOV	%R9,-0x50(%RBP)

0x51212b MOV	%R8,%R15

0x51212e MOV	%RCX,-0x48(%RBP)

0x512132 MOV	%RDX,%R13

0x512135 MOV	(%RDI),%ESI

0x512137 MOVQ	$0,-0x78(%RBP)

0x51213f MOVQ	$0x1,-0xa0(%RBP)

0x51214a SUB	$0x8,%RSP

0x51214e LEA	-0xa0(%RBP),%RAX

0x512155 LEA	-0x30(%RBP),%RCX

0x512159 LEA	-0x78(%RBP),%R8

0x51215d LEA	0x50(%RBP),%R9

0x512161 MOV	$0x560db0,%EDI

0x512166 MOV	%ESI,-0x2c(%RBP)

0x512169 MOV	$0x22,%EDX

0x51216e PUSH	$0x1

0x512170 PUSH	$0x1

0x512172 PUSH	%RAX

0x512173 CALL	410430 <__kmpc_for_static_init_8@plt>

0x512178 ADD	$0x20,%RSP

0x51217c MOV	-0x78(%RBP),%RAX

0x512180 MOV	0x50(%RBP),%RCX

0x512184 MOV	%RAX,-0x40(%RBP)

0x512188 SUB	%RAX,%RCX

0x51218b MOV	%RCX,-0x38(%RBP)

0x51218f JAE	5121c0

0x512191 MOV	$0x560dd0,%EDI

0x512196 MOV	-0x2c(%RBP),%ESI

0x512199 ADD	$0x78,%RSP

0x51219d POP	%RBX

0x51219e POP	%R12

0x5121a0 POP	%R13

0x5121a2 POP	%R14

0x5121a4 POP	%R15

0x5121a6 POP	%RBP

0x5121a7 VZEROUPPER

0x5121aa JMP	410180

0x5121af NOPW	%CS:(%RAX,%RAX,1)

0x5121be XCHG	%AX,%AX

0x5121c0 CMP	$0x1,%RBX

0x5121c4 JNE	512300

0x5121ca XOR	%EDX,%EDX

0x5121cc JMP	51221c

0x5121ce NOPW	%CS:(%RAX,%RAX,1)

0x5121dd NOPW	%CS:(%RAX,%RAX,1)

0x5121ec NOPW	%CS:(%RAX,%RAX,1)

0x5121fb NOPL	(%RAX,%RAX,1)

(4342) 0x512200 MOV	-0x68(%RBP),%RCX

(4342) 0x512204 VADDSD	(%RCX,%RAX,8),%XMM0,%XMM0

(4342) 0x512209 VMOVSD	%XMM0,(%RCX,%RAX,8)

(4342) 0x51220e CMP	-0x38(%RBP),%RDX

(4342) 0x512212 LEA	0x1(%RDX),%RDX

(4342) 0x512216 JE	512191

(4342) 0x51221c MOV	-0x40(%RBP),%RAX

(4342) 0x512220 ADD	%RDX,%RAX

(4342) 0x512223 MOV	-0x50(%RBP),%RCX

(4342) 0x512227 MOV	(%RCX,%RAX,8),%RAX

(4342) 0x51222b MOV	-0x48(%RBP),%RCX

(4342) 0x51222f MOV	(%RCX,%RAX,8),%RDI

(4342) 0x512233 MOV	0x8(%RCX,%RAX,8),%RCX

(4342) 0x512238 VXORPD	%XMM0,%XMM0,%XMM0

(4342) 0x51223c MOV	%RCX,%R8

(4342) 0x51223f SUB	%RDI,%R8

(4342) 0x512242 JLE	512200

(4342) 0x512244 MOV	%R8,%RSI

(4342) 0x512247 AND	$-0x4,%RSI

(4342) 0x51224b JE	5122c0

(4342) 0x51224d LEA	-0x1(%RSI),%R9

(4342) 0x512251 LEA	(%R13,%RDI,8),%R10

(4342) 0x512256 LEA	(%R15,%RDI,8),%R11

(4342) 0x51225a VXORPD	%XMM0,%XMM0,%XMM0

(4342) 0x51225e XOR	%R12D,%R12D

(4342) 0x512261 NOPW	%CS:(%RAX,%RAX,1)

  (4344) 0x512270 VMOVUPD	(%R11,%R12,8),%YMM1

  (4344) 0x512276 VXORPD	%XMM2,%XMM2,%XMM2

  (4344) 0x51227a KXNORW	%K0,%K0,%K1

  (4344) 0x51227e VGATHERQPD	(%R14,%YMM1,8),%YMM2{%K1}

  (4344) 0x512285 VFMADD231PD	(%R10,%R12,8),%YMM2,%YMM0

  (4344) 0x51228b ADD	$0x4,%R12

  (4344) 0x51228f CMP	%R9,%R12

  (4344) 0x512292 JBE	512270

(4342) 0x512294 VEXTRACTF128	$0x1,%YMM0,%XMM1

(4342) 0x51229a VADDPD	%XMM1,%XMM0,%XMM0

(4342) 0x51229e VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

(4342) 0x5122a3 VADDSD	%XMM1,%XMM0,%XMM0

(4342) 0x5122a7 CMP	%RSI,%R8

(4342) 0x5122aa JE	512200

(4342) 0x5122b0 JMP	5122c2

0x5122b2 NOPW	%CS:(%RAX,%RAX,1)

(4342) 0x5122c0 XOR	%ESI,%ESI

(4342) 0x5122c2 ADD	%RDI,%RSI

(4342) 0x5122c5 NOPW	%CS:(%RAX,%RAX,1)

  (4343) 0x5122d0 MOV	(%R15,%RSI,8),%RDI

  (4343) 0x5122d4 VMOVSD	(%R14,%RDI,8),%XMM1

  (4343) 0x5122da VFMADD231SD	(%R13,%RSI,8),%XMM1,%XMM0

  (4343) 0x5122e1 INC	%RSI

  (4343) 0x5122e4 CMP	%RSI,%RCX

  (4343) 0x5122e7 JNE	5122d0

(4342) 0x5122e9 JMP	512200

0x5122ee NOPW	%CS:(%RAX,%RAX,1)

0x5122fd NOPL	(%RAX)

0x512300 JL	512191

0x512306 DEC	%RBX

0x512309 MOV	%RBX,-0x90(%RBP)

0x512310 VPBROADCASTQ	%R12,%YMM0

0x512316 XOR	%ECX,%ECX

0x512318 JMP	512355

0x51231a NOPW	%CS:(%RAX,%RAX,1)

0x512329 NOPW	%CS:(%RAX,%RAX,1)

0x512338 NOPL	(%RAX,%RAX,1)

(4338) 0x512340 MOV	-0x88(%RBP),%RCX

(4338) 0x512347 CMP	-0x38(%RBP),%RCX

(4338) 0x51234b LEA	0x1(%RCX),%RCX

(4338) 0x51234f JE	512191

(4338) 0x512355 MOV	-0x40(%RBP),%RAX

(4338) 0x512359 MOV	%RCX,-0x88(%RBP)

(4338) 0x512360 ADD	%RCX,%RAX

(4338) 0x512363 MOV	-0x50(%RBP),%RCX

(4338) 0x512367 MOV	(%RCX,%RAX,8),%RSI

(4338) 0x51236b MOV	-0x48(%RBP),%RAX

(4338) 0x51236f MOV	(%RAX,%RSI,8),%RCX

(4338) 0x512373 MOV	0x8(%RAX,%RSI,8),%R8

(4338) 0x512378 MOV	%R8,%RAX

(4338) 0x51237b MOV	%RCX,-0x60(%RBP)

(4338) 0x51237f SUB	%RCX,%RAX

(4338) 0x512382 MOV	%RAX,-0x58(%RBP)

(4338) 0x512386 JLE	512340

(4338) 0x512388 MOV	-0x58(%RBP),%R9

(4338) 0x51238c AND	$-0x4,%R9

(4338) 0x512390 LEA	-0x1(%R9),%R11

(4338) 0x512394 IMUL	-0x80(%RBP),%RSI

(4338) 0x512399 MOV	-0x60(%RBP),%RCX

(4338) 0x51239d LEA	(%R13,%RCX,8),%RAX

(4338) 0x5123a2 LEA	(%R15,%RCX,8),%RCX

(4338) 0x5123a6 XOR	%EDI,%EDI

(4338) 0x5123a8 JMP	5123f2

0x5123aa NOPW	%CS:(%RAX,%RAX,1)

0x5123b9 NOPL	(%RAX)

  (4340) 0x5123c0 MOV	%RDI,%RDX

  (4340) 0x5123c3 IMUL	-0x98(%RBP),%RDX

  (4340) 0x5123cb ADD	%RSI,%RDX

  (4340) 0x5123ce MOV	-0x68(%RBP),%R10

  (4340) 0x5123d2 VADDSD	(%R10,%RDX,8),%XMM1,%XMM1

  (4340) 0x5123d8 VMOVSD	%XMM1,(%R10,%RDX,8)

  (4340) 0x5123de MOV	-0x90(%RBP),%RDX

  (4340) 0x5123e5 CMP	%RDX,%RDI

  (4340) 0x5123e8 LEA	0x1(%RDI),%RDI

  (4340) 0x5123ec JE	512340

  (4340) 0x5123f2 TEST	%R9,%R9

  (4340) 0x5123f5 JE	512480

  (4340) 0x5123fb MOV	%RDI,%RDX

  (4340) 0x5123fe IMUL	-0x70(%RBP),%RDX

  (4340) 0x512403 VPBROADCASTQ	%RDX,%YMM2

  (4340) 0x512409 VXORPD	%XMM1,%XMM1,%XMM1

  (4340) 0x51240d XOR	%EDX,%EDX

  (4340) 0x51240f NOP

    (4341) 0x512410 VXORPS	%XMM3,%XMM3,%XMM3

    (4341) 0x512414 VPMULLQ	(%RCX,%RDX,8),%YMM0,%YMM3

    (4341) 0x51241b VPADDQ	%YMM2,%YMM3,%YMM3

    (4341) 0x51241f KXNORW	%K0,%K0,%K1

    (4341) 0x512423 VXORPD	%XMM4,%XMM4,%XMM4

    (4341) 0x512427 VGATHERQPD	(%R14,%YMM3,8),%YMM4{%K1}

    (4341) 0x51242e VFMADD231PD	(%RAX,%RDX,8),%YMM4,%YMM1

    (4341) 0x512434 ADD	$0x4,%RDX

    (4341) 0x512438 CMP	%R11,%RDX

    (4341) 0x51243b JBE	512410

  (4340) 0x51243d VEXTRACTF128	$0x1,%YMM1,%XMM2

  (4340) 0x512443 VADDPD	%XMM2,%XMM1,%XMM1

  (4340) 0x512447 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM2

  (4340) 0x51244c VADDSD	%XMM2,%XMM1,%XMM1

  (4340) 0x512450 MOV	%R9,%R10

  (4340) 0x512453 CMP	%R9,-0x58(%RBP)

  (4340) 0x512457 JE	5123c0

  (4340) 0x51245d JMP	512487

0x51245f NOPW	%CS:(%RAX,%RAX,1)

0x51246e NOPW	%CS:(%RAX,%RAX,1)

0x51247d NOPL	(%RAX)

  (4340) 0x512480 VXORPD	%XMM1,%XMM1,%XMM1

  (4340) 0x512484 XOR	%R10D,%R10D

  (4340) 0x512487 MOV	%RDI,%RDX

  (4340) 0x51248a IMUL	-0x70(%RBP),%RDX

  (4340) 0x51248f ADD	-0x60(%RBP),%R10

  (4340) 0x512493 NOPW	%CS:(%RAX,%RAX,1)

    (4339) 0x5124a0 MOV	(%R15,%R10,8),%RBX

    (4339) 0x5124a4 IMUL	%R12,%RBX

    (4339) 0x5124a8 ADD	%RDX,%RBX

    (4339) 0x5124ab VMOVSD	(%R14,%RBX,8),%XMM2

    (4339) 0x5124b1 VFMADD231SD	(%R13,%R10,8),%XMM2,%XMM1

    (4339) 0x5124b8 INC	%R10

    (4339) 0x5124bb CMP	%R10,%R8

    (4339) 0x5124be JNE	5124a0

  (4340) 0x5124c0 JMP	5123c0

0x5124c5 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►99.89+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_4

Source file and lines	csr_matvec.c:178-204
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178-183,191-204.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.50 to 1.50 cycles (9.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 80 bytes. The binary function is storing 96 bytes.

General properties

nb instructions	85
nb uops	87
loop length	450
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.50 cycles
front end	14.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.90	1.80	5.67	5.67	11.50	1.80	1.70	11.50	11.50	11.50	1.80	5.67
cycles	1.90	1.80	5.67	5.67	11.50	1.80	1.70	11.50	11.50	11.50	1.80	5.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.50
Dispatch	11.50
Overall L1	14.50

Vectorization ratios

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Vector efficiency ratios

all	11%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.50 cycles. At this rate:

2% of peak load performance is reached (5.52 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.62 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 14.50 to 11.50 cycles (1.26x speedup).

ASM code

In the binary file, the address of the function is: 5120e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R9,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x1,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0xa0(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x78(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x50(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x560db0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 410430 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x78(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x50(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RCX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JAE 5121c0 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0xe0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x560dd0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x2c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 410180 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x1,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 512300 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x220>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 51221c <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x13c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JL 512191 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0xb1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
DEC %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %R12,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 512355 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x275>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_4

Source file and lines	csr_matvec.c:178-204
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178-183,191-204.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.50 to 1.50 cycles (9.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 80 bytes. The binary function is storing 96 bytes.

General properties

nb instructions	85
nb uops	87
loop length	450
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.50 cycles
front end	14.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.90	1.80	5.67	5.67	11.50	1.80	1.70	11.50	11.50	11.50	1.80	5.67
cycles	1.90	1.80	5.67	5.67	11.50	1.80	1.70	11.50	11.50	11.50	1.80	5.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.50
Dispatch	11.50
Overall L1	14.50

Vectorization ratios

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Vector efficiency ratios

all	11%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.50 cycles. At this rate:

2% of peak load performance is reached (5.52 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.62 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 5120e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R9,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x1,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0xa0(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x78(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x50(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x560db0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 410430 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x78(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x50(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RCX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JAE 5121c0 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0xe0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x560dd0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x2c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 410180 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x1,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 512300 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x220>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 51221c <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x13c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JL 512191 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0xb1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
DEC %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %R12,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 512355 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x275>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMatvecOutOfPlace.extracted.19–	0.04	0.02
▼Loop 4342 - csr_matvec.c:178-196 - exec–	0.00	0.01
○Loop 4344 - csr_matvec.c:194-195 - exec	0.04	0.02
○Loop 4343 - csr_matvec.c:194-195 - exec	0.00	0.01
▼Loop 4338 - csr_matvec.c:178-204 - exec–	0.00	0.00
▼Loop 4340 - csr_matvec.c:199-204 - exec–	0.00	0.00
○Loop 4341 - csr_matvec.c:202-203 - exec	0.00	0.00
○Loop 4339 - csr_matvec.c:202-203 - exec	0.00	0.00

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Code clean check

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Vectorization

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Workaround

Execution units bottlenecks

512-bits vectorization

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CALL instructions

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Complex instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code