OV - exec - Function hypre_IJMatrixSetValuesOMPParCSR.extracted.28

	Function: hypre_IJMatrixSetValuesOMPParCSR.extracted.28	Module: exec	Source: IJMatrix_parcsr.c:3240-3484 [...]	Coverage (incl. loops): 1.17% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 3240 - 3484

--------------------------------------------------------------------------------

3240: #pragma omp parallel

[...]

3256:          num_threads = hypre_NumActiveThreads();

3257:          my_thread_num = hypre_GetThreadNum();

3258:

3259:          len = nrows/num_threads;

3260:          rest = nrows - len*num_threads;

3261:

3262:          if (my_thread_num < rest)

3263:          {

3264:             ns = my_thread_num*(len+1);

3265:             ne = (my_thread_num+1)*(len+1);

3266:          }

3267:          else

3268:          {

3269:             ns = my_thread_num*len+rest;

3270:             ne = (my_thread_num+1)*len+rest;

3271:          }

3272:

3273:          value_start[my_thread_num] = 0;

3274:          for (ii=ns; ii < ne; ii++)

3275:             value_start[my_thread_num] += ncols[ii];

3276:

3277: #ifdef HYPRE_USING_OPENMP

3278: #pragma omp barrier

3279: #endif

3280:          if (my_thread_num == 0)

3281:          {

3282:             for (i=0; i < max_num_threads; i++)

3283:                value_start[i+1] += value_start[i];

[...]

3289:          if (my_thread_num)

3290:             indx = value_start[my_thread_num-1];

3291:          for (ii=ns; ii < ne; ii++)

3292:          {

3293:             row = rows[ii];

3294:             n = ncols[ii];

3295:             /* processor owns the row */

3296:             if (row >= row_partitioning[pstart] && row < row_partitioning[pstart+1])

3297:             {

3298:                row_local = row - row_partitioning[pstart];

3299:                /* compute local row number */

3300:                if (need_aux)

3301:                {

3302:                   local_j = aux_j[row_local];

3303:                   local_data = aux_data[row_local];

3304:    	          space = row_space[row_local];

3305:    	          old_size = row_length[row_local];

3306:    	          size = space - old_size;

3307:    	          if (size < n)

3308:       	          {

3309:       	             size = n - size;

3310:       	             tmp_j = hypre_CTAlloc(HYPRE_Int,size);

3311:       	             tmp_data = hypre_CTAlloc(HYPRE_Complex,size);

3312:       	          }

3313:       	          tmp_indx = 0;

3314:       	          not_found = 1;

3315:       	          size = old_size;

3316:                   for (i=0; i < n; i++)

3317:       	          {

3318:       	             for (j=0; j < old_size; j++)

3319:       	             {

3320:       	                if (local_j[j] == cols[indx])

3321:       	                {

3322:                            local_data[j] = values[indx];

[...]

3329:       	                if (size < space)

3330:       	                {

3331:       	                   local_j[size] = cols[indx];

3332:       	                   local_data[size++] = values[indx];

3333:       	                }

3334:       	                else

3335:       	                {

3336:       	                   tmp_j[tmp_indx] = cols[indx];

3337:       	                   tmp_data[tmp_indx++] = values[indx];

[...]

3344:                   row_length[row_local] = size+tmp_indx;

3345:

3346:                   if (tmp_indx)

3347:                   {

3348:    	             aux_j[row_local] = hypre_TReAlloc(aux_j[row_local],HYPRE_Int,

3349:                                                     size+tmp_indx);

3350:    	             aux_data[row_local] = hypre_TReAlloc(aux_data[row_local],

3351:                                                        HYPRE_Complex,size+tmp_indx);

3352:                      row_space[row_local] = size+tmp_indx;

3353:                      local_j = aux_j[row_local];

[...]

3359:    	          for (i=0; i < tmp_indx; i++)

3360:    	          {

3361:    	             local_j[cnt] = tmp_j[i];

3362:    	             local_data[cnt++] = tmp_data[i];

3363: 	          }

3364:

3365: 	          if (tmp_j)

3366: 	          {

3367: 	             hypre_TFree(tmp_j);

3368: 	             hypre_TFree(tmp_data);

[...]

3376: 	          offd_indx = hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local];

3377: 	          diag_indx = hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local];

3378: 	          cnt_diag = diag_indx;

3379: 	          cnt_offd = offd_indx;

3380: 	          diag_space = diag_i[row_local+1];

3381: 	          offd_space = offd_i[row_local+1];

3382: 	          not_found = 1;

3383:   	          for (i=0; i < n; i++)

3384: 	          {

3385: 	             if (cols[indx] < col_0 || cols[indx] > col_n)

3386:                      /* insert into offd */

3387: 	             {

3388: 	                for (j=offd_i[row_local]; j < offd_indx; j++)

3389: 	                {

3390: 		           if (offd_j[j] == cols[indx])

3391: 		           {

3392:                               offd_data[j] = values[indx];

[...]

3399: 	                   if (cnt_offd < offd_space)

3400: 	                   {

3401: 	                      offd_j[cnt_offd] = cols[indx];

3402: 	                      offd_data[cnt_offd++] = values[indx];

3403: 	                   }

3404: 	                   else

3405: 	 	           {

3406:                               hypre_error(HYPRE_ERROR_GENERIC);

3407: #ifdef HYPRE_USING_OPENMP

3408: #pragma omp atomic

3409: #endif

3410:                               error_flag++;

[...]

3422: 	                for (j=diag_i[row_local]; j < diag_indx; j++)

3423: 	                {

3424: 		           if (diag_j[j] == cols[indx])

3425: 		           {

3426:                               diag_data[j] = values[indx];

[...]

3433: 	                   if (cnt_diag < diag_space)

3434: 	                   {

3435: 	                      diag_j[cnt_diag] = cols[indx];

3436: 	                      diag_data[cnt_diag++] = values[indx];

3437: 	                   }

3438: 	                   else

3439: 	 	           {

3440:                               hypre_error(HYPRE_ERROR_GENERIC);

3441: #ifdef HYPRE_USING_OPENMP

3442: #pragma omp atomic

3443: #endif

3444:                               error_flag++;

3445: 	    	              if (print_level)

[...]

3454: 	             indx++;

3455: 	          }

3456:

3457:                   hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local] = cnt_diag;

3458:                   hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local] = cnt_offd;

[...]

3466:                indx +=  n;

3467:    	       if (aux_matrix)

3468:                {

3469:                   col_indx = 0;

3470:                   for (i=0; i < off_proc_i_indx; i=i+2)

3471:                   {

3472: 	             row_len = off_proc_i[i+1];

3473: 	             if (off_proc_i[i] == row)

3474: 		     {

3475: 		        for (j=0; j < n; j++)

3476: 		        {

3477: 			   cnt1 = col_indx;

3478: 			   for (k=0; k < row_len; k++)

3479: 			   {

3480: 			      if (off_proc_j[cnt1] == cols[j])

3481: 			      {

3482:                                  off_proc_j[cnt1++] = -1;

3483:                		         /*cancel_indx++;*/

3484: 	                         offproc_cnt[my_thread_num]++;

0x503c60 PUSH	%RBP

0x503c61 MOV	%RSP,%RBP

0x503c64 PUSH	%R15

0x503c66 PUSH	%R14

0x503c68 PUSH	%R13

0x503c6a PUSH	%R12

0x503c6c PUSH	%RBX

0x503c6d SUB	$0x98,%RSP

0x503c74 MOV	%R9,%RBX

0x503c77 MOV	%R8,-0x60(%RBP)

0x503c7b MOV	%RCX,-0x50(%RBP)

0x503c7f MOV	%RDX,%R15

0x503c82 MOV	%RDI,%R12

0x503c85 CALL	51da50 <hypre_NumActiveThreads>

0x503c8a MOV	%RAX,%R13

0x503c8d CALL	51da60 <hypre_GetThreadNum>

0x503c92 MOV	%RAX,%R14

0x503c95 MOV	%R13,%RAX

0x503c98 OR	%R15,%RAX

0x503c9b SHR	$0x20,%RAX

0x503c9f JE	503cc0

0x503ca1 MOV	%R15,%RAX

0x503ca4 CQTO

0x503ca6 IDIV	%R13

0x503ca9 JMP	503cc8

0x503cab NOPW	%CS:(%RAX,%RAX,1)

0x503cba NOPW	(%RAX,%RAX,1)

0x503cc0 MOV	%R15D,%EAX

0x503cc3 XOR	%EDX,%EDX

0x503cc5 DIV	%R13D

0x503cc8 MOV	%R12,%R13

0x503ccb MOV	0xb8(%RBP),%R15

0x503cd2 LEA	0x1(%R14),%RCX

0x503cd6 CMP	%RDX,%R14

0x503cd9 JGE	503d00

0x503cdb LEA	0x1(%RAX),%RDI

0x503cdf MOV	%RDI,%RSI

0x503ce2 IMUL	%R14,%RSI

0x503ce6 IMUL	%RCX,%RDI

0x503cea MOV	%RDI,%RCX

0x503ced JMP	503d11

0x503cef NOPW	%CS:(%RAX,%RAX,1)

0x503cfe XCHG	%AX,%AX

0x503d00 MOV	%RAX,%RSI

0x503d03 IMUL	%R14,%RSI

0x503d07 ADD	%RDX,%RSI

0x503d0a IMUL	%RAX,%RCX

0x503d0e ADD	%RDX,%RCX

0x503d11 MOVQ	$0,(%R15,%R14,8)

0x503d19 MOV	%RSI,%R12

0x503d1c MOV	%RCX,-0x48(%RBP)

0x503d20 CMP	%RCX,%RSI

0x503d23 JGE	503df0

0x503d29 CMP	%RDX,%R14

0x503d2c CMOVL	%R14,%RDX

0x503d30 IMUL	%R14,%RAX

0x503d34 MOV	-0x48(%RBP),%RDI

0x503d38 SUB	%RDX,%RDI

0x503d3b SUB	%RAX,%RDI

0x503d3e MOV	%RDI,%RCX

0x503d41 AND	$-0x4,%RCX

0x503d45 JE	503dc0

0x503d47 LEA	-0x1(%RCX),%RSI

0x503d4b MOV	-0x50(%RBP),%R8

0x503d4f LEA	(%R8,%R12,8),%R8

0x503d53 VPXOR	%XMM0,%XMM0,%XMM0

0x503d57 XOR	%R9D,%R9D

0x503d5a NOPW	(%RAX,%RAX,1)

(4074) 0x503d60 VPADDQ	(%R8,%R9,8),%YMM0,%YMM0

(4074) 0x503d66 ADD	$0x4,%R9

(4074) 0x503d6a CMP	%RSI,%R9

(4074) 0x503d6d JBE	503d60

0x503d6f VEXTRACTI128	$0x1,%YMM0,%XMM1

0x503d75 VPADDQ	%XMM1,%XMM0,%XMM0

0x503d79 VPSHUFD	$-0x12,%XMM0,%XMM1

0x503d7e VPADDQ	%XMM1,%XMM0,%XMM0

0x503d82 VMOVQ	%XMM0,%RSI

0x503d87 CMP	%RCX,%RDI

0x503d8a MOV	-0x50(%RBP),%RDI

0x503d8e MOV	-0x48(%RBP),%R8

0x503d92 JNE	503dcc

0x503d94 JMP	503dec

0x503d96 NOPW	%CS:(%RAX,%RAX,1)

0x503da5 NOPW	%CS:(%RAX,%RAX,1)

0x503db4 NOPW	%CS:(%RAX,%RAX,1)

0x503dc0 XOR	%ECX,%ECX

0x503dc2 XOR	%ESI,%ESI

0x503dc4 MOV	-0x50(%RBP),%RDI

0x503dc8 MOV	-0x48(%RBP),%R8

0x503dcc ADD	%RDX,%RCX

0x503dcf ADD	%RAX,%RCX

0x503dd2 NOPW	%CS:(%RAX,%RAX,1)

(4073) 0x503de0 ADD	(%RDI,%RCX,8),%RSI

(4073) 0x503de4 INC	%RCX

(4073) 0x503de7 CMP	%RCX,%R8

(4073) 0x503dea JNE	503de0

0x503dec MOV	%RSI,(%R15,%R14,8)

0x503df0 MOV	(%R13),%ESI

0x503df4 MOV	$0x560570,%EDI

0x503df9 VZEROUPPER

0x503dfc CALL	410570 <__kmpc_barrier@plt>

0x503e01 TEST	%R14,%R14

0x503e04 JNE	503ea4

0x503e0a MOV	0xc8(%RBP),%RAX

0x503e11 TEST	%RAX,%RAX

0x503e14 JLE	503ea4

0x503e1a CMP	$0x8,%RAX

0x503e1e JB	503e77

0x503e20 MOV	%RAX,%RCX

0x503e23 SHR	$0x3,%RCX

0x503e27 MOV	(%R15),%RDX

0x503e2a LEA	0x40(%R15),%RSI

0x503e2e XCHG	%AX,%AX

(4072) 0x503e30 ADD	-0x38(%RSI),%RDX

(4072) 0x503e34 MOV	%RDX,-0x38(%RSI)

(4072) 0x503e38 ADD	-0x30(%RSI),%RDX

(4072) 0x503e3c MOV	%RDX,-0x30(%RSI)

(4072) 0x503e40 ADD	-0x28(%RSI),%RDX

(4072) 0x503e44 MOV	%RDX,-0x28(%RSI)

(4072) 0x503e48 ADD	-0x20(%RSI),%RDX

(4072) 0x503e4c MOV	%RDX,-0x20(%RSI)

(4072) 0x503e50 ADD	-0x18(%RSI),%RDX

(4072) 0x503e54 MOV	%RDX,-0x18(%RSI)

(4072) 0x503e58 ADD	-0x10(%RSI),%RDX

(4072) 0x503e5c MOV	%RDX,-0x10(%RSI)

(4072) 0x503e60 ADD	-0x8(%RSI),%RDX

(4072) 0x503e64 MOV	%RDX,-0x8(%RSI)

(4072) 0x503e68 ADD	(%RSI),%RDX

(4072) 0x503e6b MOV	%RDX,(%RSI)

(4072) 0x503e6e ADD	$0x40,%RSI

(4072) 0x503e72 DEC	%RCX

(4072) 0x503e75 JNE	503e30

0x503e77 MOV	%RAX,%RCX

0x503e7a AND	$-0x8,%RCX

0x503e7e CMP	%RAX,%RCX

0x503e81 JAE	503ea4

0x503e83 MOV	(%R15,%RCX,8),%RDX

0x503e87 NOPW	(%RAX,%RAX,1)

(4071) 0x503e90 LEA	(%R15,%RCX,8),%RSI

(4071) 0x503e94 INC	%RCX

(4071) 0x503e97 ADD	0x8(%RSI),%RDX

(4071) 0x503e9b MOV	%RDX,0x8(%RSI)

(4071) 0x503e9f CMP	%RCX,%RAX

(4071) 0x503ea2 JNE	503e90

0x503ea4 MOV	(%R13),%ESI

0x503ea8 MOV	$0x560590,%EDI

0x503ead CALL	410570 <__kmpc_barrier@plt>

0x503eb2 TEST	%R14,%R14

0x503eb5 JE	503f00

0x503eb7 MOV	-0x8(%R15,%R14,8),%RAX

0x503ebc MOV	%RAX,-0x38(%RBP)

0x503ec0 JMP	503f08

0x503ec2 NOPW	%CS:(%RAX,%RAX,1)

0x503ed1 NOPW	%CS:(%RAX,%RAX,1)

0x503ee0 NOPW	%CS:(%RAX,%RAX,1)

0x503eef NOPW	%CS:(%RAX,%RAX,1)

0x503efe XCHG	%AX,%AX

0x503f00 MOVQ	$0,-0x38(%RBP)

0x503f08 MOV	-0x60(%RBP),%RDX

0x503f0c MOV	-0x50(%RBP),%RSI

0x503f10 MOV	%R12,%R9

0x503f13 MOV	-0x48(%RBP),%RAX

0x503f17 CMP	%RAX,%R12

0x503f1a JGE	504d80

0x503f20 MOV	0xb0(%RBP),%RAX

0x503f27 MOV	0xa8(%RBP),%R8

0x503f2e MOV	0x98(%RBP),%RDI

0x503f35 MOV	0x18(%RBP),%RCX

0x503f39 TEST	%RCX,%RCX

0x503f3c SETE	%CL

0x503f3f LEA	(%RAX,%R14,8),%R12

0x503f43 TEST	%RDI,%RDI

0x503f46 SETLE	%AL

0x503f49 OR	%CL,%AL

0x503f4b MOV	%AL,-0x39(%RBP)

0x503f4e MOV	-0x48(%RBP),%RCX

0x503f52 DEC	%RDI

0x503f55 SHR	$0x1,%RDI

0x503f58 MOV	%RDI,-0xb8(%RBP)

0x503f5f MOV	0x20(%RBP),%RAX

0x503f63 ADD	$0x18,%R8

0x503f67 MOV	%R8,-0xb0(%RBP)

0x503f6e MOVQ	$0,-0x88(%RBP)

0x503f79 JMP	503fea

0x503f7b NOPL	(%RAX,%RAX,1)

(4050) 0x503f80 SAL	$0x3,%RDX

(4050) 0x503f84 MOV	%R14,-0x88(%RBP)

(4050) 0x503f8b MOV	%R13,%RSI

(4050) 0x503f8e MOV	%RDX,%R14

(4050) 0x503f91 CALL	526020 <__intel_avx_rep_memcpy>

(4050) 0x503f96 MOV	%R15,%RDI

(4050) 0x503f99 MOV	-0x88(%RBP),%RSI

(4050) 0x503fa0 MOV	%R14,%RDX

(4050) 0x503fa3 CALL	526020 <__intel_avx_rep_memcpy>

(4050) 0x503fa8 MOV	%R13,%RDI

(4050) 0x503fab VZEROUPPER

(4050) 0x503fae CALL	51b990 <hypre_Free>

(4050) 0x503fb3 MOV	-0x88(%RBP),%RDI

(4050) 0x503fba CALL	51b990 <hypre_Free>

(4050) 0x503fbf MOVQ	$0,-0x88(%RBP)

(4050) 0x503fca MOV	-0x60(%RBP),%RDX

(4050) 0x503fce MOV	-0x50(%RBP),%RSI

(4050) 0x503fd2 MOV	-0x68(%RBP),%R9

(4050) 0x503fd6 MOV	-0x48(%RBP),%RCX

(4050) 0x503fda MOV	0x20(%RBP),%RAX

(4050) 0x503fde INC	%R9

(4050) 0x503fe1 CMP	%RCX,%R9

(4050) 0x503fe4 JGE	504d80

(4050) 0x503fea MOV	(%RDX,%R9,8),%R10

(4050) 0x503fee MOV	(%RSI,%R9,8),%R15

(4050) 0x503ff2 MOV	%R10,-0x58(%RBP)

(4050) 0x503ff6 SUB	(%RAX),%R10

(4050) 0x503ff9 JL	5040c0

(4050) 0x503fff MOV	-0x58(%RBP),%R8

(4050) 0x504003 CMP	0x8(%RAX),%R8

(4050) 0x504007 JGE	5040c0

(4050) 0x50400d CMPQ	$0,0x58(%RBP)

(4050) 0x504012 MOV	%R10,-0x30(%RBP)

(4050) 0x504016 JE	504380

(4050) 0x50401c MOV	0x38(%RBP),%RAX

(4050) 0x504020 MOV	(%RAX,%R10,8),%R13

(4050) 0x504024 MOV	0x40(%RBP),%RAX

(4050) 0x504028 MOV	(%RAX,%R10,8),%RAX

(4050) 0x50402c MOV	%RAX,-0x70(%RBP)

(4050) 0x504030 MOV	0x50(%RBP),%RAX

(4050) 0x504034 MOV	(%RAX,%R10,8),%RCX

(4050) 0x504038 MOV	0x48(%RBP),%RAX

(4050) 0x50403c MOV	(%RAX,%R10,8),%R14

(4050) 0x504040 MOV	%RCX,-0x80(%RBP)

(4050) 0x504044 MOV	%RCX,%RAX

(4050) 0x504047 SUB	%R14,%RAX

(4050) 0x50404a MOV	%R15,%RDI

(4050) 0x50404d SUB	%RAX,%RDI

(4050) 0x504050 MOV	%R9,-0x68(%RBP)

(4050) 0x504054 JLE	504800

(4050) 0x50405a MOV	$0x8,%ESI

(4050) 0x50405f MOV	%RDI,-0x58(%RBP)

(4050) 0x504063 VZEROUPPER

(4050) 0x504066 CALL	51b840 <hypre_CAlloc>

(4050) 0x50406b MOV	%RAX,-0x78(%RBP)

(4050) 0x50406f MOV	$0x8,%ESI

(4050) 0x504074 MOV	-0x58(%RBP),%RDI

(4050) 0x504078 CALL	51b840 <hypre_CAlloc>

(4050) 0x50407d MOV	-0x30(%RBP),%R10

(4050) 0x504081 MOV	%RAX,-0x88(%RBP)

(4050) 0x504088 MOV	-0x38(%RBP),%RSI

(4050) 0x50408c TEST	%R15,%R15

(4050) 0x50408f JG	504815

(4050) 0x504095 MOV	0x48(%RBP),%RAX

(4050) 0x504099 MOV	%R14,(%RAX,%R10,8)

(4050) 0x50409d JMP	504b40

0x5040a2 NOPW	%CS:(%RAX,%RAX,1)

0x5040b1 NOPW	%CS:(%RAX,%RAX,1)

(4050) 0x5040c0 ADD	%R15,-0x38(%RBP)

(4050) 0x5040c4 CMPB	$0,-0x39(%RBP)

(4050) 0x5040c8 JNE	503fde

(4050) 0x5040ce TEST	%R15,%R15

(4050) 0x5040d1 JLE	503fde

(4050) 0x5040d7 MOV	%R9,-0x68(%RBP)

(4050) 0x5040db DEC	%R15

(4050) 0x5040de XOR	%ECX,%ECX

(4050) 0x5040e0 XOR	%EAX,%EAX

(4050) 0x5040e2 JMP	504111

0x5040e4 NOPW	%CS:(%RAX,%RAX,1)

0x5040f3 NOPW	%CS:(%RAX,%RAX,1)

  (4051) 0x504100 CMP	-0xb8(%RBP),%RAX

  (4051) 0x504107 LEA	0x1(%RAX),%RAX

  (4051) 0x50410b JE	503fca

  (4051) 0x504111 MOV	%RCX,%R9

  (4051) 0x504114 MOV	%RAX,%RSI

  (4051) 0x504117 SAL	$0x4,%RSI

  (4051) 0x50411b MOV	0xa0(%RBP),%RDI

  (4051) 0x504122 MOV	0x8(%RDI,%RSI,1),%RDX

  (4051) 0x504127 ADD	%RDX,%RCX

  (4051) 0x50412a MOV	-0x58(%RBP),%R8

  (4051) 0x50412e CMP	%R8,(%RDI,%RSI,1)

  (4051) 0x504132 JNE	504100

  (4051) 0x504134 TEST	%RDX,%RDX

  (4051) 0x504137 JLE	504100

  (4051) 0x504139 MOV	0xa8(%RBP),%RSI

  (4051) 0x504140 LEA	-0x8(%RSI,%RCX,8),%RDI

  (4051) 0x504145 LEA	(%RSI,%R9,8),%RSI

  (4051) 0x504149 CMP	%R12,%RDI

  (4051) 0x50414c JB	504200

  (4051) 0x504152 CMP	%RSI,%R12

  (4051) 0x504155 JB	504200

  (4051) 0x50415b XOR	%EDI,%EDI

  (4051) 0x50415d JMP	50418d

0x50415f NOPW	%CS:(%RAX,%RAX,1)

0x50416e NOPW	%CS:(%RAX,%RAX,1)

0x50417d NOPL	(%RAX)

    (4055) 0x504180 CMP	%R15,%RDI

    (4055) 0x504183 LEA	0x1(%RDI),%RDI

    (4055) 0x504187 JE	504100

    (4055) 0x50418d MOV	(%RBX,%RDI,8),%R8

    (4055) 0x504191 XOR	%R9D,%R9D

    (4055) 0x504194 JMP	5041c8

0x504196 NOPW	%CS:(%RAX,%RAX,1)

0x5041a5 NOPW	%CS:(%RAX,%RAX,1)

0x5041b4 NOPW	%CS:(%RAX,%RAX,1)

      (4056) 0x5041c0 INC	%R9

      (4056) 0x5041c3 CMP	%R9,%RDX

      (4056) 0x5041c6 JE	504180

      (4056) 0x5041c8 CMP	%R8,(%RSI,%R9,8)

      (4056) 0x5041cc JNE	5041c0

      (4056) 0x5041ce MOVQ	$-0x1,(%RSI,%R9,8)

      (4056) 0x5041d6 INCQ	(%R12)

      (4056) 0x5041da JMP	5041c0

0x5041dc NOPW	%CS:(%RAX,%RAX,1)

0x5041eb NOPW	%CS:(%RAX,%RAX,1)

0x5041fa NOPW	(%RAX,%RAX,1)

  (4051) 0x504200 MOV	%RDX,%RDI

  (4051) 0x504203 SHR	$0x2,%RDI

  (4051) 0x504207 MOV	%RDX,%R8

  (4051) 0x50420a AND	$-0x4,%R8

  (4051) 0x50420e MOV	-0xb0(%RBP),%R10

  (4051) 0x504215 LEA	(%R10,%R9,8),%R14

  (4051) 0x504219 XOR	%R10D,%R10D

  (4051) 0x50421c JMP	50424d

0x50421e NOPW	%CS:(%RAX,%RAX,1)

0x50422d NOPW	%CS:(%RAX,%RAX,1)

0x50423c NOPL	(%RAX)

    (4052) 0x504240 CMP	%R15,%R10

    (4052) 0x504243 LEA	0x1(%R10),%R10

    (4052) 0x504247 JE	504100

    (4052) 0x50424d MOV	(%RBX,%R10,8),%R11

    (4052) 0x504251 CMP	$0x4,%RDX

    (4052) 0x504255 JAE	5042c0

    (4052) 0x504257 CMP	%RDX,%R8

    (4052) 0x50425a JAE	504240

    (4052) 0x50425c MOV	%R8,%R9

    (4052) 0x50425f JMP	504288

0x504261 NOPW	%CS:(%RAX,%RAX,1)

0x504270 NOPW	%CS:(%RAX,%RAX,1)

0x50427f NOP

      (4053) 0x504280 INC	%R9

      (4053) 0x504283 CMP	%R9,%RDX

      (4053) 0x504286 JE	504240

      (4053) 0x504288 CMP	%R11,(%RSI,%R9,8)

      (4053) 0x50428c JNE	504280

      (4053) 0x50428e MOVQ	$-0x1,(%RSI,%R9,8)

      (4053) 0x504296 INCQ	(%R12)

      (4053) 0x50429a JMP	504280

0x50429c NOPW	%CS:(%RAX,%RAX,1)

0x5042ab NOPW	%CS:(%RAX,%RAX,1)

0x5042ba NOPW	(%RAX,%RAX,1)

    (4052) 0x5042c0 MOV	%RDI,%R13

    (4052) 0x5042c3 MOV	%R14,%R9

    (4052) 0x5042c6 JMP	50430d

0x5042c8 NOPW	%CS:(%RAX,%RAX,1)

0x5042d7 NOPW	%CS:(%RAX,%RAX,1)

0x5042e6 NOPW	%CS:(%RAX,%RAX,1)

0x5042f5 NOPW	%CS:(%RAX,%RAX,1)

      (4054) 0x504300 ADD	$0x20,%R9

      (4054) 0x504304 DEC	%R13

      (4054) 0x504307 JE	504257

      (4054) 0x50430d CMP	%R11,-0x18(%R9)

      (4054) 0x504311 JNE	504340

      (4054) 0x504313 MOVQ	$-0x1,-0x18(%R9)

      (4054) 0x50431b INCQ	(%R12)

      (4054) 0x50431f CMP	%R11,-0x10(%R9)

      (4054) 0x504323 JE	504346

      (4054) 0x504325 CMP	%R11,-0x8(%R9)

      (4054) 0x504329 JNE	504358

      (4054) 0x50432b MOVQ	$-0x1,-0x8(%R9)

      (4054) 0x504333 INCQ	(%R12)

      (4054) 0x504337 CMP	%R11,(%R9)

      (4054) 0x50433a JNE	504300

      (4054) 0x50433c JMP	50435d

0x50433e XCHG	%AX,%AX

      (4054) 0x504340 CMP	%R11,-0x10(%R9)

      (4054) 0x504344 JNE	504325

      (4054) 0x504346 MOVQ	$-0x1,-0x10(%R9)

      (4054) 0x50434e INCQ	(%R12)

      (4054) 0x504352 CMP	%R11,-0x8(%R9)

      (4054) 0x504356 JE	50432b

      (4054) 0x504358 CMP	%R11,(%R9)

      (4054) 0x50435b JNE	504300

      (4054) 0x50435d MOVQ	$-0x1,(%R9)

      (4054) 0x504364 INCQ	(%R12)

      (4054) 0x504368 JMP	504300

0x50436a NOPW	%CS:(%RAX,%RAX,1)

0x504379 NOPL	(%RAX)

(4050) 0x504380 MOV	0x18(%RBP),%RCX

(4050) 0x504384 MOV	0x38(%RCX),%RAX

(4050) 0x504388 MOV	0x40(%RCX),%RCX

(4050) 0x50438c MOV	(%RCX,%R10,8),%R8

(4050) 0x504390 MOV	(%RAX,%R10,8),%R11

(4050) 0x504394 TEST	%R15,%R15

(4050) 0x504397 JLE	504b80

(4050) 0x50439d MOV	%R9,-0x68(%RBP)

(4050) 0x5043a1 MOV	0x60(%RBP),%RAX

(4050) 0x5043a5 MOV	0x8(%RAX,%R10,8),%RAX

(4050) 0x5043aa MOV	%RAX,-0x78(%RBP)

(4050) 0x5043ae MOV	0x78(%RBP),%RAX

(4050) 0x5043b2 MOV	0x8(%RAX,%R10,8),%RAX

(4050) 0x5043b7 MOV	%RAX,-0x98(%RBP)

(4050) 0x5043be XOR	%EDI,%EDI

(4050) 0x5043c0 MOV	%R8,-0x80(%RBP)

(4050) 0x5043c4 MOV	%R11,-0x90(%RBP)

(4050) 0x5043cb MOV	%R11,-0x70(%RBP)

(4050) 0x5043cf MOV	-0x38(%RBP),%RSI

(4050) 0x5043d3 LEA	(%RSI,%R15,1),%RAX

(4050) 0x5043d7 MOV	%RAX,-0xa0(%RBP)

(4050) 0x5043de MOV	%R8,%RCX

(4050) 0x5043e1 JMP	504416

0x5043e3 NOPW	%CS:(%RAX,%RAX,1)

0x5043f2 NOPW	%CS:(%RAX,%RAX,1)

  (4057) 0x504400 MOV	-0x30(%RBP),%R10

  (4057) 0x504404 MOV	%RCX,%R8

  (4057) 0x504407 INC	%RSI

  (4057) 0x50440a INC	%RDI

  (4057) 0x50440d CMP	%R15,%RDI

  (4057) 0x504410 JE	504bc0

  (4057) 0x504416 MOV	(%RBX,%RSI,8),%R9

  (4057) 0x50441a CMP	0x28(%RBP),%R9

  (4057) 0x50441e JL	504580

  (4057) 0x504424 CMP	0x30(%RBP),%R9

  (4057) 0x504428 JG	504580

  (4057) 0x50442e MOV	0x60(%RBP),%RAX

  (4057) 0x504432 MOV	(%RAX,%R10,8),%R10

  (4057) 0x504436 MOV	-0x90(%RBP),%R11

  (4057) 0x50443d SUB	%R10,%R11

  (4057) 0x504440 JLE	504530

  (4057) 0x504446 MOV	0x68(%RBP),%RAX

  (4057) 0x50444a LEA	(%RAX,%R10,8),%EAX

  (4057) 0x50444e AND	$0x7f,%EAX

  (4057) 0x504451 MOV	$0x80,%EDX

  (4057) 0x504456 SUB	%EAX,%EDX

  (4057) 0x504458 SHR	$0x3,%EDX

  (4057) 0x50445b CMP	%RDX,%R11

  (4057) 0x50445e MOV	%RDX,%R8

  (4057) 0x504461 CMOVB	%R11,%R8

  (4057) 0x504465 TEST	%R8,%R8

  (4057) 0x504468 JE	504486

  (4057) 0x50446a MOV	%R10,%R13

  (4057) 0x50446d MOV	%R8,%RAX

    (4063) 0x504470 MOV	0x68(%RBP),%R14

    (4063) 0x504474 CMP	%R9,(%R14,%R13,8)

    (4063) 0x504478 JE	50472a

    (4063) 0x50447e INC	%R13

    (4063) 0x504481 DEC	%RAX

    (4063) 0x504484 JNE	504470

  (4057) 0x504486 CMP	%RDX,%R11

  (4057) 0x504489 JBE	504530

  (4057) 0x50448f MOV	%RSI,-0x38(%RBP)

  (4057) 0x504493 SUB	%R8,%R11

  (4057) 0x504496 MOV	%R11,%R14

  (4057) 0x504499 AND	$-0x10,%R14

  (4057) 0x50449d JE	5044fa

  (4057) 0x50449f LEA	-0x1(%R14),%RSI

  (4057) 0x5044a3 LEA	(%R10,%R8,1),%R13

  (4057) 0x5044a7 VPBROADCASTQ	%R9,%YMM0

  (4057) 0x5044ad MOV	0x68(%RBP),%RAX

  (4057) 0x5044b1 LEA	(%RAX,%R13,8),%RAX

  (4057) 0x5044b5 XOR	%EDX,%EDX

  (4057) 0x5044b7 NOPW	(%RAX,%RAX,1)

    (4062) 0x5044c0 VPCMPEQQ	0x20(%RAX,%RDX,8),%YMM0,%K0

    (4062) 0x5044c8 VPCMPEQQ	(%RAX,%RDX,8),%YMM0,%K1

    (4062) 0x5044cf VPCMPEQQ	0x60(%RAX,%RDX,8),%YMM0,%K2

    (4062) 0x5044d7 VPCMPEQQ	0x40(%RAX,%RDX,8),%YMM0,%K3

    (4062) 0x5044df KORB	%K0,%K1,%K4

    (4062) 0x5044e3 KORB	%K2,%K3,%K5

    (4062) 0x5044e7 KORTESTB	%K5,%K4

    (4062) 0x5044eb JNE	504700

    (4062) 0x5044f1 ADD	$0x10,%RDX

    (4062) 0x5044f5 CMP	%RSI,%RDX

    (4062) 0x5044f8 JBE	5044c0

  (4057) 0x5044fa CMP	%R11,%R14

  (4057) 0x5044fd MOV	-0x38(%RBP),%RSI

  (4057) 0x504501 JAE	504530

  (4057) 0x504503 ADD	%R8,%R10

  (4057) 0x504506 ADD	%R14,%R10

  (4057) 0x504509 MOV	%R10,%R13

  (4057) 0x50450c NOPL	(%RAX)

    (4061) 0x504510 MOV	0x68(%RBP),%RAX

    (4061) 0x504514 CMP	%R9,(%RAX,%R13,8)

    (4061) 0x504518 JE	50472a

    (4061) 0x50451e INC	%R13

    (4061) 0x504521 CMP	%R13,-0x90(%RBP)

    (4061) 0x504528 JNE	504510

  (4057) 0x50452a NOPW	(%RAX,%RAX,1)

  (4057) 0x504530 MOV	-0x70(%RBP),%RDX

  (4057) 0x504534 CMP	-0x78(%RBP),%RDX

  (4057) 0x504538 JGE	504c40

  (4057) 0x50453e MOV	0x68(%RBP),%RAX

  (4057) 0x504542 MOV	%R9,(%RAX,%RDX,8)

  (4057) 0x504546 MOV	0x10(%RBP),%RAX

  (4057) 0x50454a VMOVQ	(%RAX,%RSI,8),%XMM0

  (4057) 0x50454f MOV	0x70(%RBP),%RAX

  (4057) 0x504553 VMOVQ	%XMM0,(%RAX,%RDX,8)

  (4057) 0x504558 INC	%RDX

  (4057) 0x50455b MOV	%RDX,-0x70(%RBP)

  (4057) 0x50455f JMP	504400

0x504564 NOPW	%CS:(%RAX,%RAX,1)

0x504573 NOPW	%CS:(%RAX,%RAX,1)

  (4057) 0x504580 MOV	0x78(%RBP),%RAX

  (4057) 0x504584 MOV	(%RAX,%R10,8),%R10

  (4057) 0x504588 MOV	%R8,%R11

  (4057) 0x50458b SUB	%R10,%R11

  (4057) 0x50458e JLE	504690

  (4057) 0x504594 MOV	0x80(%RBP),%RAX

  (4057) 0x50459b LEA	(%RAX,%R10,8),%EAX

  (4057) 0x50459f AND	$0x7f,%EAX

  (4057) 0x5045a2 MOV	$0x80,%EDX

  (4057) 0x5045a7 SUB	%EAX,%EDX

  (4057) 0x5045a9 SHR	$0x3,%EDX

  (4057) 0x5045ac CMP	%RDX,%R11

  (4057) 0x5045af MOV	%RDX,%R8

  (4057) 0x5045b2 CMOVB	%R11,%R8

  (4057) 0x5045b6 TEST	%R8,%R8

  (4057) 0x5045b9 JE	5045e9

  (4057) 0x5045bb MOV	%R10,%R13

  (4057) 0x5045be MOV	%R8,%RAX

  (4057) 0x5045c1 NOPW	%CS:(%RAX,%RAX,1)

    (4060) 0x5045d0 MOV	0x80(%RBP),%R14

    (4060) 0x5045d7 CMP	%R9,(%R14,%R13,8)

    (4060) 0x5045db JE	5047aa

    (4060) 0x5045e1 INC	%R13

    (4060) 0x5045e4 DEC	%RAX

    (4060) 0x5045e7 JNE	5045d0

  (4057) 0x5045e9 CMP	%RDX,%R11

  (4057) 0x5045ec JBE	504690

  (4057) 0x5045f2 MOV	%RSI,-0x38(%RBP)

  (4057) 0x5045f6 SUB	%R8,%R11

  (4057) 0x5045f9 MOV	%R11,%R14

  (4057) 0x5045fc AND	$-0x10,%R14

  (4057) 0x504600 JE	50465a

  (4057) 0x504602 LEA	-0x1(%R14),%RSI

  (4057) 0x504606 LEA	(%R10,%R8,1),%R13

  (4057) 0x50460a VPBROADCASTQ	%R9,%YMM0

  (4057) 0x504610 MOV	0x80(%RBP),%RAX

  (4057) 0x504617 LEA	(%RAX,%R13,8),%RAX

  (4057) 0x50461b XOR	%EDX,%EDX

  (4057) 0x50461d NOPL	(%RAX)

    (4059) 0x504620 VPCMPEQQ	0x20(%RAX,%RDX,8),%YMM0,%K0

    (4059) 0x504628 VPCMPEQQ	(%RAX,%RDX,8),%YMM0,%K1

    (4059) 0x50462f VPCMPEQQ	0x60(%RAX,%RDX,8),%YMM0,%K2

    (4059) 0x504637 VPCMPEQQ	0x40(%RAX,%RDX,8),%YMM0,%K3

    (4059) 0x50463f KORB	%K0,%K1,%K4

    (4059) 0x504643 KORB	%K2,%K3,%K5

    (4059) 0x504647 KORTESTB	%K5,%K4

    (4059) 0x50464b JNE	504780

    (4059) 0x504651 ADD	$0x10,%RDX

    (4059) 0x504655 CMP	%RSI,%RDX

    (4059) 0x504658 JBE	504620

  (4057) 0x50465a CMP	%R11,%R14

  (4057) 0x50465d MOV	-0x38(%RBP),%RSI

  (4057) 0x504661 JAE	504690

  (4057) 0x504663 ADD	%R8,%R10

  (4057) 0x504666 ADD	%R14,%R10

  (4057) 0x504669 MOV	%R10,%R13

  (4057) 0x50466c NOPL	(%RAX)

    (4058) 0x504670 MOV	0x80(%RBP),%RAX

    (4058) 0x504677 CMP	%R9,(%RAX,%R13,8)

    (4058) 0x50467b JE	5047aa

    (4058) 0x504681 INC	%R13

    (4058) 0x504684 CMP	%R13,%RCX

    (4058) 0x504687 JNE	504670

  (4057) 0x504689 NOPL	(%RAX)

  (4057) 0x504690 MOV	-0x80(%RBP),%RDX

  (4057) 0x504694 CMP	-0x98(%RBP),%RDX

  (4057) 0x50469b JGE	504c80

  (4057) 0x5046a1 MOV	0x80(%RBP),%RAX

  (4057) 0x5046a8 MOV	%R9,(%RAX,%RDX,8)

  (4057) 0x5046ac MOV	0x10(%RBP),%RAX

  (4057) 0x5046b0 VMOVQ	(%RAX,%RSI,8),%XMM0

  (4057) 0x5046b5 MOV	0x88(%RBP),%RAX

  (4057) 0x5046bc VMOVQ	%XMM0,(%RAX,%RDX,8)

  (4057) 0x5046c1 INC	%RDX

  (4057) 0x5046c4 MOV	%RDX,-0x80(%RBP)

  (4057) 0x5046c8 JMP	504400

0x5046cd NOPW	%CS:(%RAX,%RAX,1)

0x5046dc NOPW	%CS:(%RAX,%RAX,1)

0x5046eb NOPW	%CS:(%RAX,%RAX,1)

0x5046fa NOPW	(%RAX,%RAX,1)

  (4057) 0x504700 KSHIFTLB	$0x4,%K0,%K0

  (4057) 0x504706 KORB	%K0,%K1,%K0

  (4057) 0x50470a KSHIFTLB	$0x4,%K2,%K1

  (4057) 0x504710 KORB	%K1,%K3,%K1

  (4057) 0x504714 KUNPCKBW	%K0,%K1,%K0

  (4057) 0x504718 KMOVD	%K0,%EAX

  (4057) 0x50471c TZCNT	%EAX,%EAX

  (4057) 0x504720 ADD	%RDX,%R13

  (4057) 0x504723 ADD	%RAX,%R13

  (4057) 0x504726 MOV	-0x38(%RBP),%RSI

  (4057) 0x50472a MOV	-0x30(%RBP),%R10

  (4057) 0x50472e MOV	%RCX,%R8

  (4057) 0x504731 MOV	0x10(%RBP),%RAX

  (4057) 0x504735 VMOVQ	(%RAX,%RSI,8),%XMM0

  (4057) 0x50473a MOV	0x70(%RBP),%RAX

  (4057) 0x50473e VMOVQ	%XMM0,(%RAX,%R13,8)

  (4057) 0x504744 JMP	504407

0x504749 NOPW	%CS:(%RAX,%RAX,1)

0x504758 NOPW	%CS:(%RAX,%RAX,1)

0x504767 NOPW	%CS:(%RAX,%RAX,1)

0x504776 NOPW	%CS:(%RAX,%RAX,1)

  (4057) 0x504780 KSHIFTLB	$0x4,%K0,%K0

  (4057) 0x504786 KORB	%K0,%K1,%K0

  (4057) 0x50478a KSHIFTLB	$0x4,%K2,%K1

  (4057) 0x504790 KORB	%K1,%K3,%K1

  (4057) 0x504794 KUNPCKBW	%K0,%K1,%K0

  (4057) 0x504798 KMOVD	%K0,%EAX

  (4057) 0x50479c TZCNT	%EAX,%EAX

  (4057) 0x5047a0 ADD	%RDX,%R13

  (4057) 0x5047a3 ADD	%RAX,%R13

  (4057) 0x5047a6 MOV	-0x38(%RBP),%RSI

  (4057) 0x5047aa MOV	-0x30(%RBP),%R10

  (4057) 0x5047ae MOV	%RCX,%R8

  (4057) 0x5047b1 MOV	0x10(%RBP),%RAX

  (4057) 0x5047b5 VMOVQ	(%RAX,%RSI,8),%XMM0

  (4057) 0x5047ba MOV	0x88(%RBP),%RAX

  (4057) 0x5047c1 VMOVQ	%XMM0,(%RAX,%R13,8)

  (4057) 0x5047c7 JMP	504407

0x5047cc NOPW	%CS:(%RAX,%RAX,1)

0x5047db NOPW	%CS:(%RAX,%RAX,1)

0x5047ea NOPW	%CS:(%RAX,%RAX,1)

0x5047f9 NOPL	(%RAX)

(4050) 0x504800 MOVQ	$0,-0x78(%RBP)

(4050) 0x504808 MOV	-0x38(%RBP),%RSI

(4050) 0x50480c TEST	%R15,%R15

(4050) 0x50480f JLE	504095

(4050) 0x504815 LEA	-0x1(%R15),%RAX

(4050) 0x504819 MOV	%R13D,%EDX

(4050) 0x50481c AND	$0x7f,%EDX

(4050) 0x50481f MOV	$0x80,%ECX

(4050) 0x504824 SUB	%EDX,%ECX

(4050) 0x504826 SHR	$0x3,%ECX

(4050) 0x504829 CMP	%RCX,%R14

(4050) 0x50482c MOV	%RCX,%RDX

(4050) 0x50482f CMOVB	%R14,%RDX

(4050) 0x504833 MOV	%R14,%RDI

(4050) 0x504836 SUB	%RDX,%RDI

(4050) 0x504839 MOV	%RDI,-0xa0(%RBP)

(4050) 0x504840 AND	$-0x10,%RDI

(4050) 0x504844 LEA	-0x1(%RDI),%R8

(4050) 0x504848 LEA	(%R13,%RDX,8),%R9

(4050) 0x50484d MOV	%RDI,-0x98(%RBP)

(4050) 0x504854 ADD	%RDX,%RDI

(4050) 0x504857 MOV	%RDI,-0xa8(%RBP)

(4050) 0x50485e MOVQ	$0,-0x90(%RBP)

(4050) 0x504869 MOV	%R14,-0x58(%RBP)

(4050) 0x50486d XOR	%R11D,%R11D

(4050) 0x504870 JMP	5048b7

0x504872 NOPW	%CS:(%RAX,%RAX,1)

  (4067) 0x504880 MOV	-0x78(%RBP),%RDI

  (4067) 0x504884 MOV	-0x90(%RBP),%R10

  (4067) 0x50488b MOV	%RSI,(%RDI,%R10,8)

  (4067) 0x50488f MOV	-0x88(%RBP),%RSI

  (4067) 0x504896 VMOVQ	%XMM0,(%RSI,%R10,8)

  (4067) 0x50489c INC	%R10

  (4067) 0x50489f MOV	%R10,-0x90(%RBP)

  (4067) 0x5048a6 CMP	%RAX,%R11

  (4067) 0x5048a9 LEA	0x1(%R11),%R11

  (4067) 0x5048ad MOV	-0x38(%RBP),%RSI

  (4067) 0x5048b1 JE	504a00

  (4067) 0x5048b7 LEA	(%RSI,%R11,1),%R10

  (4067) 0x5048bb TEST	%R14,%R14

  (4067) 0x5048be JLE	504980

  (4067) 0x5048c4 MOV	(%RBX,%R10,8),%RDI

  (4067) 0x5048c8 TEST	%RDX,%RDX

  (4067) 0x5048cb JE	5048e3

  (4067) 0x5048cd XOR	%ESI,%ESI

  (4067) 0x5048cf NOP

    (4070) 0x5048d0 CMP	%RDI,(%R13,%RSI,8)

    (4070) 0x5048d5 JE	5049e6

    (4070) 0x5048db INC	%RSI

    (4070) 0x5048de CMP	%RSI,%RDX

    (4070) 0x5048e1 JNE	5048d0

  (4067) 0x5048e3 CMP	%RCX,%R14

  (4067) 0x5048e6 JBE	504980

  (4067) 0x5048ec CMPQ	$0,-0x98(%RBP)

  (4067) 0x5048f4 JE	50493a

  (4067) 0x5048f6 VPBROADCASTQ	%RDI,%YMM0

  (4067) 0x5048fc XOR	%ESI,%ESI

  (4067) 0x5048fe XCHG	%AX,%AX

    (4069) 0x504900 VPCMPEQQ	0x20(%R9,%RSI,8),%YMM0,%K0

    (4069) 0x504908 VPCMPEQQ	(%R9,%RSI,8),%YMM0,%K1

    (4069) 0x50490f VPCMPEQQ	0x60(%R9,%RSI,8),%YMM0,%K2

    (4069) 0x504917 VPCMPEQQ	0x40(%R9,%RSI,8),%YMM0,%K3

    (4069) 0x50491f KORB	%K0,%K1,%K4

    (4069) 0x504923 KORB	%K2,%K3,%K5

    (4069) 0x504927 KORTESTB	%K5,%K4

    (4069) 0x50492b JNE	5049c0

    (4069) 0x504931 ADD	$0x10,%RSI

    (4069) 0x504935 CMP	%R8,%RSI

    (4069) 0x504938 JBE	504900

  (4067) 0x50493a MOV	-0x98(%RBP),%RSI

  (4067) 0x504941 CMP	-0xa0(%RBP),%RSI

  (4067) 0x504948 JAE	504980

  (4067) 0x50494a MOV	-0xa8(%RBP),%RSI

  (4067) 0x504951 NOPW	%CS:(%RAX,%RAX,1)

    (4068) 0x504960 CMP	%RDI,(%R13,%RSI,8)

    (4068) 0x504965 JE	5049e6

    (4068) 0x50496b INC	%RSI

    (4068) 0x50496e CMP	%RSI,%R14

    (4068) 0x504971 JNE	504960

  (4067) 0x504973 NOPW	%CS:(%RAX,%RAX,1)

  (4067) 0x504980 MOV	(%RBX,%R10,8),%RSI

  (4067) 0x504984 MOV	0x10(%RBP),%RDI

  (4067) 0x504988 VMOVQ	(%RDI,%R10,8),%XMM0

  (4067) 0x50498e MOV	-0x58(%RBP),%RDI

  (4067) 0x504992 CMP	-0x80(%RBP),%RDI

  (4067) 0x504996 JGE	504880

  (4067) 0x50499c MOV	%RSI,(%R13,%RDI,8)

  (4067) 0x5049a1 MOV	-0x70(%RBP),%RSI

  (4067) 0x5049a5 VMOVQ	%XMM0,(%RSI,%RDI,8)

  (4067) 0x5049aa INC	%RDI

  (4067) 0x5049ad MOV	%RDI,-0x58(%RBP)

  (4067) 0x5049b1 JMP	5048a6

0x5049b6 NOPW	%CS:(%RAX,%RAX,1)

  (4067) 0x5049c0 KSHIFTLB	$0x4,%K0,%K0

  (4067) 0x5049c6 KORB	%K0,%K1,%K0

  (4067) 0x5049ca KSHIFTLB	$0x4,%K2,%K1

  (4067) 0x5049d0 KORB	%K1,%K3,%K1

  (4067) 0x5049d4 KUNPCKBW	%K0,%K1,%K0

  (4067) 0x5049d8 KMOVD	%K0,%EDI

  (4067) 0x5049dc TZCNT	%EDI,%EDI

  (4067) 0x5049e0 ADD	%RDX,%RSI

  (4067) 0x5049e3 ADD	%RDI,%RSI

  (4067) 0x5049e6 MOV	0x10(%RBP),%RDI

  (4067) 0x5049ea VMOVQ	(%RDI,%R10,8),%XMM0

  (4067) 0x5049f0 MOV	-0x70(%RBP),%RDI

  (4067) 0x5049f4 VMOVQ	%XMM0,(%RDI,%RSI,8)

  (4067) 0x5049f9 JMP	5048a6

0x5049fe XCHG	%AX,%AX

(4050) 0x504a00 ADD	%R15,%RSI

(4050) 0x504a03 MOV	-0x90(%RBP),%RDX

(4050) 0x504a0a MOV	-0x58(%RBP),%RAX

(4050) 0x504a0e LEA	(%RAX,%RDX,1),%R14

(4050) 0x504a12 MOV	0x48(%RBP),%RAX

(4050) 0x504a16 MOV	-0x30(%RBP),%RCX

(4050) 0x504a1a MOV	%R14,(%RAX,%RCX,8)

(4050) 0x504a1e TEST	%RDX,%RDX

(4050) 0x504a21 MOV	%RSI,-0x38(%RBP)

(4050) 0x504a25 JE	504b40

(4050) 0x504a2b MOV	0x38(%RBP),%R13

(4050) 0x504a2f MOV	(%R13,%RCX,8),%RDI

(4050) 0x504a34 LEA	(,%R14,8),%R15

(4050) 0x504a3c MOV	%R15,%RSI

(4050) 0x504a3f VZEROUPPER

(4050) 0x504a42 CALL	51b900 <hypre_ReAlloc>

(4050) 0x504a47 MOV	-0x30(%RBP),%RCX

(4050) 0x504a4b MOV	%RAX,(%R13,%RCX,8)

(4050) 0x504a50 MOV	0x40(%RBP),%R13

(4050) 0x504a54 MOV	-0x30(%RBP),%RAX

(4050) 0x504a58 MOV	(%R13,%RAX,8),%RDI

(4050) 0x504a5d MOV	%R15,%RSI

(4050) 0x504a60 CALL	51b900 <hypre_ReAlloc>

(4050) 0x504a65 MOV	-0x90(%RBP),%RDX

(4050) 0x504a6c MOV	-0x30(%RBP),%RSI

(4050) 0x504a70 MOV	%RAX,(%R13,%RSI,8)

(4050) 0x504a75 MOV	0x50(%RBP),%RCX

(4050) 0x504a79 MOV	%R14,(%RCX,%RSI,8)

(4050) 0x504a7d TEST	%RDX,%RDX

(4050) 0x504a80 JLE	504b40

(4050) 0x504a86 MOV	0x38(%RBP),%RCX

(4050) 0x504a8a MOV	(%RCX,%RSI,8),%RCX

(4050) 0x504a8e MOV	-0x78(%RBP),%R13

(4050) 0x504a92 LEA	-0x8(%R13,%RDX,8),%RSI

(4050) 0x504a97 MOV	-0x58(%RBP),%R10

(4050) 0x504a9b LEA	(%RCX,%R10,8),%RDI

(4050) 0x504a9f CMP	%RDI,%RSI

(4050) 0x504aa2 SETAE	%R9B

(4050) 0x504aa6 LEA	-0x1(%RDX,%R10,1),%RSI

(4050) 0x504aab LEA	(%RCX,%RSI,8),%RCX

(4050) 0x504aaf CMP	%R13,%RCX

(4050) 0x504ab2 SETAE	%R8B

(4050) 0x504ab6 MOV	-0x88(%RBP),%R14

(4050) 0x504abd LEA	-0x8(%R14,%RDX,8),%RCX

(4050) 0x504ac2 LEA	(%RAX,%R10,8),%R15

(4050) 0x504ac6 CMP	%R15,%RCX

(4050) 0x504ac9 SETB	%CL

(4050) 0x504acc LEA	(%RAX,%RSI,8),%RAX

(4050) 0x504ad0 CMP	%R14,%RAX

(4050) 0x504ad3 SETB	%AL

(4050) 0x504ad6 TEST	%R8B,%R9B

(4050) 0x504ad9 JNE	504c00

(4050) 0x504adf OR	%AL,%CL

(4050) 0x504ae1 JE	504c00

(4050) 0x504ae7 CMP	$0xd,%RDX

(4050) 0x504aeb JAE	503f80

(4050) 0x504af1 MOV	%RDX,%RAX

(4050) 0x504af4 AND	$-0x4,%RAX

(4050) 0x504af8 JE	504d00

(4050) 0x504afe LEA	-0x1(%RAX),%RCX

(4050) 0x504b02 XOR	%ESI,%ESI

(4050) 0x504b04 NOPW	%CS:(%RAX,%RAX,1)

  (4066) 0x504b10 VMOVUPS	(%R13,%RSI,8),%YMM0

  (4066) 0x504b17 VMOVUPS	%YMM0,(%RDI,%RSI,8)

  (4066) 0x504b1c VMOVDQU	(%R14,%RSI,8),%YMM0

  (4066) 0x504b22 VMOVDQU	%YMM0,(%R15,%RSI,8)

  (4066) 0x504b28 ADD	$0x4,%RSI

  (4066) 0x504b2c CMP	%RCX,%RSI

  (4066) 0x504b2f JLE	504b10

(4050) 0x504b31 JMP	504d40

0x504b36 NOPW	%CS:(%RAX,%RAX,1)

(4050) 0x504b40 MOV	-0x78(%RBP),%R13

(4050) 0x504b44 TEST	%R13,%R13

(4050) 0x504b47 JNE	503fa8

(4050) 0x504b4d JMP	503fca

0x504b52 NOPW	%CS:(%RAX,%RAX,1)

0x504b61 NOPW	%CS:(%RAX,%RAX,1)

0x504b70 NOPW	%CS:(%RAX,%RAX,1)

0x504b7f NOP

(4050) 0x504b80 MOV	%R8,%RDI

(4050) 0x504b83 MOV	-0x48(%RBP),%RCX

(4050) 0x504b87 JMP	504ce1

0x504b8c NOPW	%CS:(%RAX,%RAX,1)

0x504b9b NOPW	%CS:(%RAX,%RAX,1)

0x504baa NOPW	%CS:(%RAX,%RAX,1)

0x504bb9 NOPL	(%RAX)

(4050) 0x504bc0 MOV	-0xa0(%RBP),%RAX

(4050) 0x504bc7 MOV	%RAX,-0x38(%RBP)

(4050) 0x504bcb MOV	-0x60(%RBP),%RDX

(4050) 0x504bcf MOV	-0x50(%RBP),%RSI

(4050) 0x504bd3 MOV	-0x68(%RBP),%R9

(4050) 0x504bd7 MOV	-0x48(%RBP),%RCX

(4050) 0x504bdb JMP	504cd9

0x504be0 NOPW	%CS:(%RAX,%RAX,1)

0x504bef NOPW	%CS:(%RAX,%RAX,1)

0x504bfe XCHG	%AX,%AX

(4050) 0x504c00 XOR	%EAX,%EAX

(4050) 0x504c02 NOPW	%CS:(%RAX,%RAX,1)

  (4064) 0x504c10 MOV	(%R13,%RAX,8),%RCX

  (4064) 0x504c15 MOV	%RCX,(%RDI,%RAX,8)

  (4064) 0x504c19 VMOVQ	(%R14,%RAX,8),%XMM0

  (4064) 0x504c1f VMOVQ	%XMM0,(%R15,%RAX,8)

  (4064) 0x504c25 INC	%RAX

  (4064) 0x504c28 CMP	%RAX,%RDX

  (4064) 0x504c2b JNE	504c10

(4050) 0x504c2d JMP	503fa8

0x504c32 NOPW	%CS:(%RAX,%RAX,1)

(4050) 0x504c40 MOV	%RSI,-0x38(%RBP)

(4050) 0x504c44 MOV	-0x58(%RBP),%R14

(4050) 0x504c48 MOV	$0x53bd2f,%EDI

(4050) 0x504c4d MOV	$0xd70,%ESI

(4050) 0x504c52 MOV	$0x1,%EDX

(4050) 0x504c57 XOR	%ECX,%ECX

(4050) 0x504c59 VZEROUPPER

(4050) 0x504c5c CALL	51ec00 <hypre_error_handler>

(4050) 0x504c61 MOV	0xd0(%RBP),%RAX

(4050) 0x504c68 LOCK INCQ	(%RAX)

(4050) 0x504c6c MOV	$0x53bea8,%EDI

(4050) 0x504c71 CMPQ	$0,0xc0(%RBP)

(4050) 0x504c79 JNE	504cbb

(4050) 0x504c7b JMP	504cc5

0x504c7d NOPL	(%RAX)

(4050) 0x504c80 MOV	%RSI,-0x38(%RBP)

(4050) 0x504c84 MOV	-0x58(%RBP),%R14

(4050) 0x504c88 MOV	$0x53bd2f,%EDI

(4050) 0x504c8d MOV	$0xd4e,%ESI

(4050) 0x504c92 MOV	$0x1,%EDX

(4050) 0x504c97 XOR	%ECX,%ECX

(4050) 0x504c99 VZEROUPPER

(4050) 0x504c9c CALL	51ec00 <hypre_error_handler>

(4050) 0x504ca1 MOV	0xd0(%RBP),%RAX

(4050) 0x504ca8 LOCK INCQ	(%RAX)

(4050) 0x504cac MOV	$0x53be82,%EDI

(4050) 0x504cb1 CMPQ	$0,0xc0(%RBP)

(4050) 0x504cb9 JE	504cc5

(4050) 0x504cbb MOV	%R14,%RSI

(4050) 0x504cbe XOR	%EAX,%EAX

(4050) 0x504cc0 CALL	51bb20 <hypre_printf>

(4050) 0x504cc5 MOV	-0x60(%RBP),%RDX

(4050) 0x504cc9 MOV	-0x50(%RBP),%RSI

(4050) 0x504ccd MOV	-0x68(%RBP),%R9

(4050) 0x504cd1 MOV	-0x48(%RBP),%RCX

(4050) 0x504cd5 MOV	-0x30(%RBP),%R10

(4050) 0x504cd9 MOV	-0x80(%RBP),%RDI

(4050) 0x504cdd MOV	-0x70(%RBP),%R11

(4050) 0x504ce1 MOV	0x18(%RBP),%R8

(4050) 0x504ce5 MOV	0x38(%R8),%RAX

(4050) 0x504ce9 MOV	%R11,(%RAX,%R10,8)

(4050) 0x504ced MOV	0x40(%R8),%RAX

(4050) 0x504cf1 MOV	%RDI,(%RAX,%R10,8)

(4050) 0x504cf5 JMP	503fda

0x504cfa NOPW	(%RAX,%RAX,1)

(4050) 0x504d00 XOR	%EAX,%EAX

(4050) 0x504d02 JMP	504d49

0x504d04 NOPW	%CS:(%RAX,%RAX,1)

0x504d13 NOPW	%CS:(%RAX,%RAX,1)

0x504d22 NOPW	%CS:(%RAX,%RAX,1)

0x504d31 NOPW	%CS:(%RAX,%RAX,1)

  (4065) 0x504d40 CMP	%RAX,%RDX

  (4065) 0x504d43 JE	503fa8

  (4065) 0x504d49 MOV	(%R13,%RAX,8),%RCX

  (4065) 0x504d4e MOV	%RCX,(%RDI,%RAX,8)

  (4065) 0x504d52 VMOVQ	(%R14,%RAX,8),%XMM0

  (4065) 0x504d58 VMOVQ	%XMM0,(%R15,%RAX,8)

  (4065) 0x504d5e INC	%RAX

  (4065) 0x504d61 JMP	504d40

0x504d63 NOPW	%CS:(%RAX,%RAX,1)

0x504d72 NOPW	%CS:(%RAX,%RAX,1)

0x504d80 ADD	$0x98,%RSP

0x504d87 POP	%RBX

0x504d88 POP	%R12

0x504d8a POP	%R13

0x504d8c POP	%R14

0x504d8e POP	%R15

0x504d90 POP	%RBP

0x504d91 VZEROUPPER

0x504d94 RET

0x504d95 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_4

Source file and lines	IJMatrix_parcsr.c:3240-3484
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3240,3256-3283,3289-3322,3329-3337,3344-3353,3359-3368,3376-3392,3399-3410,3422-3426,3433-3445,3454-3458,3466-3484.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 40.67 to 6.00 cycles (6.78x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

11% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
33% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
16% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_barrier@plt: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3275
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3282
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3257
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3256

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3259
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3259
VZEROUPPER: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3275
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3359

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3259

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 168 bytes. The binary function is storing 81 bytes.

General properties

nb instructions	231
nb uops	244
loop length	1557
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	0
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	40.67 cycles
front end	40.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	12.20	12.20	9.67	9.67	10.50	12.20	12.20	10.50	10.50	10.50	12.20	9.67
cycles	12.20	16.20	9.67	9.67	10.50	12.20	12.20	10.50	10.50	10.50	12.20	9.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

16.00

Cycles summary

Front-end	40.67
Dispatch	16.20
DIV/SQRT	16.00
Overall L1	40.67

Vectorization ratios

all	11%
load	0%
store	0%
mul	0%
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	16%

Vector efficiency ratios

all	12%
load	11%
store	10%
mul	12%
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	9%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 40.67 cycles. At this rate:

2% of peak load performance is reached (4.13 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.99 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 40.67 to 16.20 cycles (2.51x speedup).

ASM code

In the binary file, the address of the function is: 503c60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x98,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 51da50 <hypre_NumActiveThreads>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 51da60 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR %R15,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x20,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JE 503cc0 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x60>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %R13	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
JMP 503cc8 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x68>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %R12,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xb8(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%R14),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RDX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 503d00 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0xa0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%RAX),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
IMUL %R14,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
IMUL %RCX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 503d11 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0xb1>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
IMUL %R14,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVQ $0,(%R15,%R14,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RCX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 503df0 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x190>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %RDX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVL %R14,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IMUL %R14,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x48(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
SUB %RDX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
SUB %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 503dc0 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x160>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RCX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x50(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R8,%R12,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VEXTRACTI128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VPSHUFD $-0x12,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVQ %XMM0,%RSI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
CMP %RCX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x50(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x48(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 503dcc <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x16c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 503dec <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x18c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV -0x50(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x48(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,(%R15,%R14,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%R13),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x560570,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 410570 <__kmpc_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %R14,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 503ea4 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x244>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0xc8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 503ea4 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x244>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 503e77 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x217>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV (%R15),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x40(%R15),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 503ea4 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x244>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R15,%RCX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R13),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x560590,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 410570 <__kmpc_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %R14,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 503f00 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x2a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x8(%R15,%R14,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 503f08 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x2a8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV -0x60(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x50(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R12,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 504d80 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x1120>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xa8(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x98(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
SETE %CL	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
LEA (%RAX,%R14,8),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %RDI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
SETLE %AL	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
OR %CL,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %AL,-0x39(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	N/A
MOV -0x48(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DEC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x1,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %RDI,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x18,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JMP 503fea <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x38a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x98,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_4

Source file and lines	IJMatrix_parcsr.c:3240-3484
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 40.67 to 6.00 cycles (6.78x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

11% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
33% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
16% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

__kmpc_barrier@plt: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3275
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3282
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3257
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3256

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3259
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3259
VZEROUPPER: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3275
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3359

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3259

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 168 bytes. The binary function is storing 81 bytes.

General properties

nb instructions	231
nb uops	244
loop length	1557
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	0
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	40.67 cycles
front end	40.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	12.20	12.20	9.67	9.67	10.50	12.20	12.20	10.50	10.50	10.50	12.20	9.67
cycles	12.20	16.20	9.67	9.67	10.50	12.20	12.20	10.50	10.50	10.50	12.20	9.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

16.00

Cycles summary

Front-end	40.67
Dispatch	16.20
DIV/SQRT	16.00
Overall L1	40.67

Vectorization ratios

all	11%
load	0%
store	0%
mul	0%
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	16%

Vector efficiency ratios

all	12%
load	11%
store	10%
mul	12%
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	9%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 40.67 cycles. At this rate:

2% of peak load performance is reached (4.13 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.99 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 503c60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x98,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 51da50 <hypre_NumActiveThreads>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 51da60 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR %R15,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x20,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JE 503cc0 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x60>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %R13	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
JMP 503cc8 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x68>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
DIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %R12,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xb8(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%R14),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RDX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 503d00 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0xa0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%RAX),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
IMUL %R14,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
IMUL %RCX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 503d11 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0xb1>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
IMUL %R14,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVQ $0,(%R15,%R14,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RCX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 503df0 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x190>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %RDX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVL %R14,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IMUL %R14,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x48(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
SUB %RDX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
SUB %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 503dc0 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x160>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RCX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x50(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R8,%R12,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VEXTRACTI128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VPSHUFD $-0x12,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVQ %XMM0,%RSI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
CMP %RCX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x50(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x48(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 503dcc <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x16c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 503dec <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x18c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV -0x50(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x48(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,(%R15,%R14,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%R13),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x560570,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 410570 <__kmpc_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %R14,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 503ea4 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x244>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0xc8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 503ea4 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x244>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 503e77 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x217>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV (%R15),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x40(%R15),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 503ea4 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x244>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R15,%RCX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R13),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x560590,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 410570 <__kmpc_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %R14,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 503f00 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x2a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x8(%R15,%R14,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 503f08 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x2a8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV -0x60(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x50(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R12,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 504d80 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x1120>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xa8(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x98(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
SETE %CL	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
LEA (%RAX,%R14,8),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %RDI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
SETLE %AL	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
OR %CL,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %AL,-0x39(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	N/A
MOV -0x48(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DEC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x1,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %RDI,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x18,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JMP 503fea <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x38a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x98,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼hypre_IJMatrixSetValuesOMPParCSR.extracted.28–	1.17	0.62
▼Loop 4050 - IJMatrix_parcsr.c:3262-3484 - exec–	0.10	0.04
▼Loop 4057 - IJMatrix_parcsr.c:3262-3454 - exec–	1.06	0.45
○Loop 4062 - IJMatrix_parcsr.c:3422-3424 - exec	0.00	0.00
○Loop 4059 - IJMatrix_parcsr.c:3388-3424 - exec	0.00	0.00
○Loop 4060 - IJMatrix_parcsr.c:3388-3390 - exec	0.00	0.00
○Loop 4063 - IJMatrix_parcsr.c:3422-3424 - exec	0.00	0.00
○Loop 4058 - IJMatrix_parcsr.c:3388-3390 - exec	0.00	0.00
○Loop 4061 - IJMatrix_parcsr.c:3422-3424 - exec	0.00	0.00
○Loop 4066 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
▼Loop 4051 - IJMatrix_parcsr.c:3262-3484 - exec–	0.00	0.00
▼Loop 4055 - IJMatrix_parcsr.c:3475-3484 - exec–	0.00	0.00
○Loop 4056 - IJMatrix_parcsr.c:3478-3484 - exec	0.00	0.00
▼Loop 4052 - IJMatrix_parcsr.c:3473-3484 - exec–	0.00	0.00
○Loop 4053 - IJMatrix_parcsr.c:3478-3484 - exec	0.00	0.00
○Loop 4054 - IJMatrix_parcsr.c:3478-3484 - exec	0.00	0.00
▼Loop 4067 - IJMatrix_parcsr.c:3262-3337 - exec–	0.00	0.00
○Loop 4070 - IJMatrix_parcsr.c:3318-3320 - exec	0.00	0.00
○Loop 4069 - IJMatrix_parcsr.c:3318-3320 - exec	0.00	0.00
○Loop 4068 - IJMatrix_parcsr.c:3318-3320 - exec	0.00	0.00
○Loop 4064 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
○Loop 4065 - IJMatrix_parcsr.c:3359-3458 - exec	0.00	0.00
○Loop 4074 - IJMatrix_parcsr.c:3274-3275 - exec	0.01	0.00
○Loop 4072 - IJMatrix_parcsr.c:3282-3283 - exec	0.00	0.00
○Loop 4071 - IJMatrix_parcsr.c:3282-3283 - exec	0.00	0.00
○Loop 4073 - IJMatrix_parcsr.c:3274-3275 - exec	0.00	0.00

Report Configuration

Code clean check

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Execution units bottlenecks

512-bits vectorization

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CALL instructions

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Complex instructions

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Conversion instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code