OV - exec - Function hypre_IJMatrixAssembleParCSR.extracted.25

	Function: hypre_IJMatrixAssembleParCSR.extracted.25	Module: exec	Source: IJMatrix_parcsr.c:2798-2812	Coverage (incl. loops): 0.59% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 2798 - 2812

--------------------------------------------------------------------------------

2798: #pragma omp parallel for private (i,j,j0,temp)

2799: #endif

2800:          for (i=0; i < num_rows; i++)

2801:          {

2802:    	    j0 = diag_i[i];

2803:    	    for (j=j0; j < diag_i[i+1]; j++)

2804:    	    {

2805:    	       diag_j[j] -= col_0;

2806:    	       if (diag_j[j] == i)

2807:    	       {

2808:    	          temp = diag_data[j0];

2809:    	          diag_data[j0] = diag_data[j];

2810:    	          diag_data[j] = temp;

2811:    	          diag_j[j] = diag_j[j0];

2812:    	          diag_j[j0] = i;

0x502a50 PUSH	%RBP

0x502a51 MOV	%RSP,%RBP

0x502a54 PUSH	%R15

0x502a56 PUSH	%R14

0x502a58 PUSH	%R13

0x502a5a PUSH	%R12

0x502a5c PUSH	%RBX

0x502a5d SUB	$0x18,%RSP

0x502a61 MOVL	$0,-0x2c(%RBP)

0x502a68 MOV	%R9,%R14

0x502a6b MOV	%R8,%R15

0x502a6e MOV	%RCX,%R12

0x502a71 MOV	%RDX,%R13

0x502a74 MOV	(%RDI),%EBX

0x502a76 MOVQ	$0,-0x38(%RBP)

0x502a7e MOVQ	$0x1,-0x40(%RBP)

0x502a86 SUB	$0x8,%RSP

0x502a8a LEA	-0x40(%RBP),%RAX

0x502a8e LEA	-0x2c(%RBP),%RCX

0x502a92 LEA	-0x38(%RBP),%R8

0x502a96 LEA	0x18(%RBP),%R9

0x502a9a MOV	$0x5607b0,%EDI

0x502a9f MOV	%EBX,%ESI

0x502aa1 MOV	$0x22,%EDX

0x502aa6 PUSH	$0x1

0x502aa8 PUSH	$0x1

0x502aaa PUSH	%RAX

0x502aab CALL	410430 <__kmpc_for_static_init_8@plt>

0x502ab0 ADD	$0x20,%RSP

0x502ab4 MOV	-0x38(%RBP),%RSI

0x502ab8 MOV	0x18(%RBP),%RAX

0x502abc CMP	%RAX,%RSI

0x502abf JA	502c08

0x502ac5 MOV	(%R13,%RSI,8),%RDX

0x502aca MOV	%EAX,%ECX

0x502acc SUB	%ESI,%ECX

0x502ace INC	%ECX

0x502ad0 TEST	$0x1,%CL

0x502ad3 JNE	502b00

0x502ad5 MOV	%RSI,%RCX

0x502ad8 CMP	%RSI,%RAX

0x502adb JNE	502c45

0x502ae1 JMP	502c08

0x502ae6 NOPW	%CS:(%RAX,%RAX,1)

0x502af5 NOPW	%CS:(%RAX,%RAX,1)

0x502b00 LEA	0x1(%RSI),%RCX

0x502b04 MOV	0x8(%R13,%RSI,8),%RDI

0x502b09 CMP	%RDI,%RDX

0x502b0c JGE	502bc0

0x502b12 MOV	%RDX,%RDI

0x502b15 JMP	502b51

0x502b17 NOPW	%CS:(%RAX,%RAX,1)

0x502b26 NOPW	%CS:(%RAX,%RAX,1)

0x502b35 NOPW	%CS:(%RAX,%RAX,1)

(4031) 0x502b40 INC	%RDI

(4031) 0x502b43 MOV	0x8(%R13,%RSI,8),%R8

(4031) 0x502b48 CMP	%R8,%RDI

(4031) 0x502b4b JGE	502c00

(4031) 0x502b51 MOV	(%R12,%RDI,8),%R8

(4031) 0x502b55 SUB	%R14,%R8

(4031) 0x502b58 MOV	%R8,(%R12,%RDI,8)

(4031) 0x502b5c CMP	%RSI,%R8

(4031) 0x502b5f JNE	502b40

(4031) 0x502b61 VMOVSD	(%R15,%RDX,8),%XMM0

(4031) 0x502b67 VMOVSD	(%R15,%RDI,8),%XMM1

(4031) 0x502b6d VMOVSD	%XMM1,(%R15,%RDX,8)

(4031) 0x502b73 VMOVSD	%XMM0,(%R15,%RDI,8)

(4031) 0x502b79 MOV	(%R12,%RDX,8),%R8

(4031) 0x502b7d MOV	%R8,(%R12,%RDI,8)

(4031) 0x502b81 MOV	%RSI,(%R12,%RDX,8)

(4031) 0x502b85 JMP	502b40

0x502b87 NOPW	%CS:(%RAX,%RAX,1)

0x502b96 NOPW	%CS:(%RAX,%RAX,1)

0x502ba5 NOPW	%CS:(%RAX,%RAX,1)

0x502bb4 NOPW	%CS:(%RAX,%RAX,1)

0x502bc0 MOV	%RDI,%RDX

0x502bc3 CMP	%RSI,%RAX

0x502bc6 JNE	502c45

0x502bc8 JMP	502c08

0x502bca NOPW	%CS:(%RAX,%RAX,1)

0x502bd9 NOPW	%CS:(%RAX,%RAX,1)

0x502be8 NOPW	%CS:(%RAX,%RAX,1)

0x502bf7 NOPW	(%RAX,%RAX,1)

0x502c00 MOV	%R8,%RDX

0x502c03 CMP	%RSI,%RAX

0x502c06 JNE	502c45

0x502c08 MOV	$0x5607d0,%EDI

0x502c0d MOV	%EBX,%ESI

0x502c0f ADD	$0x18,%RSP

0x502c13 POP	%RBX

0x502c14 POP	%R12

0x502c16 POP	%R13

0x502c18 POP	%R14

0x502c1a POP	%R15

0x502c1c POP	%RBP

0x502c1d JMP	410180

0x502c22 NOPW	%CS:(%RAX,%RAX,1)

0x502c31 NOPW	%CS:(%RAX,%RAX,1)

(4028) 0x502c40 CMP	%RAX,%RDI

(4028) 0x502c43 JE	502c08

(4028) 0x502c45 MOV	0x8(%R13,%RCX,8),%RSI

(4028) 0x502c4a CMP	%RSI,%RDX

(4028) 0x502c4d JGE	502d00

(4028) 0x502c53 MOV	%RDX,%RDI

(4028) 0x502c56 JMP	502c8d

0x502c58 NOPW	%CS:(%RAX,%RAX,1)

0x502c67 NOPW	%CS:(%RAX,%RAX,1)

0x502c76 NOPW	%CS:(%RAX,%RAX,1)

  (4030) 0x502c80 INC	%RDI

  (4030) 0x502c83 MOV	0x8(%R13,%RCX,8),%RSI

  (4030) 0x502c88 CMP	%RSI,%RDI

  (4030) 0x502c8b JGE	502d00

  (4030) 0x502c8d MOV	(%R12,%RDI,8),%RSI

  (4030) 0x502c91 SUB	%R14,%RSI

  (4030) 0x502c94 MOV	%RSI,(%R12,%RDI,8)

  (4030) 0x502c98 CMP	%RCX,%RSI

  (4030) 0x502c9b JNE	502c80

  (4030) 0x502c9d VMOVSD	(%R15,%RDX,8),%XMM0

  (4030) 0x502ca3 VMOVSD	(%R15,%RDI,8),%XMM1

  (4030) 0x502ca9 VMOVSD	%XMM1,(%R15,%RDX,8)

  (4030) 0x502caf VMOVSD	%XMM0,(%R15,%RDI,8)

  (4030) 0x502cb5 MOV	(%R12,%RDX,8),%RSI

  (4030) 0x502cb9 MOV	%RSI,(%R12,%RDI,8)

  (4030) 0x502cbd MOV	%RCX,(%R12,%RDX,8)

  (4030) 0x502cc1 JMP	502c80

0x502cc3 NOPW	%CS:(%RAX,%RAX,1)

0x502cd2 NOPW	%CS:(%RAX,%RAX,1)

0x502ce1 NOPW	%CS:(%RAX,%RAX,1)

0x502cf0 NOPW	%CS:(%RAX,%RAX,1)

0x502cff NOP

(4028) 0x502d00 MOV	0x10(%R13,%RCX,8),%RDX

(4028) 0x502d05 LEA	0x1(%RCX),%RDI

(4028) 0x502d09 ADD	$0x2,%RCX

(4028) 0x502d0d CMP	%RDX,%RSI

(4028) 0x502d10 JGE	502c40

(4028) 0x502d16 MOV	%RSI,%R8

(4028) 0x502d19 JMP	502d51

0x502d1b NOPW	%CS:(%RAX,%RAX,1)

0x502d2a NOPW	%CS:(%RAX,%RAX,1)

0x502d39 NOPL	(%RAX)

  (4029) 0x502d40 INC	%R8

  (4029) 0x502d43 MOV	(%R13,%RCX,8),%RDX

  (4029) 0x502d48 CMP	%RDX,%R8

  (4029) 0x502d4b JGE	502c40

  (4029) 0x502d51 MOV	(%R12,%R8,8),%RDX

  (4029) 0x502d55 SUB	%R14,%RDX

  (4029) 0x502d58 MOV	%RDX,(%R12,%R8,8)

  (4029) 0x502d5c CMP	%RDI,%RDX

  (4029) 0x502d5f JNE	502d40

  (4029) 0x502d61 VMOVSD	(%R15,%RSI,8),%XMM0

  (4029) 0x502d67 VMOVSD	(%R15,%R8,8),%XMM1

  (4029) 0x502d6d VMOVSD	%XMM1,(%R15,%RSI,8)

  (4029) 0x502d73 VMOVSD	%XMM0,(%R15,%R8,8)

  (4029) 0x502d79 MOV	(%R12,%RSI,8),%RDX

  (4029) 0x502d7d MOV	%RDX,(%R12,%R8,8)

  (4029) 0x502d81 MOV	%RDI,(%R12,%RSI,8)

  (4029) 0x502d85 JMP	502d40

0x502d87 NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_4

Source file and lines	IJMatrix_parcsr.c:2798-2812
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2798-2812.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 15.67 to 1.04 cycles (15.03x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2798

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	93
nb uops	94
loop length	572
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.67 cycles
front end	15.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.40	3.40	3.67	3.67	6.50	3.40	3.40	6.50	6.50	6.50	3.40	3.67
cycles	3.40	3.40	3.67	3.67	6.50	3.40	3.40	6.50	6.50	6.50	3.40	3.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.67
Dispatch	6.50
Overall L1	15.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	9%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.67 cycles. At this rate:

1% of peak load performance is reached (2.30 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.28 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 15.67 to 6.50 cycles (2.41x speedup).

ASM code

In the binary file, the address of the function is: 502a50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVL $0,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x1,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2c(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x38(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x18(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x5607b0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 410430 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 502c08 <hypre_IJMatrixAssembleParCSR.extracted.25+0x1b8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R13,%RSI,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %ESI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
TEST $0x1,%CL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 502b00 <hypre_IJMatrixAssembleParCSR.extracted.25+0xb0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 502c45 <hypre_IJMatrixAssembleParCSR.extracted.25+0x1f5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 502c08 <hypre_IJMatrixAssembleParCSR.extracted.25+0x1b8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x1(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x8(%R13,%RSI,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 502bc0 <hypre_IJMatrixAssembleParCSR.extracted.25+0x170>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 502b51 <hypre_IJMatrixAssembleParCSR.extracted.25+0x101>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 502c45 <hypre_IJMatrixAssembleParCSR.extracted.25+0x1f5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 502c08 <hypre_IJMatrixAssembleParCSR.extracted.25+0x1b8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 502c45 <hypre_IJMatrixAssembleParCSR.extracted.25+0x1f5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x5607d0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 410180 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_4

Source file and lines	IJMatrix_parcsr.c:2798-2812
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2798-2812.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2798

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	93
nb uops	94
loop length	572
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.67 cycles
front end	15.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.40	3.40	3.67	3.67	6.50	3.40	3.40	6.50	6.50	6.50	3.40	3.67
cycles	3.40	3.40	3.67	3.67	6.50	3.40	3.40	6.50	6.50	6.50	3.40	3.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.67
Dispatch	6.50
Overall L1	15.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	9%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.67 cycles. At this rate:

1% of peak load performance is reached (2.30 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.28 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 502a50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVL $0,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x1,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2c(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x38(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x18(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x5607b0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 410430 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 502c08 <hypre_IJMatrixAssembleParCSR.extracted.25+0x1b8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R13,%RSI,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %ESI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
TEST $0x1,%CL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 502b00 <hypre_IJMatrixAssembleParCSR.extracted.25+0xb0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 502c45 <hypre_IJMatrixAssembleParCSR.extracted.25+0x1f5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 502c08 <hypre_IJMatrixAssembleParCSR.extracted.25+0x1b8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x1(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x8(%R13,%RSI,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 502bc0 <hypre_IJMatrixAssembleParCSR.extracted.25+0x170>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 502b51 <hypre_IJMatrixAssembleParCSR.extracted.25+0x101>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 502c45 <hypre_IJMatrixAssembleParCSR.extracted.25+0x1f5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 502c08 <hypre_IJMatrixAssembleParCSR.extracted.25+0x1b8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 502c45 <hypre_IJMatrixAssembleParCSR.extracted.25+0x1f5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x5607d0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 410180 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼hypre_IJMatrixAssembleParCSR.extracted.25–	0.59	0.31
▼Loop 4028 - IJMatrix_parcsr.c:2798-2812 - exec–	0.00	0.01
○Loop 4029 - IJMatrix_parcsr.c:2803-2812 - exec	0.30	0.13
○Loop 4030 - IJMatrix_parcsr.c:2803-2812 - exec	0.29	0.12
○Loop 4031 - IJMatrix_parcsr.c:2803-2812 - exec	0.00	0.00

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Vectorization

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Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code