OV - exec - Function hypre_ParMatmul.extracted.12

	Function: hypre_ParMatmul.extracted.12	Module: exec	Source: par_csr_matop.c:829-995 [...]	Coverage (incl. loops): 1.15% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 829 - 995

--------------------------------------------------------------------------------

829: #pragma omp parallel

[...]

840:     ii = hypre_GetThreadNum();

841:     num_threads = hypre_NumActiveThreads();

842:     size = num_rows_diag_A/num_threads;

843:     rest = num_rows_diag_A - size*num_threads;

844:     if (ii < rest)

845:     {

846:        ns = ii*size+ii;

847:        ne = (ii+1)*size+ii+1;

848:     }

849:     else

850:     {

851:        ns = ii*size+rest;

852:        ne = (ii+1)*size+rest;

853:     }

854:     jj_count_diag = C_diag_i[ns];

855:     jj_count_offd = C_offd_i[ns];

856:     if (num_cols_diag_B || num_cols_offd_C)

857:     B_marker = hypre_CTAlloc(HYPRE_Int, num_cols_diag_B+num_cols_offd_C);

858:     for (i1 = 0; i1 < num_cols_diag_B+num_cols_offd_C; i1++)

859:       B_marker[i1] = -1;

[...]

865:     for (i1 = ns; i1 < ne; i1++)

[...]

874:       if ( allsquare )

875:       {

876:          B_marker[i1] = jj_count_diag;

877:          C_diag_data[jj_count_diag] = zero;

878:          C_diag_j[jj_count_diag] = i1;

879:          jj_count_diag++;

[...]

886:       if (num_cols_offd_A)

887:       {

888:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

889:          {

890:             i2 = A_offd_j[jj2];

891:             a_entry = A_offd_data[jj2];

[...]

897:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

898:             {

899:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

907:                if (B_marker[i3] < jj_row_begin_offd)

908:                {

909:                   B_marker[i3] = jj_count_offd;

910:                   C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3];

911:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

912:                   jj_count_offd++;

913:                }

914:                else

915:                   C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3];

916:             }

917:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

918:             {

919:                i3 = B_ext_diag_j[jj3];

920:                if (B_marker[i3] < jj_row_begin_diag)

921:                {

922:                   B_marker[i3] = jj_count_diag;

923:                   C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3];

924:                   C_diag_j[jj_count_diag] = i3;

925:                   jj_count_diag++;

926:                }

927:                else

928:                   C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3];

[...]

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

971:             {

972:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

980:                if (B_marker[i3] < jj_row_begin_offd)

981:                {

982:                   B_marker[i3] = jj_count_offd;

983:                   C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3];

984:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

985:                   jj_count_offd++;

986:                }

987:                else

988:                {

989:                   C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3];

[...]

995:     hypre_TFree(B_marker);

0x4e7380 PUSH	%RBP

0x4e7381 MOV	%RSP,%RBP

0x4e7384 PUSH	%R15

0x4e7386 PUSH	%R14

0x4e7388 PUSH	%R13

0x4e738a PUSH	%R12

0x4e738c PUSH	%RBX

0x4e738d SUB	$0xe8,%RSP

0x4e7394 MOV	%R9,-0xa8(%RBP)

0x4e739b MOV	%R8,-0xc8(%RBP)

0x4e73a2 MOV	%RCX,-0x60(%RBP)

0x4e73a6 MOV	%RDX,-0xc0(%RBP)

0x4e73ad MOV	0xe0(%RBP),%RAX

0x4e73b4 MOV	%RAX,-0x98(%RBP)

0x4e73bb MOV	0xd8(%RBP),%RAX

0x4e73c2 MOV	%RAX,-0x100(%RBP)

0x4e73c9 MOV	0xd0(%RBP),%RAX

0x4e73d0 MOV	%RAX,-0x78(%RBP)

0x4e73d4 MOV	0xc8(%RBP),%RAX

0x4e73db MOV	%RAX,-0xf8(%RBP)

0x4e73e2 MOV	0xc0(%RBP),%RAX

0x4e73e9 MOV	%RAX,-0xf0(%RBP)

0x4e73f0 MOV	0xb8(%RBP),%RAX

0x4e73f7 MOV	%RAX,-0x70(%RBP)

0x4e73fb MOV	0xb0(%RBP),%RAX

0x4e7402 MOV	%RAX,-0xe8(%RBP)

0x4e7409 MOV	0xa8(%RBP),%RAX

0x4e7410 MOV	%RAX,-0x48(%RBP)

0x4e7414 MOV	0xa0(%RBP),%RAX

0x4e741b MOV	%RAX,-0x88(%RBP)

0x4e7422 MOV	0x98(%RBP),%RAX

0x4e7429 MOV	%RAX,-0x30(%RBP)

0x4e742d MOV	0x90(%RBP),%R13

0x4e7434 MOV	0x88(%RBP),%RAX

0x4e743b MOV	%RAX,-0x50(%RBP)

0x4e743f MOV	0x80(%RBP),%RAX

0x4e7446 MOV	%RAX,-0x40(%RBP)

0x4e744a MOV	0x78(%RBP),%R12

0x4e744e MOV	0x70(%RBP),%RAX

0x4e7452 MOV	%RAX,-0xe0(%RBP)

0x4e7459 MOV	0x68(%RBP),%RAX

0x4e745d MOV	%RAX,-0xb8(%RBP)

0x4e7464 MOV	0x60(%RBP),%R15

0x4e7468 MOV	0x58(%RBP),%RAX

0x4e746c MOV	%RAX,-0xd8(%RBP)

0x4e7473 MOV	0x50(%RBP),%RAX

0x4e7477 MOV	%RAX,-0x68(%RBP)

0x4e747b MOV	0x48(%RBP),%RAX

0x4e747f MOV	%RAX,-0xd0(%RBP)

0x4e7486 MOV	0x40(%RBP),%RAX

0x4e748a MOV	%RAX,-0x110(%RBP)

0x4e7491 MOV	0x38(%RBP),%RAX

0x4e7495 MOV	%RAX,-0x80(%RBP)

0x4e7499 MOV	0x30(%RBP),%RAX

0x4e749d MOV	%RAX,-0x108(%RBP)

0x4e74a4 MOV	0x28(%RBP),%RAX

0x4e74a8 MOV	%RAX,-0x90(%RBP)

0x4e74af MOV	0x20(%RBP),%R14

0x4e74b3 MOV	0x18(%RBP),%RAX

0x4e74b7 MOV	%RAX,-0xa0(%RBP)

0x4e74be MOV	0x10(%RBP),%RAX

0x4e74c2 MOV	%RAX,-0x58(%RBP)

0x4e74c6 CALL	51da60 <hypre_GetThreadNum>

0x4e74cb MOV	%RAX,%RBX

0x4e74ce CALL	51da50 <hypre_NumActiveThreads>

0x4e74d3 MOV	%RAX,%RCX

0x4e74d6 OR	%R14,%RAX

0x4e74d9 SHR	$0x20,%RAX

0x4e74dd JE	4e7540

0x4e74df MOV	%R14,%RAX

0x4e74e2 CQTO

0x4e74e4 IDIV	%RCX

0x4e74e7 MOV	%RDX,-0x38(%RBP)

0x4e74eb LEA	0x1(%RBX),%RCX

0x4e74ef CMP	-0x38(%RBP),%RBX

0x4e74f3 MOV	-0x48(%RBP),%R9

0x4e74f7 JGE	4e7559

0x4e74f9 LEA	0x1(%RAX),%R8

0x4e74fd IMUL	%RBX,%R8

0x4e7501 MOV	%RCX,-0x38(%RBP)

0x4e7505 JMP	4e7564

0x4e7507 NOPW	%CS:(%RAX,%RAX,1)

0x4e7516 NOPW	%CS:(%RAX,%RAX,1)

0x4e7525 NOPW	%CS:(%RAX,%RAX,1)

0x4e7534 NOPW	%CS:(%RAX,%RAX,1)

0x4e7540 MOV	%R14D,%EAX

0x4e7543 XOR	%EDX,%EDX

0x4e7545 DIV	%ECX

0x4e7547 MOV	%RDX,-0x38(%RBP)

0x4e754b LEA	0x1(%RBX),%RCX

0x4e754f CMP	-0x38(%RBP),%RBX

0x4e7553 MOV	-0x48(%RBP),%R9

0x4e7557 JL	4e74f9

0x4e7559 IMUL	%RAX,%RBX

0x4e755d ADD	-0x38(%RBP),%RBX

0x4e7561 MOV	%RBX,%R8

0x4e7564 MOV	-0x30(%RBP),%RDX

0x4e7568 MOV	-0x40(%RBP),%RBX

0x4e756c IMUL	%RCX,%RAX

0x4e7570 MOV	(%RBX),%RCX

0x4e7573 MOV	(%RCX,%R8,8),%RBX

0x4e7577 MOV	(%RDX),%RCX

0x4e757a MOV	(%RCX,%R8,8),%RCX

0x4e757e MOV	%RCX,-0x30(%RBP)

0x4e7582 MOV	(%R9),%RCX

0x4e7585 XOR	%ESI,%ESI

0x4e7587 MOV	%R15,%RDX

0x4e758a OR	%RCX,%RDX

0x4e758d MOV	$0,%EDI

0x4e7592 MOV	%R15,-0x40(%RBP)

0x4e7596 JE	4e75c2

0x4e7598 ADD	%R15,%RCX

0x4e759b MOV	$0x8,%ESI

0x4e75a0 MOV	%RCX,%RDI

0x4e75a3 MOV	%RAX,%R15

0x4e75a6 MOV	%R8,%R14

0x4e75a9 CALL	51b840 <hypre_CAlloc>

0x4e75ae MOV	-0x48(%RBP),%R9

0x4e75b2 MOV	%R14,%R8

0x4e75b5 MOV	%RAX,%RDI

0x4e75b8 MOV	%R15,%RAX

0x4e75bb MOV	-0x40(%RBP),%R15

0x4e75bf MOV	(%R9),%RSI

0x4e75c2 MOV	-0x38(%RBP),%RCX

0x4e75c6 ADD	%RAX,%RCX

0x4e75c9 MOV	%RCX,-0x38(%RBP)

0x4e75cd ADD	%R15,%RSI

0x4e75d0 JLE	4e75f6

0x4e75d2 XOR	%EAX,%EAX

0x4e75d4 NOPW	%CS:(%RAX,%RAX,1)

(3602) 0x4e75e0 MOVQ	$-0x1,(%RDI,%RAX,8)

(3602) 0x4e75e8 INC	%RAX

(3602) 0x4e75eb MOV	(%R9),%RCX

(3602) 0x4e75ee ADD	%R15,%RCX

(3602) 0x4e75f1 CMP	%RCX,%RAX

(3602) 0x4e75f4 JL	4e75e0

0x4e75f6 CMP	-0x38(%RBP),%R8

0x4e75fa JGE	4e7a40

0x4e7600 MOV	%RBX,%RAX

0x4e7603 JMP	4e7651

0x4e7605 NOPW	%CS:(%RAX,%RAX,1)

0x4e7614 NOPW	%CS:(%RAX,%RAX,1)

0x4e7623 NOPW	%CS:(%RAX,%RAX,1)

0x4e7632 NOPW	%CS:(%RAX,%RAX,1)

(3595) 0x4e7640 MOV	%RCX,-0x30(%RBP)

(3595) 0x4e7644 MOV	%RAX,%RBX

(3595) 0x4e7647 CMP	-0x38(%RBP),%R8

(3595) 0x4e764b JGE	4e7a40

(3595) 0x4e7651 MOV	%R8,%RSI

(3595) 0x4e7654 CMPQ	$0,-0x98(%RBP)

(3595) 0x4e765c JE	4e7676

(3595) 0x4e765e MOV	%RBX,(%RDI,%RSI,8)

(3595) 0x4e7662 MOVQ	$0,(%R12,%RBX,8)

(3595) 0x4e766a MOV	-0x50(%RBP),%RAX

(3595) 0x4e766e MOV	%RSI,(%RAX,%RBX,8)

(3595) 0x4e7672 LEA	0x1(%RBX),%RAX

(3595) 0x4e7676 CMPQ	$0,-0x90(%RBP)

(3595) 0x4e767e JE	4e7880

(3595) 0x4e7684 MOV	-0x58(%RBP),%RCX

(3595) 0x4e7688 MOV	(%RCX,%RSI,8),%R10

(3595) 0x4e768c LEA	0x1(%RSI),%R8

(3595) 0x4e7690 CMP	0x8(%RCX,%RSI,8),%R10

(3595) 0x4e7695 JGE	4e7884

(3595) 0x4e769b MOV	%R8,-0x48(%RBP)

(3595) 0x4e769f MOV	-0x30(%RBP),%RCX

(3595) 0x4e76a3 MOV	%RSI,-0xb0(%RBP)

(3595) 0x4e76aa JMP	4e76dc

0x4e76ac NOPW	%CS:(%RAX,%RAX,1)

0x4e76bb NOPL	(%RAX,%RAX,1)

  (3599) 0x4e76c0 MOV	%R14,%R10

  (3599) 0x4e76c3 INC	%R10

  (3599) 0x4e76c6 MOV	-0x58(%RBP),%RDX

  (3599) 0x4e76ca MOV	-0xb0(%RBP),%RSI

  (3599) 0x4e76d1 CMP	0x8(%RDX,%RSI,8),%R10

  (3599) 0x4e76d6 JGE	4e78c0

  (3599) 0x4e76dc MOV	-0xa0(%RBP),%RDX

  (3599) 0x4e76e3 MOV	(%RDX,%R10,8),%R9

  (3599) 0x4e76e7 MOV	-0xa8(%RBP),%RDX

  (3599) 0x4e76ee MOV	%R10,%R14

  (3599) 0x4e76f1 VMOVSD	(%RDX,%R10,8),%XMM0

  (3599) 0x4e76f7 MOV	-0x78(%RBP),%RDX

  (3599) 0x4e76fb MOV	(%RDX,%R9,8),%R10

  (3599) 0x4e76ff MOV	0x8(%RDX,%R9,8),%R11

  (3599) 0x4e7704 JMP	4e7755

0x4e7706 NOPW	%CS:(%RAX,%RAX,1)

0x4e7715 NOPW	%CS:(%RAX,%RAX,1)

0x4e7724 NOPW	%CS:(%RAX,%RAX,1)

0x4e7733 NOPW	%CS:(%RAX,%RAX,1)

    (3601) 0x4e7740 VADDSD	(%R13,%R8,8),%XMM1,%XMM1

    (3601) 0x4e7747 VMOVSD	%XMM1,(%R13,%R8,8)

    (3601) 0x4e774e MOV	-0x40(%RBP),%R15

    (3601) 0x4e7752 INC	%R10

    (3601) 0x4e7755 CMP	%R11,%R10

    (3601) 0x4e7758 JGE	4e77c0

    (3601) 0x4e775a MOV	-0x100(%RBP),%RDX

    (3601) 0x4e7761 MOV	(%RDX,%R10,8),%RSI

    (3601) 0x4e7765 LEA	(%RSI,%R15,1),%RDX

    (3601) 0x4e7769 MOV	(%RDI,%RDX,8),%R8

    (3601) 0x4e776d MOV	-0xf8(%RBP),%R15

    (3601) 0x4e7774 VMULSD	(%R15,%R10,8),%XMM0,%XMM1

    (3601) 0x4e777a CMP	-0x30(%RBP),%R8

    (3601) 0x4e777e JGE	4e7740

    (3601) 0x4e7780 MOV	%RCX,(%RDI,%RDX,8)

    (3601) 0x4e7784 VMOVSD	%XMM1,(%R13,%RCX,8)

    (3601) 0x4e778b MOV	-0x88(%RBP),%RDX

    (3601) 0x4e7792 MOV	%RSI,(%RDX,%RCX,8)

    (3601) 0x4e7796 INC	%RCX

    (3601) 0x4e7799 MOV	-0x78(%RBP),%RDX

    (3601) 0x4e779d MOV	0x8(%RDX,%R9,8),%R11

    (3601) 0x4e77a2 JMP	4e774e

0x4e77a4 NOPW	%CS:(%RAX,%RAX,1)

0x4e77b3 NOPW	%CS:(%RAX,%RAX,1)

  (3599) 0x4e77c0 MOV	-0x70(%RBP),%RDX

  (3599) 0x4e77c4 MOV	(%RDX,%R9,8),%R10

  (3599) 0x4e77c8 MOV	0x8(%RDX,%R9,8),%R11

  (3599) 0x4e77cd CMP	%R11,%R10

  (3599) 0x4e77d0 JL	4e782a

  (3599) 0x4e77d2 JMP	4e76c0

0x4e77d7 NOPW	%CS:(%RAX,%RAX,1)

0x4e77e6 NOPW	%CS:(%RAX,%RAX,1)

0x4e77f5 NOPW	%CS:(%RAX,%RAX,1)

    (3600) 0x4e7800 MOV	%RAX,(%RDI,%RSI,8)

    (3600) 0x4e7804 VMOVSD	%XMM1,(%R12,%RAX,8)

    (3600) 0x4e780a MOV	-0x50(%RBP),%RDX

    (3600) 0x4e780e MOV	%RSI,(%RDX,%RAX,8)

    (3600) 0x4e7812 INC	%RAX

    (3600) 0x4e7815 MOV	-0x70(%RBP),%RDX

    (3600) 0x4e7819 MOV	0x8(%RDX,%R9,8),%R11

    (3600) 0x4e781e INC	%R10

    (3600) 0x4e7821 CMP	%R11,%R10

    (3600) 0x4e7824 JGE	4e76c0

    (3600) 0x4e782a MOV	-0xf0(%RBP),%RDX

    (3600) 0x4e7831 MOV	(%RDX,%R10,8),%RSI

    (3600) 0x4e7835 MOV	(%RDI,%RSI,8),%RDX

    (3600) 0x4e7839 MOV	-0xe8(%RBP),%R8

    (3600) 0x4e7840 VMULSD	(%R8,%R10,8),%XMM0,%XMM1

    (3600) 0x4e7846 CMP	%RBX,%RDX

    (3600) 0x4e7849 JL	4e7800

    (3600) 0x4e784b VADDSD	(%R12,%RDX,8),%XMM1,%XMM1

    (3600) 0x4e7851 VMOVSD	%XMM1,(%R12,%RDX,8)

    (3600) 0x4e7857 INC	%R10

    (3600) 0x4e785a CMP	%R11,%R10

    (3600) 0x4e785d JL	4e782a

  (3599) 0x4e785f JMP	4e76c0

0x4e7864 NOPW	%CS:(%RAX,%RAX,1)

0x4e7873 NOPW	%CS:(%RAX,%RAX,1)

(3595) 0x4e7880 LEA	0x1(%RSI),%R8

(3595) 0x4e7884 MOV	-0x30(%RBP),%RCX

(3595) 0x4e7888 MOV	-0x60(%RBP),%RDX

(3595) 0x4e788c MOV	(%RDX,%RSI,8),%RSI

(3595) 0x4e7890 CMP	(%RDX,%R8,8),%RSI

(3595) 0x4e7894 JGE	4e7640

(3595) 0x4e789a JMP	4e78d6

0x4e789c NOPW	%CS:(%RAX,%RAX,1)

0x4e78ab NOPW	%CS:(%RAX,%RAX,1)

0x4e78ba NOPW	(%RAX,%RAX,1)

(3595) 0x4e78c0 MOV	-0x48(%RBP),%R8

(3595) 0x4e78c4 MOV	-0x60(%RBP),%RDX

(3595) 0x4e78c8 MOV	(%RDX,%RSI,8),%RSI

(3595) 0x4e78cc CMP	(%RDX,%R8,8),%RSI

(3595) 0x4e78d0 JGE	4e7640

(3595) 0x4e78d6 MOV	%R8,-0x48(%RBP)

(3595) 0x4e78da JMP	4e7915

0x4e78dc NOPW	%CS:(%RAX,%RAX,1)

0x4e78eb NOPW	%CS:(%RAX,%RAX,1)

0x4e78fa NOPW	(%RAX,%RAX,1)

  (3596) 0x4e7900 INC	%RSI

  (3596) 0x4e7903 MOV	-0x60(%RBP),%RDX

  (3596) 0x4e7907 MOV	-0x48(%RBP),%R8

  (3596) 0x4e790b CMP	(%RDX,%R8,8),%RSI

  (3596) 0x4e790f JGE	4e7640

  (3596) 0x4e7915 MOV	-0xc8(%RBP),%RDX

  (3596) 0x4e791c MOV	(%RDX,%RSI,8),%R8

  (3596) 0x4e7920 MOV	-0xc0(%RBP),%RDX

  (3596) 0x4e7927 VMOVSD	(%RDX,%RSI,8),%XMM0

  (3596) 0x4e792c MOV	-0x80(%RBP),%RDX

  (3596) 0x4e7930 MOV	(%RDX,%R8,8),%R9

  (3596) 0x4e7934 MOV	0x8(%RDX,%R8,8),%R10

  (3596) 0x4e7939 CMP	%R10,%R9

  (3596) 0x4e793c JL	4e7966

  (3596) 0x4e793e JMP	4e799b

    (3598) 0x4e7940 MOV	%RAX,(%RDI,%RDX,8)

    (3598) 0x4e7944 VMOVSD	%XMM1,(%R12,%RAX,8)

    (3598) 0x4e794a MOV	-0x50(%RBP),%R10

    (3598) 0x4e794e MOV	%RDX,(%R10,%RAX,8)

    (3598) 0x4e7952 INC	%RAX

    (3598) 0x4e7955 MOV	-0x80(%RBP),%RDX

    (3598) 0x4e7959 MOV	0x8(%RDX,%R8,8),%R10

    (3598) 0x4e795e INC	%R9

    (3598) 0x4e7961 CMP	%R10,%R9

    (3598) 0x4e7964 JGE	4e799b

    (3598) 0x4e7966 MOV	-0x110(%RBP),%RDX

    (3598) 0x4e796d MOV	(%RDX,%R9,8),%RDX

    (3598) 0x4e7971 MOV	(%RDI,%RDX,8),%R11

    (3598) 0x4e7975 MOV	-0x108(%RBP),%R14

    (3598) 0x4e797c VMULSD	(%R14,%R9,8),%XMM0,%XMM1

    (3598) 0x4e7982 CMP	%RBX,%R11

    (3598) 0x4e7985 JL	4e7940

    (3598) 0x4e7987 VADDSD	(%R12,%R11,8),%XMM1,%XMM1

    (3598) 0x4e798d VMOVSD	%XMM1,(%R12,%R11,8)

    (3598) 0x4e7993 INC	%R9

    (3598) 0x4e7996 CMP	%R10,%R9

    (3598) 0x4e7999 JL	4e7966

  (3596) 0x4e799b CMPQ	$0,-0xb8(%RBP)

  (3596) 0x4e79a3 JE	4e7900

  (3596) 0x4e79a9 MOV	-0x68(%RBP),%RDX

  (3596) 0x4e79ad MOV	(%RDX,%R8,8),%R9

  (3596) 0x4e79b1 MOV	0x8(%RDX,%R8,8),%R10

  (3596) 0x4e79b6 JMP	4e79d5

0x4e79b8 NOPL	(%RAX,%RAX,1)

    (3597) 0x4e79c0 VADDSD	(%R13,%R15,8),%XMM1,%XMM1

    (3597) 0x4e79c7 VMOVSD	%XMM1,(%R13,%R15,8)

    (3597) 0x4e79ce MOV	-0x40(%RBP),%R15

    (3597) 0x4e79d2 INC	%R9

    (3597) 0x4e79d5 CMP	%R10,%R9

    (3597) 0x4e79d8 JGE	4e7900

    (3597) 0x4e79de MOV	-0xd8(%RBP),%RDX

    (3597) 0x4e79e5 MOV	(%RDX,%R9,8),%RDX

    (3597) 0x4e79e9 MOV	-0xe0(%RBP),%R11

    (3597) 0x4e79f0 MOV	(%R11,%RDX,8),%RDX

    (3597) 0x4e79f4 LEA	(%RDX,%R15,1),%R11

    (3597) 0x4e79f8 MOV	(%RDI,%R11,8),%R15

    (3597) 0x4e79fc MOV	-0xd0(%RBP),%R14

    (3597) 0x4e7a03 VMULSD	(%R14,%R9,8),%XMM0,%XMM1

    (3597) 0x4e7a09 CMP	-0x30(%RBP),%R15

    (3597) 0x4e7a0d JGE	4e79c0

    (3597) 0x4e7a0f MOV	%RCX,(%RDI,%R11,8)

    (3597) 0x4e7a13 VMOVSD	%XMM1,(%R13,%RCX,8)

    (3597) 0x4e7a1a MOV	-0x88(%RBP),%R10

    (3597) 0x4e7a21 MOV	%RDX,(%R10,%RCX,8)

    (3597) 0x4e7a25 INC	%RCX

    (3597) 0x4e7a28 MOV	-0x68(%RBP),%RDX

    (3597) 0x4e7a2c MOV	0x8(%RDX,%R8,8),%R10

    (3597) 0x4e7a31 JMP	4e79ce

0x4e7a33 NOPW	%CS:(%RAX,%RAX,1)

0x4e7a40 ADD	$0xe8,%RSP

0x4e7a47 POP	%RBX

0x4e7a48 POP	%R12

0x4e7a4a POP	%R13

0x4e7a4c POP	%R14

0x4e7a4e POP	%R15

0x4e7a50 POP	%RBP

0x4e7a51 JMP	51b990

0x4e7a56 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_4

Source file and lines	par_csr_matop.c:829-995
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:829,840-859,865,874-879,886-891,897-899,907-928,937-940,946-948,956-972,980-989,995.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 29.67 to 6.50 cycles (4.56x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CAlloc: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:857
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:840
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:841

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:842
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:842

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:842

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 352 bytes. The binary function is storing 264 bytes.

General properties

nb instructions	168
nb uops	178
loop length	982
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	55

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	29.67 cycles
front end	29.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.40	9.00	16.67	16.67	21.00	5.20	5.20	21.00	21.00	21.00	5.20	16.67
cycles	5.40	11.60	16.67	16.67	21.00	5.20	5.20	21.00	21.00	21.00	5.20	16.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

16.00

Cycles summary

Front-end	29.67
Dispatch	21.00
DIV/SQRT	16.00
Overall L1	29.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	9%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 29.67 cycles. At this rate:

6% of peak load performance is reached (11.87 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.90 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 29.67 to 21.00 cycles (1.41x speedup).

ASM code

In the binary file, the address of the function is: 4e7380

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xe8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xe0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xb8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x98(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x90(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x88(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x80(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x78(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x70(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x68(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x60(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x108(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 51da60 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 51da50 <hypre_NumActiveThreads>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR %R14,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x20,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JE 4e7540 <hypre_ParMatmul.extracted.12+0x1c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RCX	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOV %RDX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%RBX),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP -0x38(%RBP),%RBX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x48(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JGE 4e7559 <hypre_ParMatmul.extracted.12+0x1d9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%RAX),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RBX,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RCX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 4e7564 <hypre_ParMatmul.extracted.12+0x1e4>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %ECX	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %RDX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%RBX),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP -0x38(%RBP),%RBX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x48(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JL 4e74f9 <hypre_ParMatmul.extracted.12+0x179>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %RAX,%RBX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD -0x38(%RBP),%RBX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x40(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RCX,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV (%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%R8,8),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%R8,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%R9),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV $0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 4e75c2 <hypre_ParMatmul.extracted.12+0x242>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %R15,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 51b840 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x48(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R14,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x40(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R9),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x38(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R15,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 4e75f6 <hypre_ParMatmul.extracted.12+0x276>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP -0x38(%RBP),%R8	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 4e7a40 <hypre_ParMatmul.extracted.12+0x6c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 4e7651 <hypre_ParMatmul.extracted.12+0x2d1>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0xe8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 51b990 <hypre_Free>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_4

Source file and lines	par_csr_matop.c:829-995
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_CAlloc: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:857
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:840
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:841

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:842
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:842

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:842

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 352 bytes. The binary function is storing 264 bytes.

General properties

nb instructions	168
nb uops	178
loop length	982
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	55

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	29.67 cycles
front end	29.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.40	9.00	16.67	16.67	21.00	5.20	5.20	21.00	21.00	21.00	5.20	16.67
cycles	5.40	11.60	16.67	16.67	21.00	5.20	5.20	21.00	21.00	21.00	5.20	16.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

16.00

Cycles summary

Front-end	29.67
Dispatch	21.00
DIV/SQRT	16.00
Overall L1	29.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	9%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 29.67 cycles. At this rate:

6% of peak load performance is reached (11.87 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.90 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4e7380

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xe8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xe0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xb8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x98(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x90(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x88(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x80(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x78(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x70(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x68(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x60(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x108(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 51da60 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 51da50 <hypre_NumActiveThreads>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR %R14,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x20,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JE 4e7540 <hypre_ParMatmul.extracted.12+0x1c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RCX	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOV %RDX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%RBX),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP -0x38(%RBP),%RBX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x48(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JGE 4e7559 <hypre_ParMatmul.extracted.12+0x1d9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%RAX),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RBX,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RCX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 4e7564 <hypre_ParMatmul.extracted.12+0x1e4>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %ECX	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV %RDX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%RBX),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP -0x38(%RBP),%RBX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x48(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JL 4e74f9 <hypre_ParMatmul.extracted.12+0x179>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %RAX,%RBX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD -0x38(%RBP),%RBX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x40(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RCX,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV (%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%R8,8),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%R8,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%R9),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV $0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 4e75c2 <hypre_ParMatmul.extracted.12+0x242>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %R15,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 51b840 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x48(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R14,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x40(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R9),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x38(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R15,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 4e75f6 <hypre_ParMatmul.extracted.12+0x276>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP -0x38(%RBP),%R8	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 4e7a40 <hypre_ParMatmul.extracted.12+0x6c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 4e7651 <hypre_ParMatmul.extracted.12+0x2d1>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0xe8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 51b990 <hypre_Free>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼hypre_ParMatmul.extracted.12–	1.15	0.61
▼Loop 3595 - par_csr_matop.c:865-989 - exec–	0.03	0.01
▼Loop 3596 - par_csr_matop.c:937-989 - exec–	0.31	0.13
○Loop 3598 - par_csr_matop.c:946-965 - exec	0.79	0.34
○Loop 3597 - par_csr_matop.c:970-989 - exec	0.02	0.01
▼Loop 3599 - par_csr_matop.c:888-928 - exec–	0.00	0.00
○Loop 3601 - par_csr_matop.c:897-915 - exec	0.00	0.01
○Loop 3600 - par_csr_matop.c:917-928 - exec	0.00	0.01
○Loop 3602 - par_csr_matop.c:858-859 - exec	0.00	0.00

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Matching between your function (in the source code) and the binary function

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Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code