OV - exec - Function hypre_BoomerAMGCreate2ndS.extracted

	Function: hypre_BoomerAMGCreate2ndS.extracted	Module: exec	Source: par_strength.c:1253-1278 [...]	Coverage (incl. loops): 0.03% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1253 - 1278

--------------------------------------------------------------------------------

1253: #pragma omp parallel private(i)

[...]

1259:       hypre_GetSimpleThreadPartition(&i_begin, &i_end, num_cols_diag_S);

1260:

1261:       for (i = i_begin; i < i_end; i++)

1262:       {

1263:          if (CF_marker[i] > 0) num_coarse_private++;

1264:       }

1265:

1266:       hypre_prefix_sum(&num_coarse_private, &num_coarse, num_coarse_prefix_sum);

1267:

1268:       for (i = i_begin; i < i_end; i++)

1269:       {

1270:          if (CF_marker[i] > 0)

1271:          {

1272:             fine_to_coarse[i] = num_coarse_private;

1273:             coarse_to_fine[num_coarse_private] = i;

1274:             num_coarse_private++;

1275:          }

1276:          else

1277:          {

1278:             fine_to_coarse[i] = -1;

0x4ad200 PUSH	%RBP

0x4ad201 MOV	%RSP,%RBP

0x4ad204 PUSH	%R15

0x4ad206 PUSH	%R14

0x4ad208 PUSH	%R12

0x4ad20a PUSH	%RBX

0x4ad20b SUB	$0x20,%RSP

0x4ad20f MOV	%R9,%R15

0x4ad212 MOV	%R8,%RBX

0x4ad215 MOV	%RDX,%R14

0x4ad218 MOV	0x10(%RBP),%R12

0x4ad21c LEA	-0x30(%RBP),%RDI

0x4ad220 LEA	-0x38(%RBP),%RSI

0x4ad224 MOV	%RCX,%RDX

0x4ad227 CALL	51da70 <hypre_GetSimpleThreadPartition>

0x4ad22c MOV	-0x30(%RBP),%RDX

0x4ad230 MOV	-0x38(%RBP),%RAX

0x4ad234 MOV	%RAX,%RDI

0x4ad237 SUB	%RDX,%RDI

0x4ad23a JLE	4ad2c0

0x4ad240 MOV	%RDI,%RCX

0x4ad243 AND	$-0x4,%RCX

0x4ad247 JE	4ad300

0x4ad24d LEA	-0x1(%RCX),%RSI

0x4ad251 LEA	(%R14,%RDX,8),%R8

0x4ad255 VPXOR	%XMM1,%XMM1,%XMM1

0x4ad259 XOR	%R9D,%R9D

0x4ad25c VPXOR	%XMM0,%XMM0,%XMM0

(2501) 0x4ad260 VMOVDQU	(%R8,%R9,8),%YMM2

(2501) 0x4ad266 VPCMPGTQ	%YMM1,%YMM2,%YMM2

(2501) 0x4ad26b VPSUBQ	%YMM2,%YMM0,%YMM0

(2501) 0x4ad26f ADD	$0x4,%R9

(2501) 0x4ad273 CMP	%RSI,%R9

(2501) 0x4ad276 JBE	4ad260

0x4ad278 VEXTRACTI128	$0x1,%YMM0,%XMM1

0x4ad27e VPADDQ	%XMM1,%XMM0,%XMM0

0x4ad282 VPSHUFD	$-0x12,%XMM0,%XMM1

0x4ad287 VPADDQ	%XMM1,%XMM0,%XMM0

0x4ad28b VMOVQ	%XMM0,%RSI

0x4ad290 CMP	%RCX,%RDI

0x4ad293 JNE	4ad304

0x4ad295 JMP	4ad325

0x4ad29a NOPW	%CS:(%RAX,%RAX,1)

0x4ad2a9 NOPW	%CS:(%RAX,%RAX,1)

0x4ad2b8 NOPL	(%RAX,%RAX,1)

0x4ad2c0 XOR	%ESI,%ESI

0x4ad2c2 JMP	4ad325

0x4ad2c4 NOPW	%CS:(%RAX,%RAX,1)

0x4ad2d3 NOPW	%CS:(%RAX,%RAX,1)

0x4ad2e2 NOPW	%CS:(%RAX,%RAX,1)

0x4ad2f1 NOPW	%CS:(%RAX,%RAX,1)

0x4ad300 XOR	%ECX,%ECX

0x4ad302 XOR	%ESI,%ESI

0x4ad304 ADD	%RDX,%RCX

0x4ad307 NOPW	(%RAX,%RAX,1)

(2500) 0x4ad310 XOR	%EDX,%EDX

(2500) 0x4ad312 CMPQ	$0,(%R14,%RCX,8)

(2500) 0x4ad317 SETG	%DL

(2500) 0x4ad31a ADD	%RDX,%RSI

(2500) 0x4ad31d INC	%RCX

(2500) 0x4ad320 CMP	%RCX,%RAX

(2500) 0x4ad323 JNE	4ad310

0x4ad325 MOV	%RSI,-0x28(%RBP)

0x4ad329 LEA	-0x28(%RBP),%RDI

0x4ad32d MOV	%R15,%RSI

0x4ad330 MOV	%R12,%RDX

0x4ad333 VZEROUPPER

0x4ad336 CALL	51edc0 <hypre_prefix_sum>

0x4ad33b MOV	-0x30(%RBP),%RAX

0x4ad33f MOV	-0x38(%RBP),%RCX

0x4ad343 MOV	%RCX,%RSI

0x4ad346 SUB	%RAX,%RSI

0x4ad349 JLE	4ad4b2

0x4ad34f MOV	0x18(%RBP),%RDX

0x4ad353 CMP	$0x4,%RSI

0x4ad357 JB	4ad456

0x4ad35d MOV	%RSI,%RDI

0x4ad360 SHR	$0x2,%RDI

0x4ad364 LEA	0x3(%RAX),%R8

0x4ad368 JMP	4ad395

0x4ad36a NOPW	%CS:(%RAX,%RAX,1)

0x4ad379 NOPL	(%RAX)

(2499) 0x4ad380 MOVQ	$-0x1,(%RBX,%R8,8)

(2499) 0x4ad388 ADD	$0x4,%R8

(2499) 0x4ad38c DEC	%RDI

(2499) 0x4ad38f JE	4ad456

(2499) 0x4ad395 CMPQ	$0,-0x18(%R14,%R8,8)

(2499) 0x4ad39b JLE	4ad400

(2499) 0x4ad39d LEA	-0x3(%R8),%R9

(2499) 0x4ad3a1 MOV	-0x28(%RBP),%R10

(2499) 0x4ad3a5 MOV	%R10,-0x18(%RBX,%R8,8)

(2499) 0x4ad3aa MOV	%R9,(%RDX,%R10,8)

(2499) 0x4ad3ae INC	%R10

(2499) 0x4ad3b1 MOV	%R10,-0x28(%RBP)

(2499) 0x4ad3b5 CMPQ	$0,-0x10(%R14,%R8,8)

(2499) 0x4ad3bb JLE	4ad411

(2499) 0x4ad3bd LEA	-0x2(%R8),%R9

(2499) 0x4ad3c1 MOV	-0x28(%RBP),%R10

(2499) 0x4ad3c5 MOV	%R10,-0x10(%RBX,%R8,8)

(2499) 0x4ad3ca MOV	%R9,(%RDX,%R10,8)

(2499) 0x4ad3ce INC	%R10

(2499) 0x4ad3d1 MOV	%R10,-0x28(%RBP)

(2499) 0x4ad3d5 CMPQ	$0,-0x8(%R14,%R8,8)

(2499) 0x4ad3db JLE	4ad422

(2499) 0x4ad3dd LEA	-0x1(%R8),%R9

(2499) 0x4ad3e1 MOV	-0x28(%RBP),%R10

(2499) 0x4ad3e5 MOV	%R10,-0x8(%RBX,%R8,8)

(2499) 0x4ad3ea MOV	%R9,(%RDX,%R10,8)

(2499) 0x4ad3ee INC	%R10

(2499) 0x4ad3f1 MOV	%R10,-0x28(%RBP)

(2499) 0x4ad3f5 CMPQ	$0,(%R14,%R8,8)

(2499) 0x4ad3fa JG	4ad436

(2499) 0x4ad3fc JMP	4ad380

0x4ad3fe XCHG	%AX,%AX

(2499) 0x4ad400 MOVQ	$-0x1,-0x18(%RBX,%R8,8)

(2499) 0x4ad409 CMPQ	$0,-0x10(%R14,%R8,8)

(2499) 0x4ad40f JG	4ad3bd

(2499) 0x4ad411 MOVQ	$-0x1,-0x10(%RBX,%R8,8)

(2499) 0x4ad41a CMPQ	$0,-0x8(%R14,%R8,8)

(2499) 0x4ad420 JG	4ad3dd

(2499) 0x4ad422 MOVQ	$-0x1,-0x8(%RBX,%R8,8)

(2499) 0x4ad42b CMPQ	$0,(%R14,%R8,8)

(2499) 0x4ad430 JLE	4ad380

(2499) 0x4ad436 MOV	-0x28(%RBP),%R9

(2499) 0x4ad43a MOV	%R9,(%RBX,%R8,8)

(2499) 0x4ad43e MOV	%R8,(%RDX,%R9,8)

(2499) 0x4ad442 INC	%R9

(2499) 0x4ad445 MOV	%R9,-0x28(%RBP)

(2499) 0x4ad449 ADD	$0x4,%R8

(2499) 0x4ad44d DEC	%RDI

(2499) 0x4ad450 JNE	4ad395

0x4ad456 MOV	%RSI,%RDI

0x4ad459 AND	$-0x4,%RDI

0x4ad45d CMP	%RSI,%RDI

0x4ad460 JAE	4ad4b2

0x4ad462 ADD	%RDI,%RAX

0x4ad465 JMP	4ad490

0x4ad467 NOPW	%CS:(%RAX,%RAX,1)

0x4ad476 NOPW	%CS:(%RAX,%RAX,1)

(2498) 0x4ad480 MOVQ	$-0x1,(%RBX,%RAX,8)

(2498) 0x4ad488 INC	%RAX

(2498) 0x4ad48b CMP	%RAX,%RCX

(2498) 0x4ad48e JE	4ad4b2

(2498) 0x4ad490 CMPQ	$0,(%R14,%RAX,8)

(2498) 0x4ad495 JLE	4ad480

(2498) 0x4ad497 MOV	-0x28(%RBP),%RSI

(2498) 0x4ad49b MOV	%RSI,(%RBX,%RAX,8)

(2498) 0x4ad49f MOV	%RAX,(%RDX,%RSI,8)

(2498) 0x4ad4a3 INC	%RSI

(2498) 0x4ad4a6 MOV	%RSI,-0x28(%RBP)

(2498) 0x4ad4aa INC	%RAX

(2498) 0x4ad4ad CMP	%RAX,%RCX

(2498) 0x4ad4b0 JNE	4ad490

0x4ad4b2 ADD	$0x20,%RSP

0x4ad4b6 POP	%RBX

0x4ad4b7 POP	%R12

0x4ad4b9 POP	%R14

0x4ad4bb POP	%R15

0x4ad4bd POP	%RBP

0x4ad4be RET

0x4ad4bf NOP

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_4

Source file and lines	par_strength.c:1253-1278
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1253,1259-1278.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.83 to 3.50 cycles (4.24x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions).

Details

25% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
23% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_GetSimpleThreadPartition: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1259
hypre_prefix_sum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1266

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1266

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 48 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	86
nb uops	89
loop length	397
used x86 registers	13
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.83 cycles
front end	14.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.50	4.40	4.00	4.00	4.00	4.40	4.50	4.00	4.00	4.00	4.20	4.00
cycles	4.50	4.40	4.00	4.00	4.00	4.40	4.50	4.00	4.00	4.00	4.20	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.83
Dispatch	4.50
Overall L1	14.83

Vectorization ratios

all	25%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Vector efficiency ratios

all	15%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.83 cycles. At this rate:

1% of peak load performance is reached (3.24 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.54 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 14.83 to 4.50 cycles (3.30x speedup).

ASM code

In the binary file, the address of the function is: 4ad200

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA -0x30(%RBP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x38(%RBP),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 51da70 <hypre_GetSimpleThreadPartition>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 4ad2c0 <hypre_BoomerAMGCreate2ndS.extracted+0xc0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4ad300 <hypre_BoomerAMGCreate2ndS.extracted+0x100>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RCX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R14,%RDX,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPXOR %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VEXTRACTI128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VPSHUFD $-0x12,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVQ %XMM0,%RSI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
CMP %RCX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 4ad304 <hypre_BoomerAMGCreate2ndS.extracted+0x104>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 4ad325 <hypre_BoomerAMGCreate2ndS.extracted+0x125>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 4ad325 <hypre_BoomerAMGCreate2ndS.extracted+0x125>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,-0x28(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA -0x28(%RBP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 51edc0 <hypre_prefix_sum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 4ad4b2 <hypre_BoomerAMGCreate2ndS.extracted+0x2b2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x18(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP $0x4,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 4ad456 <hypre_BoomerAMGCreate2ndS.extracted+0x256>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x2,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
LEA 0x3(%RAX),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4ad395 <hypre_BoomerAMGCreate2ndS.extracted+0x195>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x4,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
CMP %RSI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 4ad4b2 <hypre_BoomerAMGCreate2ndS.extracted+0x2b2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 4ad490 <hypre_BoomerAMGCreate2ndS.extracted+0x290>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_4

Source file and lines	par_strength.c:1253-1278
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1253,1259-1278.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.83 to 3.50 cycles (4.24x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions).

Details

25% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
23% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

hypre_GetSimpleThreadPartition: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1259
hypre_prefix_sum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1266

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1266

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 48 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	86
nb uops	89
loop length	397
used x86 registers	13
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.83 cycles
front end	14.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.50	4.40	4.00	4.00	4.00	4.40	4.50	4.00	4.00	4.00	4.20	4.00
cycles	4.50	4.40	4.00	4.00	4.00	4.40	4.50	4.00	4.00	4.00	4.20	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.83
Dispatch	4.50
Overall L1	14.83

Vectorization ratios

all	25%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Vector efficiency ratios

all	15%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.83 cycles. At this rate:

1% of peak load performance is reached (3.24 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.54 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4ad200

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA -0x30(%RBP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x38(%RBP),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 51da70 <hypre_GetSimpleThreadPartition>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 4ad2c0 <hypre_BoomerAMGCreate2ndS.extracted+0xc0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4ad300 <hypre_BoomerAMGCreate2ndS.extracted+0x100>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RCX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R14,%RDX,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPXOR %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VEXTRACTI128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VPSHUFD $-0x12,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVQ %XMM0,%RSI	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
CMP %RCX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 4ad304 <hypre_BoomerAMGCreate2ndS.extracted+0x104>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 4ad325 <hypre_BoomerAMGCreate2ndS.extracted+0x125>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 4ad325 <hypre_BoomerAMGCreate2ndS.extracted+0x125>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,-0x28(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA -0x28(%RBP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 51edc0 <hypre_prefix_sum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 4ad4b2 <hypre_BoomerAMGCreate2ndS.extracted+0x2b2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x18(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP $0x4,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 4ad456 <hypre_BoomerAMGCreate2ndS.extracted+0x256>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x2,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
LEA 0x3(%RAX),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4ad395 <hypre_BoomerAMGCreate2ndS.extracted+0x195>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x4,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
CMP %RSI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 4ad4b2 <hypre_BoomerAMGCreate2ndS.extracted+0x2b2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 4ad490 <hypre_BoomerAMGCreate2ndS.extracted+0x290>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCreate2ndS.extracted–	0.03	0.02
○Loop 2499 - par_strength.c:1268-1278 - exec	0.02	0.01
○Loop 2501 - par_strength.c:1261-1263 - exec	0.01	0.01
○Loop 2500 - par_strength.c:1261-1263 - exec	0.00	0.00
○Loop 2498 - par_strength.c:1268-1278 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

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Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

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Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code