OV - exec - Function hypre_BoomerAMGBuildMultipass.extracted.28

	Function: hypre_BoomerAMGBuildMultipass.extracted.28	Module: exec	Source: par_multi_interp.c:1737-1881 [...]	Coverage (incl. loops): 1.43% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1737 - 1881

--------------------------------------------------------------------------------

1737: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa,tmp_array,tmp_array_offd)

[...]

1747:              if (n_fine)

1748:              {    tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); }

1749:              tmp_marker_offd = NULL;

1750:              if (num_cols_offd)

1751:              {    tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1752:              tmp_array = NULL;

1753:              if (n_coarse)

1754:              {    tmp_array = hypre_CTAlloc(HYPRE_Int,n_coarse); }

[...]

1760:              for (i=0; i < n_fine; i++)

1761:              {    tmp_marker[i] = -1; }

1762:              for (i=0; i < num_cols_offd; i++)

1763:              {    tmp_marker_offd[i] = -1; }

1764:

1765:              /* Compute this thread's range of pass_length */

1766:              my_thread_num = hypre_GetThreadNum();

1767:              num_threads = hypre_NumActiveThreads();

1768:              thread_start = pass_pointer[pass] + (pass_length/num_threads)*my_thread_num;

1769:              if (my_thread_num == num_threads-1)

1770:              {  thread_stop = pass_pointer[pass] + pass_length; }

1771:              else

1772:              {  thread_stop = pass_pointer[pass] + (pass_length/num_threads)*(my_thread_num+1); }

1773:

1774:              for (i=thread_start; i < thread_stop; i++)

1775:              {

1776:                 i1 = pass_array[i];

1777:                 sum_C = 0;

1778:                 sum_N = 0;

1779:                 j_start = P_diag_start[i1];

1780:                 j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1781:                 cnt = P_diag_i[i1];

1782:                 for (j=j_start; j < j_end; j++)

1783:                 {

1784:                    k1 = P_diag_pass[pass][j];

1785:                tmp_array[k1] = cnt;

1786:                P_diag_data[cnt] = 0;

1787:                P_diag_j[cnt++] = k1;

1788:                 }

1789:                 j_start = P_offd_start[i1];

1790:                 j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1791:                 cnt_offd = P_offd_i[i1];

1792:                 for (j=j_start; j < j_end; j++)

1793:                 {

1794:                    k1 = P_offd_pass[pass][j];

1795:                tmp_array_offd[k1] = cnt_offd;

1796:                P_offd_data[cnt_offd] = 0;

1797:                P_offd_j[cnt_offd++] = k1;

1798:                 }

1799:                 for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1800:                 {

1801:                j1 = S_diag_j[j];

1802:                if (assigned[j1] == pass-1)

1803:                   tmp_marker[j1] = i1;

1804:                 }

1805:                 for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1806:                 {

1807:                j1 = S_offd_j[j];

1808:                if (assigned_offd[j1] == pass-1)

1809:                   tmp_marker_offd[j1] = i1;

1810:                 }

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

1838:                    }

1839:                 }

1840:                 for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1841:                 {

1842:                if (col_offd_S_to_A)

1843:                   j1 = map_A_to_S[A_offd_j[j]];

1844:                else

1845:                   j1 = A_offd_j[j];

1846:

1847:                if (j1 > -1 && tmp_marker_offd[j1] == i1)

1848:                {

1849:                   j_start = Pext_start[j1];

1850:                   j_end = j_start+Pext_i[j1+1];

1851:                   for (k=j_start; k < j_end; k++)

1852:                   {

1853:                  k1 = Pext_pass[pass][k];

1854:                      alfa = A_offd_data[j]*Pext_data[k];

1855:                  if (k1 < 0)

1856:                         P_diag_data[tmp_array[-k1-1]] += alfa;

1857:                  else

1858:                         P_offd_data[tmp_array_offd[k1]] += alfa;

1859:                      sum_C += alfa;

1860:                      sum_N += alfa;

1861:                       }

1862:                    }

1863:                    else

1864:                    {

1865:                       if (CF_marker_offd[j1] != -3 &&

1866:                 (num_functions == 1 || dof_func_offd[j1] == dof_func[i1]))

1867:                  sum_N += A_offd_data[j];

1868:                    }

1869:                 }

1870:                 diagonal = A_diag_data[A_diag_i[i1]];

1871:                 if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1872:

1873:                 for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++)

1874:                P_diag_data[j] *= alfa;

1875:                 for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++)

1876:                P_offd_data[j] *= alfa;

1877:              }

1878:              hypre_TFree(tmp_marker);

1879:              hypre_TFree(tmp_marker_offd);

1880:              hypre_TFree(tmp_array);

1881:              hypre_TFree(tmp_array_offd);

0x450ab0 PUSH	%RBP

0x450ab1 MOV	%RSP,%RBP

0x450ab4 PUSH	%R15

0x450ab6 PUSH	%R14

0x450ab8 PUSH	%R13

0x450aba PUSH	%R12

0x450abc PUSH	%RBX

0x450abd SUB	$0x168,%RSP

0x450ac4 MOV	%R9,-0x188(%RBP)

0x450acb MOV	%R8,-0xa8(%RBP)

0x450ad2 MOV	%RCX,-0xc8(%RBP)

0x450ad9 MOV	%RDX,-0x140(%RBP)

0x450ae0 MOV	0x138(%RBP),%RAX

0x450ae7 MOV	%RAX,-0x38(%RBP)

0x450aeb MOV	0x130(%RBP),%RAX

0x450af2 MOV	%RAX,-0x48(%RBP)

0x450af6 MOV	0x128(%RBP),%RAX

0x450afd MOV	%RAX,-0x130(%RBP)

0x450b04 MOV	0x120(%RBP),%RAX

0x450b0b MOV	%RAX,-0x180(%RBP)

0x450b12 MOV	0x118(%RBP),%RAX

0x450b19 MOV	%RAX,-0x178(%RBP)

0x450b20 MOV	0x110(%RBP),%R15

0x450b27 MOV	0x108(%RBP),%R12

0x450b2e MOV	0x100(%RBP),%RDI

0x450b35 MOV	0xf8(%RBP),%RAX

0x450b3c MOV	%RAX,-0x60(%RBP)

0x450b40 MOV	0xf0(%RBP),%RAX

0x450b47 MOV	%RAX,-0x148(%RBP)

0x450b4e MOV	0xe8(%RBP),%RAX

0x450b55 MOV	%RAX,-0x138(%RBP)

0x450b5c MOV	0xe0(%RBP),%RAX

0x450b63 MOV	%RAX,-0x128(%RBP)

0x450b6a MOV	0xd8(%RBP),%RAX

0x450b71 MOV	%RAX,-0xe8(%RBP)

0x450b78 MOV	0xd0(%RBP),%RAX

0x450b7f MOV	%RAX,-0xe0(%RBP)

0x450b86 MOV	0xc8(%RBP),%RAX

0x450b8d MOV	%RAX,-0x110(%RBP)

0x450b94 MOV	0xc0(%RBP),%RAX

0x450b9b MOV	%RAX,-0x108(%RBP)

0x450ba2 MOV	0xb8(%RBP),%RAX

0x450ba9 MOV	%RAX,-0x50(%RBP)

0x450bad MOV	0xb0(%RBP),%RAX

0x450bb4 MOV	%RAX,-0x100(%RBP)

0x450bbb MOV	0xa8(%RBP),%RAX

0x450bc2 MOV	%RAX,-0x118(%RBP)

0x450bc9 MOV	0xa0(%RBP),%RAX

0x450bd0 MOV	%RAX,-0x150(%RBP)

0x450bd7 MOV	0x98(%RBP),%RAX

0x450bde MOV	%RAX,-0x120(%RBP)

0x450be5 MOV	0x90(%RBP),%RAX

0x450bec MOV	%RAX,-0x40(%RBP)

0x450bf0 MOV	0x88(%RBP),%RAX

0x450bf7 MOV	%RAX,-0xa0(%RBP)

0x450bfe MOV	0x80(%RBP),%R13

0x450c05 MOV	0x78(%RBP),%RAX

0x450c09 MOV	%RAX,-0x58(%RBP)

0x450c0d MOV	0x70(%RBP),%RAX

0x450c11 MOV	%RAX,-0x98(%RBP)

0x450c18 MOV	0x68(%RBP),%R14

0x450c1c MOV	0x60(%RBP),%RCX

0x450c20 MOV	0x58(%RBP),%RAX

0x450c24 MOV	%RAX,-0x170(%RBP)

0x450c2b MOV	0x50(%RBP),%RAX

0x450c2f MOV	%RAX,-0xc0(%RBP)

0x450c36 MOV	0x48(%RBP),%RAX

0x450c3a MOV	%RAX,-0x168(%RBP)

0x450c41 MOV	0x40(%RBP),%RAX

0x450c45 MOV	%RAX,-0xb8(%RBP)

0x450c4c MOV	0x38(%RBP),%RAX

0x450c50 MOV	%RAX,-0x160(%RBP)

0x450c57 MOV	0x30(%RBP),%RAX

0x450c5b MOV	%RAX,-0xf8(%RBP)

0x450c62 MOV	0x28(%RBP),%RAX

0x450c66 MOV	%RAX,-0xb0(%RBP)

0x450c6d MOV	0x20(%RBP),%RAX

0x450c71 MOV	%RAX,-0x158(%RBP)

0x450c78 MOV	0x18(%RBP),%RAX

0x450c7c MOV	%RAX,-0xf0(%RBP)

0x450c83 MOV	0x10(%RBP),%RBX

0x450c87 TEST	%RDI,%RDI

0x450c8a MOV	%RCX,-0x30(%RBP)

0x450c8e MOV	%RDI,-0x90(%RBP)

0x450c95 JE	450d00

0x450c97 MOV	$0x8,%ESI

0x450c9c CALL	51b840 <hypre_CAlloc>

0x450ca1 MOV	-0x30(%RBP),%RCX

0x450ca5 MOV	%RAX,-0x70(%RBP)

0x450ca9 TEST	%RCX,%RCX

0x450cac JE	450d0d

0x450cae MOV	$0x8,%ESI

0x450cb3 MOV	%RCX,%RDI

0x450cb6 CALL	51b840 <hypre_CAlloc>

0x450cbb MOV	%RAX,-0x68(%RBP)

0x450cbf TEST	%R12,%R12

0x450cc2 JE	450d1a

0x450cc4 MOV	$0x8,%ESI

0x450cc9 MOV	%R12,%RDI

0x450ccc CALL	51b840 <hypre_CAlloc>

0x450cd1 MOV	%RAX,%R12

0x450cd4 JMP	450d1d

0x450cd6 NOPW	%CS:(%RAX,%RAX,1)

0x450ce5 NOPW	%CS:(%RAX,%RAX,1)

0x450cf4 NOPW	%CS:(%RAX,%RAX,1)

0x450d00 MOVQ	$0,-0x70(%RBP)

0x450d08 TEST	%RCX,%RCX

0x450d0b JNE	450cae

0x450d0d MOVQ	$0,-0x68(%RBP)

0x450d15 TEST	%R12,%R12

0x450d18 JNE	450cc4

0x450d1a XOR	%R12D,%R12D

0x450d1d MOV	-0x48(%RBP),%RAX

0x450d21 CMP	%R15,%RAX

0x450d24 CMOVG	%RAX,%R15

0x450d28 MOV	$0x8,%ESI

0x450d2d MOV	%R15,%RDI

0x450d30 CALL	51b840 <hypre_CAlloc>

0x450d35 MOV	%RAX,%R15

0x450d38 MOV	-0x90(%RBP),%RDX

0x450d3f TEST	%RDX,%RDX

0x450d42 JLE	450d56

0x450d44 SAL	$0x3,%RDX

0x450d48 MOV	-0x70(%RBP),%RDI

0x450d4c MOV	$0xff,%ESI

0x450d51 CALL	5277f0 <__intel_avx_rep_memset>

0x450d56 MOV	-0x30(%RBP),%RDX

0x450d5a TEST	%RDX,%RDX

0x450d5d JLE	450d71

0x450d5f SAL	$0x3,%RDX

0x450d63 MOV	-0x68(%RBP),%RDI

0x450d67 MOV	$0xff,%ESI

0x450d6c CALL	5277f0 <__intel_avx_rep_memset>

0x450d71 CALL	51da60 <hypre_GetThreadNum>

0x450d76 MOV	%RAX,-0x30(%RBP)

0x450d7a CALL	51da50 <hypre_NumActiveThreads>

0x450d7f MOV	%RAX,%RCX

0x450d82 MOV	-0x60(%RBP),%RAX

0x450d86 MOV	(%RAX),%RAX

0x450d89 MOV	-0x50(%RBP),%RDX

0x450d8d MOV	(%RDX,%RAX,8),%RSI

0x450d91 MOV	-0x38(%RBP),%R8

0x450d95 MOV	%R8,%RAX

0x450d98 OR	%RCX,%RAX

0x450d9b SHR	$0x20,%RAX

0x450d9f JE	450dc0

0x450da1 MOV	%R8,%RAX

0x450da4 CQTO

0x450da6 IDIV	%RCX

0x450da9 JMP	450dc7

0x450dab NOPW	%CS:(%RAX,%RAX,1)

0x450dba NOPW	(%RAX,%RAX,1)

0x450dc0 MOV	%R8D,%EAX

0x450dc3 XOR	%EDX,%EDX

0x450dc5 DIV	%ECX

0x450dc7 MOV	-0x40(%RBP),%R10

0x450dcb MOV	%RAX,%RDX

0x450dce MOV	-0x30(%RBP),%R9

0x450dd2 IMUL	%R9,%RDX

0x450dd6 DEC	%RCX

0x450dd9 LEA	0x1(%R9),%RDI

0x450ddd IMUL	%RAX,%RDI

0x450de1 CMP	%RCX,%R9

0x450de4 CMOVE	%R8,%RDI

0x450de8 MOV	%RDI,-0x88(%RBP)

0x450def CMP	%RDI,%RDX

0x450df2 JGE	451a80

0x450df8 MOV	-0x88(%RBP),%RAX

0x450dff ADD	%RSI,%RAX

0x450e02 MOV	%RAX,-0x88(%RBP)

0x450e09 ADD	%RSI,%RDX

0x450e0c MOV	-0x58(%RBP),%RAX

0x450e10 ADD	$0x38,%RAX

0x450e14 MOV	%RAX,-0xd8(%RBP)

0x450e1b LEA	0x38(%R10),%RAX

0x450e1f MOV	%RAX,-0xd0(%RBP)

0x450e26 VXORPD	%XMM16,%XMM16,%XMM16

0x450e2c VMOVDDUP	0xd9d8a(%RIP),%XMM17

0x450e36 MOV	%R12,-0x50(%RBP)

0x450e3a JMP	450e57

0x450e3c NOPL	(%RAX)

(974) 0x450e40 MOV	-0x90(%RBP),%RDX

(974) 0x450e47 INC	%RDX

(974) 0x450e4a CMP	-0x88(%RBP),%RDX

(974) 0x450e51 JGE	451a80

(974) 0x450e57 MOV	-0x100(%RBP),%RAX

(974) 0x450e5e MOV	%RDX,-0x90(%RBP)

(974) 0x450e65 MOV	(%RAX,%RDX,8),%R9

(974) 0x450e69 MOV	-0x108(%RBP),%RAX

(974) 0x450e70 MOV	(%RAX,%R9,8),%R8

(974) 0x450e74 MOV	-0x98(%RBP),%RAX

(974) 0x450e7b MOV	(%RAX,%R9,8),%R12

(974) 0x450e7f MOV	0x8(%RAX,%R9,8),%RDI

(974) 0x450e84 LEA	(%RDI,%R8,1),%RAX

(974) 0x450e88 SUB	%R12,%RAX

(974) 0x450e8b CMP	%RAX,%R8

(974) 0x450e8e MOV	%R9,-0x30(%RBP)

(974) 0x450e92 JGE	45106f

(974) 0x450e98 MOV	-0x60(%RBP),%RAX

(974) 0x450e9c MOV	(%RAX),%RAX

(974) 0x450e9f MOV	-0xe0(%RBP),%RCX

(974) 0x450ea6 MOV	(%RCX,%RAX,8),%RAX

(974) 0x450eaa MOV	%RDI,%RCX

(974) 0x450ead SUB	%R12,%RCX

(974) 0x450eb0 CMP	$0xd,%RCX

(974) 0x450eb4 JB	451040

(974) 0x450eba MOV	%RDI,-0x80(%RBP)

(974) 0x450ebe LEA	(%R14,%R12,8),%RDI

(974) 0x450ec2 MOV	%RCX,-0x78(%RBP)

(974) 0x450ec6 LEA	(,%RCX,8),%RDX

(974) 0x450ece XOR	%ESI,%ESI

(974) 0x450ed0 MOV	%RAX,-0x38(%RBP)

(974) 0x450ed4 MOV	%R8,-0x48(%RBP)

(974) 0x450ed8 VZEROUPPER

(974) 0x450edb CALL	5277f0 <__intel_avx_rep_memset>

(974) 0x450ee0 MOV	-0x78(%RBP),%RAX

(974) 0x450ee4 MOV	%RAX,%R10

(974) 0x450ee7 SHR	$0x3,%RAX

(974) 0x450eeb MOV	-0x48(%RBP),%RDX

(974) 0x450eef MOV	-0x38(%RBP),%RCX

(974) 0x450ef3 LEA	0x38(%RCX,%RDX,8),%RCX

(974) 0x450ef8 MOV	-0xd8(%RBP),%RDX

(974) 0x450eff LEA	(%RDX,%R12,8),%RDX

(974) 0x450f03 MOV	%RAX,%RSI

(974) 0x450f06 XOR	%EDI,%EDI

(974) 0x450f08 MOV	-0x50(%RBP),%R11

(974) 0x450f0c NOPL	(%RAX)

  (992) 0x450f10 MOV	-0x38(%RCX,%RDI,8),%R8

  (992) 0x450f15 LEA	(%R12,%RDI,1),%R9

  (992) 0x450f19 MOV	%R9,(%R11,%R8,8)

  (992) 0x450f1d MOV	%R8,-0x38(%RDX,%RDI,8)

  (992) 0x450f22 MOV	-0x30(%RCX,%RDI,8),%R8

  (992) 0x450f27 LEA	0x1(%R12,%RDI,1),%R9

  (992) 0x450f2c MOV	%R9,(%R11,%R8,8)

  (992) 0x450f30 MOV	%R8,-0x30(%RDX,%RDI,8)

  (992) 0x450f35 MOV	-0x28(%RCX,%RDI,8),%R8

  (992) 0x450f3a LEA	0x2(%R12,%RDI,1),%R9

  (992) 0x450f3f MOV	%R9,(%R11,%R8,8)

  (992) 0x450f43 MOV	%R8,-0x28(%RDX,%RDI,8)

  (992) 0x450f48 MOV	-0x20(%RCX,%RDI,8),%R8

  (992) 0x450f4d LEA	0x3(%R12,%RDI,1),%R9

  (992) 0x450f52 MOV	%R9,(%R11,%R8,8)

  (992) 0x450f56 MOV	%R8,-0x20(%RDX,%RDI,8)

  (992) 0x450f5b MOV	-0x18(%RCX,%RDI,8),%R8

  (992) 0x450f60 LEA	0x4(%R12,%RDI,1),%R9

  (992) 0x450f65 MOV	%R9,(%R11,%R8,8)

  (992) 0x450f69 MOV	%R8,-0x18(%RDX,%RDI,8)

  (992) 0x450f6e MOV	-0x10(%RCX,%RDI,8),%R8

  (992) 0x450f73 LEA	0x5(%R12,%RDI,1),%R9

  (992) 0x450f78 MOV	%R9,(%R11,%R8,8)

  (992) 0x450f7c MOV	%R8,-0x10(%RDX,%RDI,8)

  (992) 0x450f81 MOV	-0x8(%RCX,%RDI,8),%R8

  (992) 0x450f86 LEA	0x6(%R12,%RDI,1),%R9

  (992) 0x450f8b MOV	%R9,(%R11,%R8,8)

  (992) 0x450f8f MOV	%R8,-0x8(%RDX,%RDI,8)

  (992) 0x450f94 MOV	(%RCX,%RDI,8),%R8

  (992) 0x450f98 LEA	0x7(%R12,%RDI,1),%R9

  (992) 0x450f9d MOV	%R9,(%R11,%R8,8)

  (992) 0x450fa1 MOV	%R8,(%RDX,%RDI,8)

  (992) 0x450fa5 ADD	$0x8,%RDI

  (992) 0x450fa9 DEC	%RSI

  (992) 0x450fac JNE	450f10

(974) 0x450fb2 MOV	%R10,%RDX

(974) 0x450fb5 MOV	%R10,%RCX

(974) 0x450fb8 AND	$-0x8,%RCX

(974) 0x450fbc CMP	%R10,%RCX

(974) 0x450fbf MOV	-0x40(%RBP),%R10

(974) 0x450fc3 MOV	-0x58(%RBP),%RDX

(974) 0x450fc7 MOV	-0x30(%RBP),%R9

(974) 0x450fcb MOV	-0x80(%RBP),%RSI

(974) 0x450fcf MOV	-0x38(%RBP),%RDI

(974) 0x450fd3 MOV	-0x48(%RBP),%R8

(974) 0x450fd7 JAE	45106f

(974) 0x450fdd ADD	%RCX,%R12

(974) 0x450fe0 SAL	$0x6,%RAX

(974) 0x450fe4 LEA	(%RAX,%R8,8),%RAX

(974) 0x450fe8 ADD	%RAX,%RDI

(974) 0x450feb NOPL	(%RAX,%RAX,1)

  (993) 0x450ff0 MOV	(%RDI),%RAX

  (993) 0x450ff3 MOV	%R12,(%R11,%RAX,8)

  (993) 0x450ff7 MOV	%RAX,(%RDX,%R12,8)

  (993) 0x450ffb INC	%R12

  (993) 0x450ffe ADD	$0x8,%RDI

  (993) 0x451002 CMP	%R12,%RSI

  (993) 0x451005 JNE	450ff0

(974) 0x451007 JMP	45106f

0x451009 NOPW	%CS:(%RAX,%RAX,1)

0x451018 NOPW	%CS:(%RAX,%RAX,1)

0x451027 NOPW	%CS:(%RAX,%RAX,1)

0x451036 NOPW	%CS:(%RAX,%RAX,1)

(974) 0x451040 LEA	(%RAX,%R8,8),%RAX

(974) 0x451044 MOV	-0x58(%RBP),%RDX

(974) 0x451048 MOV	-0x50(%RBP),%RSI

(974) 0x45104c NOPL	(%RAX)

  (991) 0x451050 MOV	(%RAX),%RCX

  (991) 0x451053 MOV	%R12,(%RSI,%RCX,8)

  (991) 0x451057 MOVQ	$0,(%R14,%R12,8)

  (991) 0x45105f MOV	%RCX,(%RDX,%R12,8)

  (991) 0x451063 INC	%R12

  (991) 0x451066 ADD	$0x8,%RAX

  (991) 0x45106a CMP	%R12,%RDI

  (991) 0x45106d JNE	451050

(974) 0x45106f MOV	-0x110(%RBP),%RAX

(974) 0x451076 MOV	(%RAX,%R9,8),%RSI

(974) 0x45107a MOV	-0xa0(%RBP),%RAX

(974) 0x451081 MOV	(%RAX,%R9,8),%R12

(974) 0x451085 MOV	0x8(%RAX,%R9,8),%RDX

(974) 0x45108a LEA	(%RDX,%RSI,1),%RAX

(974) 0x45108e SUB	%R12,%RAX

(974) 0x451091 CMP	%RAX,%RSI

(974) 0x451094 JGE	451230

(974) 0x45109a MOV	-0x60(%RBP),%RAX

(974) 0x45109e MOV	(%RAX),%RAX

(974) 0x4510a1 MOV	-0xe8(%RBP),%RCX

(974) 0x4510a8 MOV	(%RCX,%RAX,8),%RAX

(974) 0x4510ac MOV	%RDX,%RCX

(974) 0x4510af SUB	%R12,%RCX

(974) 0x4510b2 CMP	$0xd,%RCX

(974) 0x4510b6 JB	451200

(974) 0x4510bc MOV	%RDX,-0x48(%RBP)

(974) 0x4510c0 LEA	(%R13,%R12,8),%RDI

(974) 0x4510c5 LEA	(,%RCX,8),%RDX

(974) 0x4510cd MOV	%RSI,-0x38(%RBP)

(974) 0x4510d1 XOR	%ESI,%ESI

(974) 0x4510d3 MOV	%RAX,-0x80(%RBP)

(974) 0x4510d7 MOV	%RCX,-0x78(%RBP)

(974) 0x4510db VZEROUPPER

(974) 0x4510de CALL	5277f0 <__intel_avx_rep_memset>

(974) 0x4510e3 MOV	-0x80(%RBP),%R11

(974) 0x4510e7 MOV	-0x78(%RBP),%RAX

(974) 0x4510eb MOV	%RAX,%R10

(974) 0x4510ee SHR	$0x3,%RAX

(974) 0x4510f2 MOV	-0x38(%RBP),%RCX

(974) 0x4510f6 LEA	0x38(%R11,%RCX,8),%RCX

(974) 0x4510fb MOV	-0xd0(%RBP),%RDX

(974) 0x451102 LEA	(%RDX,%R12,8),%RDX

(974) 0x451106 MOV	%RAX,%RSI

(974) 0x451109 XOR	%EDI,%EDI

(974) 0x45110b NOPL	(%RAX,%RAX,1)

  (989) 0x451110 MOV	-0x38(%RCX,%RDI,8),%R8

  (989) 0x451115 LEA	(%R12,%RDI,1),%R9

  (989) 0x451119 MOV	%R9,(%R15,%R8,8)

  (989) 0x45111d MOV	%R8,-0x38(%RDX,%RDI,8)

  (989) 0x451122 MOV	-0x30(%RCX,%RDI,8),%R8

  (989) 0x451127 LEA	0x1(%R12,%RDI,1),%R9

  (989) 0x45112c MOV	%R9,(%R15,%R8,8)

  (989) 0x451130 MOV	%R8,-0x30(%RDX,%RDI,8)

  (989) 0x451135 MOV	-0x28(%RCX,%RDI,8),%R8

  (989) 0x45113a LEA	0x2(%R12,%RDI,1),%R9

  (989) 0x45113f MOV	%R9,(%R15,%R8,8)

  (989) 0x451143 MOV	%R8,-0x28(%RDX,%RDI,8)

  (989) 0x451148 MOV	-0x20(%RCX,%RDI,8),%R8

  (989) 0x45114d LEA	0x3(%R12,%RDI,1),%R9

  (989) 0x451152 MOV	%R9,(%R15,%R8,8)

  (989) 0x451156 MOV	%R8,-0x20(%RDX,%RDI,8)

  (989) 0x45115b MOV	-0x18(%RCX,%RDI,8),%R8

  (989) 0x451160 LEA	0x4(%R12,%RDI,1),%R9

  (989) 0x451165 MOV	%R9,(%R15,%R8,8)

  (989) 0x451169 MOV	%R8,-0x18(%RDX,%RDI,8)

  (989) 0x45116e MOV	-0x10(%RCX,%RDI,8),%R8

  (989) 0x451173 LEA	0x5(%R12,%RDI,1),%R9

  (989) 0x451178 MOV	%R9,(%R15,%R8,8)

  (989) 0x45117c MOV	%R8,-0x10(%RDX,%RDI,8)

  (989) 0x451181 MOV	-0x8(%RCX,%RDI,8),%R8

  (989) 0x451186 LEA	0x6(%R12,%RDI,1),%R9

  (989) 0x45118b MOV	%R9,(%R15,%R8,8)

  (989) 0x45118f MOV	%R8,-0x8(%RDX,%RDI,8)

  (989) 0x451194 MOV	(%RCX,%RDI,8),%R8

  (989) 0x451198 LEA	0x7(%R12,%RDI,1),%R9

  (989) 0x45119d MOV	%R9,(%R15,%R8,8)

  (989) 0x4511a1 MOV	%R8,(%RDX,%RDI,8)

  (989) 0x4511a5 ADD	$0x8,%RDI

  (989) 0x4511a9 DEC	%RSI

  (989) 0x4511ac JNE	451110

(974) 0x4511b2 MOV	%R10,%RDX

(974) 0x4511b5 MOV	%R10,%RCX

(974) 0x4511b8 AND	$-0x8,%RCX

(974) 0x4511bc CMP	%R10,%RCX

(974) 0x4511bf MOV	-0x40(%RBP),%R10

(974) 0x4511c3 MOV	-0x30(%RBP),%R9

(974) 0x4511c7 MOV	-0x48(%RBP),%RDX

(974) 0x4511cb MOV	-0x38(%RBP),%RSI

(974) 0x4511cf JAE	451230

(974) 0x4511d1 ADD	%RCX,%R12

(974) 0x4511d4 SAL	$0x6,%RAX

(974) 0x4511d8 LEA	(%RAX,%RSI,8),%RAX

(974) 0x4511dc ADD	%RAX,%R11

(974) 0x4511df NOP

  (990) 0x4511e0 MOV	(%R11),%RAX

  (990) 0x4511e3 MOV	%R12,(%R15,%RAX,8)

  (990) 0x4511e7 MOV	%RAX,(%R10,%R12,8)

  (990) 0x4511eb INC	%R12

  (990) 0x4511ee ADD	$0x8,%R11

  (990) 0x4511f2 CMP	%R12,%RDX

  (990) 0x4511f5 JNE	4511e0

(974) 0x4511f7 JMP	451230

0x4511f9 NOPL	(%RAX)

(974) 0x451200 LEA	(%RAX,%RSI,8),%RAX

(974) 0x451204 NOPW	%CS:(%RAX,%RAX,1)

  (988) 0x451210 MOV	(%RAX),%RCX

  (988) 0x451213 MOV	%R12,(%R15,%RCX,8)

  (988) 0x451217 MOVQ	$0,(%R13,%R12,8)

  (988) 0x451220 MOV	%RCX,(%R10,%R12,8)

  (988) 0x451224 INC	%R12

  (988) 0x451227 ADD	$0x8,%RAX

  (988) 0x45122b CMP	%R12,%RDX

  (988) 0x45122e JNE	451210

(974) 0x451230 MOV	-0xb8(%RBP),%RCX

(974) 0x451237 MOV	(%RCX,%R9,8),%RAX

(974) 0x45123b MOV	0x8(%RCX,%R9,8),%RCX

(974) 0x451240 CMP	%RCX,%RAX

(974) 0x451243 MOV	-0x50(%RBP),%R12

(974) 0x451247 JGE	4512c0

(974) 0x451249 MOV	-0x60(%RBP),%RDX

(974) 0x45124d MOV	(%RDX),%RDX

(974) 0x451250 DEC	%RDX

(974) 0x451253 JMP	451288

0x451255 NOPW	%CS:(%RAX,%RAX,1)

0x451264 NOPW	%CS:(%RAX,%RAX,1)

0x451273 NOPW	%CS:(%RAX,%RAX,1)

  (987) 0x451280 INC	%RAX

  (987) 0x451283 CMP	%RCX,%RAX

  (987) 0x451286 JGE	4512c0

  (987) 0x451288 MOV	-0x168(%RBP),%RSI

  (987) 0x45128f MOV	(%RSI,%RAX,8),%RSI

  (987) 0x451293 MOV	-0x178(%RBP),%RDI

  (987) 0x45129a CMP	%RDX,(%RDI,%RSI,8)

  (987) 0x45129e JNE	451280

  (987) 0x4512a0 MOV	-0x70(%RBP),%RCX

  (987) 0x4512a4 MOV	%R9,(%RCX,%RSI,8)

  (987) 0x4512a8 MOV	-0xb8(%RBP),%RCX

  (987) 0x4512af MOV	0x8(%RCX,%R9,8),%RCX

  (987) 0x4512b4 JMP	451280

0x4512b6 NOPW	%CS:(%RAX,%RAX,1)

(974) 0x4512c0 MOV	-0xc0(%RBP),%RCX

(974) 0x4512c7 MOV	(%RCX,%R9,8),%RAX

(974) 0x4512cb MOV	0x8(%RCX,%R9,8),%RCX

(974) 0x4512d0 CMP	%RCX,%RAX

(974) 0x4512d3 JGE	451340

(974) 0x4512d5 MOV	-0x60(%RBP),%RDX

(974) 0x4512d9 MOV	(%RDX),%RDX

(974) 0x4512dc DEC	%RDX

(974) 0x4512df JMP	451308

0x4512e1 NOPW	%CS:(%RAX,%RAX,1)

0x4512f0 NOPW	%CS:(%RAX,%RAX,1)

0x4512ff NOP

  (986) 0x451300 INC	%RAX

  (986) 0x451303 CMP	%RCX,%RAX

  (986) 0x451306 JGE	451340

  (986) 0x451308 MOV	-0x170(%RBP),%RSI

  (986) 0x45130f MOV	(%RSI,%RAX,8),%RSI

  (986) 0x451313 MOV	-0x180(%RBP),%RDI

  (986) 0x45131a CMP	%RDX,(%RDI,%RSI,8)

  (986) 0x45131e JNE	451300

  (986) 0x451320 MOV	-0x68(%RBP),%RCX

  (986) 0x451324 MOV	%R9,(%RCX,%RSI,8)

  (986) 0x451328 MOV	-0xc0(%RBP),%RCX

  (986) 0x45132f MOV	0x8(%RCX,%R9,8),%RCX

  (986) 0x451334 JMP	451300

0x451336 NOPW	%CS:(%RAX,%RAX,1)

(974) 0x451340 MOV	-0xf0(%RBP),%RAX

(974) 0x451347 MOV	(%RAX,%R9,8),%RCX

(974) 0x45134b MOV	0x8(%RAX,%R9,8),%R11

(974) 0x451350 LEA	0x1(%RCX),%RDX

(974) 0x451354 VXORPD	%XMM1,%XMM1,%XMM1

(974) 0x451358 CMP	%R11,%RDX

(974) 0x45135b MOV	%RCX,-0x48(%RBP)

(974) 0x45135f VXORPD	%XMM0,%XMM0,%XMM0

(974) 0x451363 JGE	451780

(974) 0x451369 MOV	-0x58(%RBP),%RAX

(974) 0x45136d MOV	%R11,-0x38(%RBP)

(974) 0x451371 JMP	451394

0x451373 NOPW	%CS:(%RAX,%RAX,1)

  (981) 0x451380 MOV	-0x58(%RBP),%RAX

  (981) 0x451384 MOV	-0x30(%RBP),%R9

  (981) 0x451388 INC	%RDX

  (981) 0x45138b CMP	%R11,%RDX

  (981) 0x45138e JE	451780

  (981) 0x451394 MOV	-0x158(%RBP),%RSI

  (981) 0x45139b MOV	(%RSI,%RDX,8),%RSI

  (981) 0x45139f MOV	-0x70(%RBP),%RDI

  (981) 0x4513a3 CMP	%R9,(%RDI,%RSI,8)

  (981) 0x4513a7 JNE	451400

  (981) 0x4513a9 MOV	-0x98(%RBP),%R8

  (981) 0x4513b0 MOV	(%R8,%RSI,8),%RDI

  (981) 0x4513b4 MOV	0x8(%R8,%RSI,8),%R8

  (981) 0x4513b9 MOV	%R8,%R9

  (981) 0x4513bc SUB	%RDI,%R9

  (981) 0x4513bf JLE	451588

  (981) 0x4513c5 CMP	$0x4,%R9

  (981) 0x4513c9 JAE	451440

  (981) 0x4513cb JMP	451519

0x4513d0 NOPW	%CS:(%RAX,%RAX,1)

0x4513df NOPW	%CS:(%RAX,%RAX,1)

0x4513ee NOPW	%CS:(%RAX,%RAX,1)

0x4513fd NOPL	(%RAX)

  (981) 0x451400 MOV	-0x140(%RBP),%RDI

  (981) 0x451407 CMPQ	$-0x3,(%RDI,%RSI,8)

  (981) 0x45140c JE	451388

  (981) 0x451412 CMPQ	$0x1,-0xc8(%RBP)

  (981) 0x45141a JE	451431

  (981) 0x45141c MOV	-0xa8(%RBP),%R8

  (981) 0x451423 MOV	(%R8,%R9,8),%RDI

  (981) 0x451427 CMP	(%R8,%RSI,8),%RDI

  (981) 0x45142b JNE	451388

  (981) 0x451431 VADDSD	(%RBX,%RDX,8),%XMM0,%XMM0

  (981) 0x451436 JMP	451388

0x45143b NOPL	(%RAX,%RAX,1)

  (981) 0x451440 MOV	%R9,%R10

  (981) 0x451443 SHR	$0x2,%R10

  (981) 0x451447 LEA	0x18(,%RDI,8),%R11

  (981) 0x45144f MOV	%R12,%RCX

  (981) 0x451452 NOPW	%CS:(%RAX,%RAX,1)

    (984) 0x451460 MOV	-0x18(%RAX,%R11,1),%R12

    (984) 0x451465 VMOVSD	-0x18(%R14,%R11,1),%XMM2

    (984) 0x45146c VMOVSD	(%RBX,%RDX,8),%XMM3

    (984) 0x451471 MOV	(%RCX,%R12,8),%R12

    (984) 0x451475 VMOVSD	(%R14,%R12,8),%XMM4

    (984) 0x45147b VFMADD231SD	%XMM2,%XMM3,%XMM4

    (984) 0x451480 VMOVSD	%XMM4,(%R14,%R12,8)

    (984) 0x451486 MOV	-0x10(%RAX,%R11,1),%R12

    (984) 0x45148b VMOVSD	-0x10(%R14,%R11,1),%XMM4

    (984) 0x451492 VMOVSD	(%RBX,%RDX,8),%XMM5

    (984) 0x451497 MOV	(%RCX,%R12,8),%R12

    (984) 0x45149b VMOVSD	(%R14,%R12,8),%XMM6

    (984) 0x4514a1 VFMADD231SD	%XMM4,%XMM5,%XMM6

    (984) 0x4514a6 VMOVSD	%XMM6,(%R14,%R12,8)

    (984) 0x4514ac MOV	-0x8(%RAX,%R11,1),%R12

    (984) 0x4514b1 VMOVSD	-0x8(%R14,%R11,1),%XMM6

    (984) 0x4514b8 VMOVSD	(%RBX,%RDX,8),%XMM7

    (984) 0x4514bd MOV	(%RCX,%R12,8),%R12

    (984) 0x4514c1 VMOVSD	(%R14,%R12,8),%XMM8

    (984) 0x4514c7 VFMADD231SD	%XMM6,%XMM7,%XMM8

    (984) 0x4514cc VMOVSD	%XMM8,(%R14,%R12,8)

    (984) 0x4514d2 VMOVSD	(%R14,%R11,1),%XMM8

    (984) 0x4514d8 VMULSD	(%RBX,%RDX,8),%XMM8,%XMM18

    (984) 0x4514df MOV	(%RAX,%R11,1),%R12

    (984) 0x4514e3 MOV	(%RCX,%R12,8),%R12

    (984) 0x4514e7 VADDSD	(%R14,%R12,8),%XMM18,%XMM8

    (984) 0x4514ee VMOVSD	%XMM8,(%R14,%R12,8)

    (984) 0x4514f4 VFMADD213SD	%XMM18,%XMM5,%XMM4

    (984) 0x4514fa VFMADD231SD	%XMM2,%XMM3,%XMM4

    (984) 0x4514ff VFMADD231SD	%XMM6,%XMM7,%XMM4

    (984) 0x451504 VADDSD	%XMM1,%XMM4,%XMM1

    (984) 0x451508 VADDSD	%XMM0,%XMM4,%XMM0

    (984) 0x45150c ADD	$0x20,%R11

    (984) 0x451510 DEC	%R10

    (984) 0x451513 JNE	451460

  (981) 0x451519 MOV	%R9,%R10

  (981) 0x45151c AND	$-0x4,%R10

  (981) 0x451520 CMP	%R9,%R10

  (981) 0x451523 MOV	-0x38(%RBP),%R11

  (981) 0x451527 JAE	451580

  (981) 0x451529 ADD	%R10,%RDI

  (981) 0x45152c MOV	-0x40(%RBP),%R10

  (981) 0x451530 MOV	-0x50(%RBP),%R12

  (981) 0x451534 NOPW	%CS:(%RAX,%RAX,1)

    (985) 0x451540 MOV	(%RAX,%RDI,8),%R9

    (985) 0x451544 VMOVSD	(%R14,%RDI,8),%XMM2

    (985) 0x45154a VMULSD	(%RBX,%RDX,8),%XMM2,%XMM18

    (985) 0x451551 MOV	(%R12,%R9,8),%R9

    (985) 0x451555 VADDSD	(%R14,%R9,8),%XMM18,%XMM2

    (985) 0x45155c VMOVSD	%XMM2,(%R14,%R9,8)

    (985) 0x451562 VADDSD	%XMM1,%XMM18,%XMM1

    (985) 0x451568 VADDSD	%XMM0,%XMM18,%XMM0

    (985) 0x45156e INC	%RDI

    (985) 0x451571 CMP	%RDI,%R8

    (985) 0x451574 JNE	451540

  (981) 0x451576 JMP	451588

0x451578 NOPL	(%RAX,%RAX,1)

  (981) 0x451580 MOV	-0x40(%RBP),%R10

  (981) 0x451584 MOV	-0x50(%RBP),%R12

  (981) 0x451588 MOV	-0xa0(%RBP),%RAX

  (981) 0x45158f MOV	(%RAX,%RSI,8),%RDI

  (981) 0x451593 MOV	0x8(%RAX,%RSI,8),%RSI

  (981) 0x451598 MOV	%RSI,%R8

  (981) 0x45159b SUB	%RDI,%R8

  (981) 0x45159e JLE	451380

  (981) 0x4515a4 CMP	$0x4,%R8

  (981) 0x4515a8 JAE	4515c0

  (981) 0x4515aa JMP	4516a2

0x4515af NOPW	%CS:(%RAX,%RAX,1)

0x4515be XCHG	%AX,%AX

  (981) 0x4515c0 MOV	%R8,%R9

  (981) 0x4515c3 SHR	$0x2,%R9

  (981) 0x4515c7 MOV	%R10,%RAX

  (981) 0x4515ca LEA	0x18(,%RDI,8),%R10

  (981) 0x4515d2 NOPW	%CS:(%RAX,%RAX,1)

    (982) 0x4515e0 MOV	-0x18(%RAX,%R10,1),%R11

    (982) 0x4515e5 VMOVSD	-0x18(%R13,%R10,1),%XMM2

    (982) 0x4515ec VMOVSD	(%RBX,%RDX,8),%XMM3

    (982) 0x4515f1 MOV	(%R15,%R11,8),%R11

    (982) 0x4515f5 VMOVSD	(%R13,%R11,8),%XMM4

    (982) 0x4515fc VFMADD231SD	%XMM2,%XMM3,%XMM4

    (982) 0x451601 VMOVSD	%XMM4,(%R13,%R11,8)

    (982) 0x451608 MOV	-0x10(%RAX,%R10,1),%R11

    (982) 0x45160d VMOVSD	-0x10(%R13,%R10,1),%XMM4

    (982) 0x451614 VMOVSD	(%RBX,%RDX,8),%XMM5

    (982) 0x451619 MOV	(%R15,%R11,8),%R11

    (982) 0x45161d VMOVSD	(%R13,%R11,8),%XMM6

    (982) 0x451624 VFMADD231SD	%XMM4,%XMM5,%XMM6

    (982) 0x451629 VMOVSD	%XMM6,(%R13,%R11,8)

    (982) 0x451630 MOV	-0x8(%RAX,%R10,1),%R11

    (982) 0x451635 VMOVSD	-0x8(%R13,%R10,1),%XMM6

    (982) 0x45163c VMOVSD	(%RBX,%RDX,8),%XMM7

    (982) 0x451641 MOV	(%R15,%R11,8),%R11

    (982) 0x451645 VMOVSD	(%R13,%R11,8),%XMM8

    (982) 0x45164c VFMADD231SD	%XMM6,%XMM7,%XMM8

    (982) 0x451651 VMOVSD	%XMM8,(%R13,%R11,8)

    (982) 0x451658 VMOVSD	(%R13,%R10,1),%XMM8

    (982) 0x45165f VMULSD	(%RBX,%RDX,8),%XMM8,%XMM18

    (982) 0x451666 MOV	(%RAX,%R10,1),%R11

    (982) 0x45166a MOV	(%R15,%R11,8),%R11

    (982) 0x45166e VADDSD	(%R13,%R11,8),%XMM18,%XMM8

    (982) 0x451676 VMOVSD	%XMM8,(%R13,%R11,8)

    (982) 0x45167d VFMADD213SD	%XMM18,%XMM5,%XMM4

    (982) 0x451683 VFMADD231SD	%XMM2,%XMM3,%XMM4

    (982) 0x451688 VFMADD231SD	%XMM6,%XMM7,%XMM4

    (982) 0x45168d VADDSD	%XMM1,%XMM4,%XMM1

    (982) 0x451691 VADDSD	%XMM0,%XMM4,%XMM0

    (982) 0x451695 ADD	$0x20,%R10

    (982) 0x451699 DEC	%R9

    (982) 0x45169c JNE	4515e0

  (981) 0x4516a2 MOV	%R8,%R9

  (981) 0x4516a5 AND	$-0x4,%R9

  (981) 0x4516a9 CMP	%R8,%R9

  (981) 0x4516ac JAE	451740

  (981) 0x4516b2 ADD	%R9,%RDI

  (981) 0x4516b5 MOV	-0x40(%RBP),%R10

  (981) 0x4516b9 MOV	-0x58(%RBP),%RAX

  (981) 0x4516bd MOV	-0x30(%RBP),%R9

  (981) 0x4516c1 MOV	-0x38(%RBP),%R11

  (981) 0x4516c5 NOPW	%CS:(%RAX,%RAX,1)

    (983) 0x4516d0 MOV	(%R10,%RDI,8),%R8

    (983) 0x4516d4 VMOVSD	(%R13,%RDI,8),%XMM2

    (983) 0x4516db VMULSD	(%RBX,%RDX,8),%XMM2,%XMM18

    (983) 0x4516e2 MOV	(%R15,%R8,8),%R8

    (983) 0x4516e6 VADDSD	(%R13,%R8,8),%XMM18,%XMM2

    (983) 0x4516ee VMOVSD	%XMM2,(%R13,%R8,8)

    (983) 0x4516f5 VADDSD	%XMM1,%XMM18,%XMM1

    (983) 0x4516fb VADDSD	%XMM0,%XMM18,%XMM0

    (983) 0x451701 INC	%RDI

    (983) 0x451704 CMP	%RDI,%RSI

    (983) 0x451707 JNE	4516d0

  (981) 0x451709 JMP	451388

0x45170e NOPW	%CS:(%RAX,%RAX,1)

0x45171d NOPW	%CS:(%RAX,%RAX,1)

0x45172c NOPW	%CS:(%RAX,%RAX,1)

0x45173b NOPL	(%RAX,%RAX,1)

  (981) 0x451740 MOV	-0x40(%RBP),%R10

  (981) 0x451744 MOV	-0x58(%RBP),%RAX

  (981) 0x451748 MOV	-0x30(%RBP),%R9

  (981) 0x45174c MOV	-0x38(%RBP),%R11

  (981) 0x451750 JMP	451388

0x451755 NOPW	%CS:(%RAX,%RAX,1)

0x451764 NOPW	%CS:(%RAX,%RAX,1)

0x451773 NOPW	%CS:(%RAX,%RAX,1)

(974) 0x451780 MOV	-0xf8(%RBP),%RAX

(974) 0x451787 MOV	(%RAX,%R9,8),%RCX

(974) 0x45178b MOV	0x8(%RAX,%R9,8),%RDX

(974) 0x451790 CMP	%RDX,%RCX

(974) 0x451793 JL	451860

(974) 0x451799 MOV	-0x48(%RBP),%RAX

(974) 0x45179d VMULSD	(%RBX,%RAX,8),%XMM1,%XMM1

(974) 0x4517a2 VUCOMISD	%XMM16,%XMM1

(974) 0x4517a8 JE	4517b6

(974) 0x4517aa VXORPD	%XMM17,%XMM0,%XMM0

(974) 0x4517b0 VDIVSD	%XMM1,%XMM0,%XMM18

(974) 0x4517b6 MOV	-0x98(%RBP),%RAX

(974) 0x4517bd MOV	(%RAX,%R9,8),%RDX

(974) 0x4517c1 MOV	0x8(%RAX,%R9,8),%RAX

(974) 0x4517c6 MOV	%RAX,%RSI

(974) 0x4517c9 SUB	%RDX,%RSI

(974) 0x4517cc JLE	4519e5

(974) 0x4517d2 MOV	%RSI,%RCX

(974) 0x4517d5 AND	$-0x4,%RCX

(974) 0x4517d9 JE	4519c0

(974) 0x4517df LEA	-0x1(%RCX),%RDI

(974) 0x4517e3 VBROADCASTSD	%XMM18,%YMM0

(974) 0x4517e9 LEA	(%R14,%RDX,8),%R8

(974) 0x4517ed XOR	%R9D,%R9D

  (978) 0x4517f0 VMULPD	(%R8,%R9,8),%YMM0,%YMM1

  (978) 0x4517f6 VMOVUPD	%YMM1,(%R8,%R9,8)

  (978) 0x4517fc ADD	$0x4,%R9

  (978) 0x451800 CMP	%RDI,%R9

  (978) 0x451803 JBE	4517f0

(974) 0x451805 CMP	%RCX,%RSI

(974) 0x451808 MOV	-0x30(%RBP),%R9

(974) 0x45180c JNE	4519c2

(974) 0x451812 JMP	4519e5

0x451817 NOPW	%CS:(%RAX,%RAX,1)

0x451826 NOPW	%CS:(%RAX,%RAX,1)

0x451835 NOPW	%CS:(%RAX,%RAX,1)

  (979) 0x451840 VADDSD	(%R8,%RCX,8),%XMM0,%XMM0

  (979) 0x451846 MOV	%R12,%R11

  (979) 0x451849 INC	%RCX

  (979) 0x45184c CMP	%RDX,%RCX

  (979) 0x45184f MOV	-0x40(%RBP),%R10

  (979) 0x451853 MOV	%R11,%R12

  (979) 0x451856 MOV	-0x30(%RBP),%R9

  (979) 0x45185a JE	451799

  (979) 0x451860 MOV	-0x160(%RBP),%RAX

  (979) 0x451867 LEA	(%RAX,%RCX,8),%RSI

  (979) 0x45186b CMPQ	$0,-0x188(%RBP)

  (979) 0x451873 JE	451883

  (979) 0x451875 MOV	(%RSI),%RSI

  (979) 0x451878 MOV	-0x148(%RBP),%RDI

  (979) 0x45187f LEA	(%RDI,%RSI,8),%RSI

  (979) 0x451883 MOV	(%RSI),%RDI

  (979) 0x451886 TEST	%RDI,%RDI

  (979) 0x451889 JS	451940

  (979) 0x45188f MOV	-0x68(%RBP),%RSI

  (979) 0x451893 CMP	%R9,(%RSI,%RDI,8)

  (979) 0x451897 JNE	451940

  (979) 0x45189d MOV	-0x138(%RBP),%RSI

  (979) 0x4518a4 MOV	0x8(%RSI,%RDI,8),%RSI

  (979) 0x4518a9 TEST	%RSI,%RSI

  (979) 0x4518ac JLE	451846

  (979) 0x4518ae MOV	-0x120(%RBP),%R8

  (979) 0x4518b5 MOV	(%R8,%RDI,8),%RDI

  (979) 0x4518b9 ADD	%RDI,%RSI

  (979) 0x4518bc MOV	-0x60(%RBP),%R8

  (979) 0x4518c0 MOV	(%R8),%R8

  (979) 0x4518c3 MOV	-0x128(%RBP),%R9

  (979) 0x4518ca MOV	(%R9,%R8,8),%R8

  (979) 0x4518ce MOV	%R12,%R11

  (979) 0x4518d1 MOV	-0xb0(%RBP),%R12

  (979) 0x4518d8 MOV	-0x130(%RBP),%RAX

  (979) 0x4518df NOP

    (980) 0x4518e0 MOV	(%R8,%RDI,8),%R9

    (980) 0x4518e4 VMOVSD	(%RAX,%RDI,8),%XMM2

    (980) 0x4518e9 VMULSD	(%R12,%RCX,8),%XMM2,%XMM18

    (980) 0x4518f0 TEST	%R9,%R9

    (980) 0x4518f3 LEA	(%R15,%R9,8),%R10

    (980) 0x4518f7 NOT	%R9

    (980) 0x4518fa LEA	(%R11,%R9,8),%R9

    (980) 0x4518fe CMOVNS	%R10,%R9

    (980) 0x451902 MOV	%R13,%R10

    (980) 0x451905 CMOVS	%R14,%R10

    (980) 0x451909 MOV	(%R9),%R9

    (980) 0x45190c VADDSD	(%R10,%R9,8),%XMM18,%XMM2

    (980) 0x451913 VMOVSD	%XMM2,(%R10,%R9,8)

    (980) 0x451919 VADDSD	%XMM1,%XMM18,%XMM1

    (980) 0x45191f VADDSD	%XMM0,%XMM18,%XMM0

    (980) 0x451925 INC	%RDI

    (980) 0x451928 CMP	%RSI,%RDI

    (980) 0x45192b JL	4518e0

  (979) 0x45192d JMP	451849

0x451932 NOPW	%CS:(%RAX,%RAX,1)

  (979) 0x451940 MOV	-0x150(%RBP),%RSI

  (979) 0x451947 CMPQ	$-0x3,(%RSI,%RDI,8)

  (979) 0x45194c JE	451846

  (979) 0x451952 CMPQ	$0x1,-0xc8(%RBP)

  (979) 0x45195a MOV	-0xb0(%RBP),%R8

  (979) 0x451961 JE	451840

  (979) 0x451967 MOV	-0x118(%RBP),%RSI

  (979) 0x45196e MOV	(%RSI,%RDI,8),%RSI

  (979) 0x451972 MOV	-0xa8(%RBP),%RDI

  (979) 0x451979 CMP	(%RDI,%R9,8),%RSI

  (979) 0x45197d JE	451840

  (979) 0x451983 JMP	451846

0x451988 NOPW	%CS:(%RAX,%RAX,1)

0x451997 NOPW	%CS:(%RAX,%RAX,1)

0x4519a6 NOPW	%CS:(%RAX,%RAX,1)

0x4519b5 NOPW	%CS:(%RAX,%RAX,1)

(974) 0x4519c0 XOR	%ECX,%ECX

(974) 0x4519c2 ADD	%RDX,%RCX

(974) 0x4519c5 NOPW	%CS:(%RAX,%RAX,1)

  (977) 0x4519d0 VMULSD	(%R14,%RCX,8),%XMM18,%XMM0

  (977) 0x4519d7 VMOVSD	%XMM0,(%R14,%RCX,8)

  (977) 0x4519dd INC	%RCX

  (977) 0x4519e0 CMP	%RCX,%RAX

  (977) 0x4519e3 JNE	4519d0

(974) 0x4519e5 MOV	-0xa0(%RBP),%RAX

(974) 0x4519ec MOV	(%RAX,%R9,8),%RDX

(974) 0x4519f0 MOV	0x8(%RAX,%R9,8),%RAX

(974) 0x4519f5 MOV	%RAX,%RSI

(974) 0x4519f8 SUB	%RDX,%RSI

(974) 0x4519fb JLE	450e40

(974) 0x451a01 MOV	%RSI,%RCX

(974) 0x451a04 AND	$-0x4,%RCX

(974) 0x451a08 JE	451a40

(974) 0x451a0a LEA	-0x1(%RCX),%RDI

(974) 0x451a0e VBROADCASTSD	%XMM18,%YMM0

(974) 0x451a14 LEA	(%R13,%RDX,8),%R8

(974) 0x451a19 XOR	%R9D,%R9D

(974) 0x451a1c NOPL	(%RAX)

  (976) 0x451a20 VMULPD	(%R8,%R9,8),%YMM0,%YMM1

  (976) 0x451a26 VMOVUPD	%YMM1,(%R8,%R9,8)

  (976) 0x451a2c ADD	$0x4,%R9

  (976) 0x451a30 CMP	%RDI,%R9

  (976) 0x451a33 JBE	451a20

(974) 0x451a35 CMP	%RCX,%RSI

(974) 0x451a38 JE	450e40

(974) 0x451a3e JMP	451a42

(974) 0x451a40 XOR	%ECX,%ECX

(974) 0x451a42 ADD	%RDX,%RCX

(974) 0x451a45 NOPW	%CS:(%RAX,%RAX,1)

  (975) 0x451a50 VMULSD	(%R13,%RCX,8),%XMM18,%XMM0

  (975) 0x451a58 VMOVSD	%XMM0,(%R13,%RCX,8)

  (975) 0x451a5f INC	%RCX

  (975) 0x451a62 CMP	%RCX,%RAX

  (975) 0x451a65 JNE	451a50

(974) 0x451a67 JMP	450e40

0x451a6c NOPW	%CS:(%RAX,%RAX,1)

0x451a7b NOPL	(%RAX,%RAX,1)

0x451a80 MOV	-0x70(%RBP),%RDI

0x451a84 VZEROUPPER

0x451a87 CALL	51b990 <hypre_Free>

0x451a8c MOV	-0x68(%RBP),%RDI

0x451a90 CALL	51b990 <hypre_Free>

0x451a95 MOV	%R12,%RDI

0x451a98 CALL	51b990 <hypre_Free>

0x451a9d MOV	%R15,%RDI

0x451aa0 ADD	$0x168,%RSP

0x451aa7 POP	%RBX

0x451aa8 POP	%R12

0x451aaa POP	%R13

0x451aac POP	%R14

0x451aae POP	%R15

0x451ab0 POP	%RBP

0x451ab1 JMP	51b990

0x451ab6 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►99.65+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_4

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1747-1754,1760-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 42.67 to 4.50 cycles (9.48x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 42.67 to 6.50 cycles (6.56x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__intel_avx_rep_memset: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1761
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1763
hypre_CAlloc: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1748
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1751
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1754
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1753
hypre_Free: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1878
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1879
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1880
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1766
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1767

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1768
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1768
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1878

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1768

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 448 bytes. The binary function is storing 376 bytes.

General properties

nb instructions	237
nb uops	256
loop length	1447
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	80

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	42.67 cycles
front end	42.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.90	8.80	20.67	20.67	32.00	8.80	8.70	32.00	32.00	32.00	8.80	20.67
cycles	8.90	12.20	20.67	20.67	32.00	8.80	8.70	32.00	32.00	32.00	8.80	20.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

16.00

Cycles summary

Front-end	42.67
Dispatch	32.00
DIV/SQRT	16.00
Overall L1	42.67

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	3%

all	50%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	6%

Vector efficiency ratios

INT

all	11%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	18%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	9%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 42.67 cycles. At this rate:

5% of peak load performance is reached (10.50 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.81 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 42.67 to 32.00 cycles (1.33x speedup).

ASM code

In the binary file, the address of the function is: 450ab0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x168,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,-0x188(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x140(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x138(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x130(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x128(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x120(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x180(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x118(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x178(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x110(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x108(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x100(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xf8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xf0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x148(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xe8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x138(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xe0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x128(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x108(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xb8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x118(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x150(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x98(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x90(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x88(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x80(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x78(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x70(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x68(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x60(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x170(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x168(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x160(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x158(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TEST %RDI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 450d00 <hypre_BoomerAMGBuildMultipass.extracted.28+0x250>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 51b840 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 450d0d <hypre_BoomerAMGBuildMultipass.extracted.28+0x25d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 51b840 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %R12,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 450d1a <hypre_BoomerAMGBuildMultipass.extracted.28+0x26a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 51b840 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 450d1d <hypre_BoomerAMGBuildMultipass.extracted.28+0x26d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 450cae <hypre_BoomerAMGBuildMultipass.extracted.28+0x1fe>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %R12,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 450cc4 <hypre_BoomerAMGBuildMultipass.extracted.28+0x214>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R15,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVG %RAX,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 51b840 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x90(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 450d56 <hypre_BoomerAMGBuildMultipass.extracted.28+0x2a6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV -0x70(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 5277f0 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 450d71 <hypre_BoomerAMGBuildMultipass.extracted.28+0x2c1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV -0x68(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 5277f0 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
CALL 51da60 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 51da50 <hypre_NumActiveThreads>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RAX,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x38(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x20,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JE 450dc0 <hypre_BoomerAMGBuildMultipass.extracted.28+0x310>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RCX	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
JMP 450dc7 <hypre_BoomerAMGBuildMultipass.extracted.28+0x317>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %ECX	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV -0x40(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R9,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DEC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA 0x1(%R9),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RAX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
CMP %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVE %R8,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 451a80 <hypre_BoomerAMGBuildMultipass.extracted.28+0xfd0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x88(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x38,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x38(%R10),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VXORPD %XMM16,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVDDUP 0xd9d8a(%RIP),%XMM17	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R12,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 450e57 <hypre_BoomerAMGBuildMultipass.extracted.28+0x3a7>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x70(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 51b990 <hypre_Free>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x68(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CALL 51b990 <hypre_Free>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 51b990 <hypre_Free>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD $0x168,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 51b990 <hypre_Free>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_4

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1747-1754,1760-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 42.67 to 4.50 cycles (9.48x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__intel_avx_rep_memset: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1761
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1763
hypre_CAlloc: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1748
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1751
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1754
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1753
hypre_Free: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1878
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1879
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1880
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1766
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1767

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1768
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1768
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1878

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1768

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 448 bytes. The binary function is storing 376 bytes.

General properties

nb instructions	237
nb uops	256
loop length	1447
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	80

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	42.67 cycles
front end	42.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.90	8.80	20.67	20.67	32.00	8.80	8.70	32.00	32.00	32.00	8.80	20.67
cycles	8.90	12.20	20.67	20.67	32.00	8.80	8.70	32.00	32.00	32.00	8.80	20.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

16.00

Cycles summary

Front-end	42.67
Dispatch	32.00
DIV/SQRT	16.00
Overall L1	42.67

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	3%

all	50%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	6%

Vector efficiency ratios

INT

all	11%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	18%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	9%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 42.67 cycles. At this rate:

5% of peak load performance is reached (10.50 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.81 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 450ab0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x168,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,-0x188(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x140(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x138(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x130(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x128(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x120(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x180(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x118(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x178(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x110(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x108(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x100(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xf8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xf0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x148(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xe8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x138(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xe0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x128(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x108(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xb8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x118(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x150(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x98(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x90(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x88(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x80(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x78(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x70(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x68(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x60(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x170(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x168(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x160(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x158(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TEST %RDI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 450d00 <hypre_BoomerAMGBuildMultipass.extracted.28+0x250>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 51b840 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 450d0d <hypre_BoomerAMGBuildMultipass.extracted.28+0x25d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 51b840 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %R12,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 450d1a <hypre_BoomerAMGBuildMultipass.extracted.28+0x26a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 51b840 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 450d1d <hypre_BoomerAMGBuildMultipass.extracted.28+0x26d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 450cae <hypre_BoomerAMGBuildMultipass.extracted.28+0x1fe>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %R12,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 450cc4 <hypre_BoomerAMGBuildMultipass.extracted.28+0x214>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R15,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVG %RAX,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 51b840 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x90(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 450d56 <hypre_BoomerAMGBuildMultipass.extracted.28+0x2a6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV -0x70(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 5277f0 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 450d71 <hypre_BoomerAMGBuildMultipass.extracted.28+0x2c1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV -0x68(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 5277f0 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
CALL 51da60 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 51da50 <hypre_NumActiveThreads>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RAX,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x38(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x20,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JE 450dc0 <hypre_BoomerAMGBuildMultipass.extracted.28+0x310>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RCX	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
JMP 450dc7 <hypre_BoomerAMGBuildMultipass.extracted.28+0x317>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %ECX	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV -0x40(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R9,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
DEC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA 0x1(%R9),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RAX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
CMP %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVE %R8,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 451a80 <hypre_BoomerAMGBuildMultipass.extracted.28+0xfd0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x88(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x38,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x38(%R10),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VXORPD %XMM16,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVDDUP 0xd9d8a(%RIP),%XMM17	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R12,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 450e57 <hypre_BoomerAMGBuildMultipass.extracted.28+0x3a7>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x70(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 51b990 <hypre_Free>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x68(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CALL 51b990 <hypre_Free>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 51b990 <hypre_Free>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD $0x168,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 51b990 <hypre_Free>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass.extracted.28–	1.43	0.75
▼Loop 974 - par_multi_interp.c:1747-1876 - exec–	0.14	0.06
▼Loop 981 - par_multi_interp.c:1747-1837 - exec–	0.48	0.20
○Loop 985 - par_multi_interp.c:1816-1822 - exec	0.31	0.13
○Loop 984 - par_multi_interp.c:1816-1820 - exec	0.00	0.01
○Loop 983 - par_multi_interp.c:1824-1830 - exec	0.00	0.01
○Loop 982 - par_multi_interp.c:1824-1828 - exec	0.00	0.00
○Loop 987 - par_multi_interp.c:1799-1803 - exec	0.47	0.20
○Loop 991 - par_multi_interp.c:1782-1787 - exec	0.02	0.01
○Loop 977 - par_multi_interp.c:1873-1874 - exec	0.00	0.01
▼Loop 979 - par_multi_interp.c:1836-1867 - exec–	0.00	0.01
○Loop 980 - par_multi_interp.c:1851-1860 - exec	0.00	0.00
○Loop 978 - par_multi_interp.c:1873-1874 - exec	0.00	0.01
○Loop 986 - par_multi_interp.c:1805-1809 - exec	0.00	0.00
○Loop 989 - par_multi_interp.c:1792-1797 - exec	0.00	0.00
○Loop 976 - par_multi_interp.c:1875-1876 - exec	0.00	0.00
○Loop 975 - par_multi_interp.c:1875-1876 - exec	0.00	0.00
○Loop 993 - par_multi_interp.c:1782-1787 - exec	0.00	0.00
○Loop 990 - par_multi_interp.c:1792-1797 - exec	0.00	0.00
○Loop 992 - par_multi_interp.c:1782-1787 - exec	0.00	0.00
○Loop 988 - par_multi_interp.c:1792-1797 - exec	0.00	0.00

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Matching between your function (in the source code) and the binary function

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Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code