OV - exec - Function hypre_BoomerAMGBuildMultipass.extracted.27

	Function: hypre_BoomerAMGBuildMultipass.extracted.27	Module: exec	Source: par_multi_interp.c:1575-1663 [...]	Coverage (incl. loops): 0.36% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1575 - 1663

--------------------------------------------------------------------------------

1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa)

[...]

1585:            if (n_fine)

1586:            {   tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); }

1587:            tmp_marker_offd = NULL;

1588:            if (num_cols_offd)

1589:            {   tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1590:            for (i=0; i < n_fine; i++)

1591:            {   tmp_marker[i] = -1; }

1592:            for (i=0; i < num_cols_offd; i++)

1593:            {   tmp_marker_offd[i] = -1; }

1594:

1595:            /* Compute this thread's range of pass_length */

1596:            my_thread_num = hypre_GetThreadNum();

1597:            num_threads = hypre_NumActiveThreads();

1598:            thread_start = pass_pointer[1] + (pass_length/num_threads)*my_thread_num;

1599:            if (my_thread_num == num_threads-1)

[...]

1605:            for (i=thread_start; i < thread_stop; i++)

1606:            {

1607:              i1 = pass_array[i];

1608:              sum_C = 0;

1609:              sum_N = 0;

1610:              j_start = P_diag_start[i1];

1611:              j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1612:              for (j=j_start; j < j_end; j++)

1613:              {

1614:                 k1 = P_diag_pass[1][j];

1615:                 tmp_marker[C_array[k1]] = i1;

1616:              }

1617:              cnt = P_diag_i[i1];

1618:              for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1619:              {

1620:                 j1 = A_diag_j[j];

1621:                 if (CF_marker[j1] != -3 &&

1622:                    (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1623:                    sum_N += A_diag_data[j];

1624:                 if (j1 != -1 && tmp_marker[j1] == i1)

1625:                 {

1626:                    P_diag_data[cnt] = A_diag_data[j];

1627:                    P_diag_j[cnt++] = fine_to_coarse[j1];

1628:                    sum_C += A_diag_data[j];

1629:                 }

1630:              }

1631:              j_start = P_offd_start[i1];

1632:              j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1633:              for (j=j_start; j < j_end; j++)

1634:              {

1635:                 k1 = P_offd_pass[1][j];

1636:                 tmp_marker_offd[C_array_offd[k1]] = i1;

1637:              }

1638:              cnt_offd = P_offd_i[i1];

1639:              for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1640:              {

1641:                 if (col_offd_S_to_A)

1642:                     j1 = map_A_to_S[A_offd_j[j]];

1643:                 else

1644:                     j1 = A_offd_j[j];

1645:                 if (CF_marker_offd[j1] != -3 &&

1646:                   (num_functions == 1 || dof_func[i1] == dof_func_offd[j1]))

1647:                     sum_N += A_offd_data[j];

1648:                 if (j1 != -1 && tmp_marker_offd[j1] == i1)

1649:                 {

1650:                    P_offd_data[cnt_offd] = A_offd_data[j];

1651:                    P_offd_j[cnt_offd++] = map_S_to_new[j1];

1652:                    sum_C += A_offd_data[j];

1653:                 }

1654:              }

1655:              diagonal = A_diag_data[A_diag_i[i1]];

1656:              if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1657:              for (j=P_diag_i[i1]; j < cnt; j++)

1658:                 P_diag_data[j] *= alfa;

1659:              for (j=P_offd_i[i1]; j < cnt_offd; j++)

1660:                 P_offd_data[j] *= alfa;

1661:           }

1662:           hypre_TFree(tmp_marker);

1663:           hypre_TFree(tmp_marker_offd);

0x4501a0 PUSH	%RBP

0x4501a1 MOV	%RSP,%RBP

0x4501a4 PUSH	%R15

0x4501a6 PUSH	%R14

0x4501a8 PUSH	%R13

0x4501aa PUSH	%R12

0x4501ac PUSH	%RBX

0x4501ad SUB	$0xe8,%RSP

0x4501b4 MOV	%R9,-0xd0(%RBP)

0x4501bb MOV	%R8,-0x90(%RBP)

0x4501c2 MOV	%RCX,-0xa0(%RBP)

0x4501c9 MOV	%RDX,-0x40(%RBP)

0x4501cd MOV	0xe8(%RBP),%RAX

0x4501d4 MOV	%RAX,-0x50(%RBP)

0x4501d8 MOV	0xe0(%RBP),%RAX

0x4501df MOV	%RAX,-0x108(%RBP)

0x4501e6 MOV	0xd8(%RBP),%RDI

0x4501ed MOV	0xd0(%RBP),%RAX

0x4501f4 MOV	%RAX,-0x110(%RBP)

0x4501fb MOV	0xc8(%RBP),%RAX

0x450202 MOV	%RAX,-0x100(%RBP)

0x450209 MOV	0xc0(%RBP),%RAX

0x450210 MOV	%RAX,-0xc8(%RBP)

0x450217 MOV	0xb8(%RBP),%RAX

0x45021e MOV	%RAX,-0xc0(%RBP)

0x450225 MOV	0xb0(%RBP),%RAX

0x45022c MOV	%RAX,-0xe8(%RBP)

0x450233 MOV	0xa8(%RBP),%RAX

0x45023a MOV	%RAX,-0xe0(%RBP)

0x450241 MOV	0xa0(%RBP),%RAX

0x450248 MOV	%RAX,-0x38(%RBP)

0x45024c MOV	0x98(%RBP),%RAX

0x450253 MOV	%RAX,-0xd8(%RBP)

0x45025a MOV	0x90(%RBP),%RBX

0x450261 MOV	0x88(%RBP),%R15

0x450268 MOV	0x80(%RBP),%RAX

0x45026f MOV	%RAX,-0xf0(%RBP)

0x450276 MOV	0x78(%RBP),%R12

0x45027a MOV	0x70(%RBP),%RAX

0x45027e MOV	%RAX,-0xf8(%RBP)

0x450285 MOV	0x68(%RBP),%RAX

0x450289 MOV	%RAX,-0x60(%RBP)

0x45028d MOV	0x60(%RBP),%RAX

0x450291 MOV	%RAX,-0x48(%RBP)

0x450295 MOV	0x58(%RBP),%RAX

0x450299 MOV	%RAX,-0xb8(%RBP)

0x4502a0 MOV	0x50(%RBP),%RAX

0x4502a4 MOV	%RAX,-0x58(%RBP)

0x4502a8 MOV	0x48(%RBP),%RAX

0x4502ac MOV	%RAX,-0x88(%RBP)

0x4502b3 MOV	0x40(%RBP),%RCX

0x4502b7 MOV	0x38(%RBP),%RAX

0x4502bb MOV	%RAX,-0xb0(%RBP)

0x4502c2 MOV	0x30(%RBP),%RAX

0x4502c6 MOV	%RAX,-0x80(%RBP)

0x4502ca MOV	0x28(%RBP),%RAX

0x4502ce MOV	%RAX,-0x98(%RBP)

0x4502d5 MOV	0x20(%RBP),%RAX

0x4502d9 MOV	%RAX,-0x78(%RBP)

0x4502dd MOV	0x18(%RBP),%RAX

0x4502e1 MOV	%RAX,-0x68(%RBP)

0x4502e5 MOV	0x10(%RBP),%RAX

0x4502e9 MOV	%RAX,-0x70(%RBP)

0x4502ed TEST	%RDI,%RDI

0x4502f0 MOV	%RCX,-0x30(%RBP)

0x4502f4 MOV	%RDI,-0xa8(%RBP)

0x4502fb JE	4503c0

0x450301 MOV	$0x8,%ESI

0x450306 CALL	51b840 <hypre_CAlloc>

0x45030b MOV	-0x30(%RBP),%RCX

0x45030f MOV	%RAX,%R13

0x450312 TEST	%RCX,%RCX

0x450315 JE	4503cc

0x45031b MOV	$0x8,%ESI

0x450320 MOV	%RCX,%RDI

0x450323 CALL	51b840 <hypre_CAlloc>

0x450328 MOV	%RAX,%R14

0x45032b MOV	-0xa8(%RBP),%RDX

0x450332 TEST	%RDX,%RDX

0x450335 JLE	450348

0x450337 SAL	$0x3,%RDX

0x45033b MOV	%R13,%RDI

0x45033e MOV	$0xff,%ESI

0x450343 CALL	5277f0 <__intel_avx_rep_memset>

0x450348 MOV	-0x30(%RBP),%RDX

0x45034c TEST	%RDX,%RDX

0x45034f JLE	450362

0x450351 SAL	$0x3,%RDX

0x450355 MOV	%R14,%RDI

0x450358 MOV	$0xff,%ESI

0x45035d CALL	5277f0 <__intel_avx_rep_memset>

0x450362 CALL	51da60 <hypre_GetThreadNum>

0x450367 MOV	%RAX,-0x30(%RBP)

0x45036b CALL	51da50 <hypre_NumActiveThreads>

0x450370 MOV	%RAX,%RCX

0x450373 MOV	-0x38(%RBP),%RAX

0x450377 MOV	0x8(%RAX),%RDI

0x45037b MOV	-0x50(%RBP),%R8

0x45037f MOV	%R8,%RAX

0x450382 OR	%RCX,%RAX

0x450385 SHR	$0x20,%RAX

0x450389 JE	450400

0x45038b MOV	%R8,%RAX

0x45038e CQTO

0x450390 IDIV	%RCX

0x450393 JMP	450407

0x450395 NOPW	%CS:(%RAX,%RAX,1)

0x4503a4 NOPW	%CS:(%RAX,%RAX,1)

0x4503b3 NOPW	%CS:(%RAX,%RAX,1)

0x4503c0 XOR	%R13D,%R13D

0x4503c3 TEST	%RCX,%RCX

0x4503c6 JNE	45031b

0x4503cc XOR	%R14D,%R14D

0x4503cf MOV	-0xa8(%RBP),%RDX

0x4503d6 TEST	%RDX,%RDX

0x4503d9 JG	450337

0x4503df JMP	450348

0x4503e4 NOPW	%CS:(%RAX,%RAX,1)

0x4503f3 NOPW	%CS:(%RAX,%RAX,1)

0x450400 MOV	%R8D,%EAX

0x450403 XOR	%EDX,%EDX

0x450405 DIV	%ECX

0x450407 MOV	-0x40(%RBP),%R10

0x45040b MOV	%RAX,%RDX

0x45040e MOV	-0x30(%RBP),%R9

0x450412 IMUL	%R9,%RDX

0x450416 DEC	%RCX

0x450419 LEA	0x1(%R9),%RSI

0x45041d IMUL	%RAX,%RSI

0x450421 CMP	%RCX,%R9

0x450424 CMOVE	%R8,%RSI

0x450428 MOV	%RSI,-0x38(%RBP)

0x45042c CMP	%RSI,%RDX

0x45042f JGE	450a80

0x450435 MOV	-0x38(%RBP),%RAX

0x450439 ADD	%RDI,%RAX

0x45043c MOV	%RAX,-0x38(%RBP)

0x450440 ADD	%RDI,%RDX

0x450443 VXORPD	%XMM0,%XMM0,%XMM0

0x450447 VMOVDDUP	0xda771(%RIP),%XMM1

0x45044f JMP	450491

0x450451 NOPW	%CS:(%RAX,%RAX,1)

0x450460 NOPW	%CS:(%RAX,%RAX,1)

0x45046f NOPW	%CS:(%RAX,%RAX,1)

0x45047e XCHG	%AX,%AX

(963) 0x450480 MOV	-0x50(%RBP),%RDX

(963) 0x450484 INC	%RDX

(963) 0x450487 CMP	-0x38(%RBP),%RDX

(963) 0x45048b JGE	450a80

(963) 0x450491 MOV	-0xd8(%RBP),%RAX

(963) 0x450498 MOV	%RDX,-0x50(%RBP)

(963) 0x45049c MOV	(%RAX,%RDX,8),%RAX

(963) 0x4504a0 MOV	-0xe0(%RBP),%RCX

(963) 0x4504a7 MOV	(%RCX,%RAX,8),%RDI

(963) 0x4504ab MOV	-0x58(%RBP),%RCX

(963) 0x4504af MOV	(%RCX,%RAX,8),%RSI

(963) 0x4504b3 MOV	0x8(%RCX,%RAX,8),%RCX

(963) 0x4504b8 LEA	(%RCX,%RDI,1),%RDX

(963) 0x4504bc SUB	%RSI,%RDX

(963) 0x4504bf CMP	%RDX,%RDI

(963) 0x4504c2 JGE	450595

(963) 0x4504c8 MOV	-0xc0(%RBP),%RDX

(963) 0x4504cf MOV	0x8(%RDX),%R8

(963) 0x4504d3 SUB	%RSI,%RCX

(963) 0x4504d6 CMP	$0x8,%RCX

(963) 0x4504da JB	450560

(963) 0x4504e0 MOV	%RCX,%R9

(963) 0x4504e3 SHR	$0x3,%R9

(963) 0x4504e7 LEA	0x38(%R8,%RDI,8),%R10

(963) 0x4504ec NOPL	(%RAX)

  (973) 0x4504f0 MOV	-0x38(%R10),%RDX

  (973) 0x4504f4 MOV	(%R15,%RDX,8),%RDX

  (973) 0x4504f8 MOV	%RAX,(%R13,%RDX,8)

  (973) 0x4504fd MOV	-0x30(%R10),%RDX

  (973) 0x450501 MOV	(%R15,%RDX,8),%RDX

  (973) 0x450505 MOV	%RAX,(%R13,%RDX,8)

  (973) 0x45050a MOV	-0x28(%R10),%RDX

  (973) 0x45050e MOV	(%R15,%RDX,8),%RDX

  (973) 0x450512 MOV	%RAX,(%R13,%RDX,8)

  (973) 0x450517 MOV	-0x20(%R10),%RDX

  (973) 0x45051b MOV	(%R15,%RDX,8),%RDX

  (973) 0x45051f MOV	%RAX,(%R13,%RDX,8)

  (973) 0x450524 MOV	-0x18(%R10),%RDX

  (973) 0x450528 MOV	(%R15,%RDX,8),%RDX

  (973) 0x45052c MOV	%RAX,(%R13,%RDX,8)

  (973) 0x450531 MOV	-0x10(%R10),%RDX

  (973) 0x450535 MOV	(%R15,%RDX,8),%RDX

  (973) 0x450539 MOV	%RAX,(%R13,%RDX,8)

  (973) 0x45053e MOV	-0x8(%R10),%RDX

  (973) 0x450542 MOV	(%R15,%RDX,8),%RDX

  (973) 0x450546 MOV	%RAX,(%R13,%RDX,8)

  (973) 0x45054b MOV	(%R10),%RDX

  (973) 0x45054e MOV	(%R15,%RDX,8),%RDX

  (973) 0x450552 MOV	%RAX,(%R13,%RDX,8)

  (973) 0x450557 ADD	$0x40,%R10

  (973) 0x45055b DEC	%R9

  (973) 0x45055e JNE	4504f0

(963) 0x450560 MOV	%RCX,%R9

(963) 0x450563 AND	$-0x8,%R9

(963) 0x450567 CMP	%RCX,%R9

(963) 0x45056a MOV	-0x40(%RBP),%R10

(963) 0x45056e JAE	450595

(963) 0x450570 LEA	(%R8,%RDI,8),%RDI

(963) 0x450574 NOPW	%CS:(%RAX,%RAX,1)

  (972) 0x450580 MOV	(%RDI,%R9,8),%RDX

  (972) 0x450584 MOV	(%R15,%RDX,8),%RDX

  (972) 0x450588 MOV	%RAX,(%R13,%RDX,8)

  (972) 0x45058d INC	%R9

  (972) 0x450590 CMP	%R9,%RCX

  (972) 0x450593 JNE	450580

(963) 0x450595 MOV	-0x58(%RBP),%RCX

(963) 0x450599 MOV	(%RCX,%RAX,8),%RDX

(963) 0x45059d MOV	-0x68(%RBP),%RCX

(963) 0x4505a1 MOV	(%RCX,%RAX,8),%RDI

(963) 0x4505a5 MOV	0x8(%RCX,%RAX,8),%R8

(963) 0x4505aa INC	%RDI

(963) 0x4505ad VXORPD	%XMM4,%XMM4,%XMM4

(963) 0x4505b1 CMP	%R8,%RDI

(963) 0x4505b4 MOV	%RDX,-0x30(%RBP)

(963) 0x4505b8 VXORPD	%XMM3,%XMM3,%XMM3

(963) 0x4505bc JGE	4506c0

(963) 0x4505c2 MOV	-0xb8(%RBP),%RCX

(963) 0x4505c9 MOV	-0x78(%RBP),%RSI

(963) 0x4505cd JMP	45060c

0x4505cf NOPW	%CS:(%RAX,%RAX,1)

0x4505de NOPW	%CS:(%RAX,%RAX,1)

0x4505ed NOPW	%CS:(%RAX,%RAX,1)

0x4505fc NOPL	(%RAX)

  (971) 0x450600 INC	%RDI

  (971) 0x450603 CMP	%R8,%RDI

  (971) 0x450606 JGE	4506c0

  (971) 0x45060c MOV	(%RSI,%RDI,8),%R9

  (971) 0x450610 CMPQ	$-0x3,(%R10,%R9,8)

  (971) 0x450615 JE	45063f

  (971) 0x450617 CMPQ	$0x1,-0xa0(%RBP)

  (971) 0x45061f JE	450636

  (971) 0x450621 MOV	-0x90(%RBP),%RSI

  (971) 0x450628 MOV	(%RSI,%RAX,8),%RDX

  (971) 0x45062c CMP	(%RSI,%R9,8),%RDX

  (971) 0x450630 MOV	-0x78(%RBP),%RSI

  (971) 0x450634 JNE	45063f

  (971) 0x450636 MOV	-0x70(%RBP),%RDX

  (971) 0x45063a VADDSD	(%RDX,%RDI,8),%XMM3,%XMM3

  (971) 0x45063f CMP	$-0x1,%R9

  (971) 0x450643 JE	450600

  (971) 0x450645 CMP	%RAX,(%R13,%R9,8)

  (971) 0x45064a JNE	450600

  (971) 0x45064c MOV	-0x70(%RBP),%R8

  (971) 0x450650 VMOVSD	(%R8,%RDI,8),%XMM5

  (971) 0x450656 MOV	-0x88(%RBP),%RDX

  (971) 0x45065d MOV	-0x30(%RBP),%R11

  (971) 0x450661 VMOVSD	%XMM5,(%RDX,%R11,8)

  (971) 0x450667 MOV	-0x108(%RBP),%RDX

  (971) 0x45066e MOV	(%RDX,%R9,8),%RDX

  (971) 0x450672 MOV	%RDX,(%RCX,%R11,8)

  (971) 0x450676 INC	%R11

  (971) 0x450679 MOV	%R11,-0x30(%RBP)

  (971) 0x45067d VADDSD	(%R8,%RDI,8),%XMM4,%XMM4

  (971) 0x450683 MOV	-0x68(%RBP),%RDX

  (971) 0x450687 MOV	0x8(%RDX,%RAX,8),%R8

  (971) 0x45068c JMP	450600

0x450691 NOPW	%CS:(%RAX,%RAX,1)

0x4506a0 NOPW	%CS:(%RAX,%RAX,1)

0x4506af NOPW	%CS:(%RAX,%RAX,1)

0x4506be XCHG	%AX,%AX

(963) 0x4506c0 MOV	-0xe8(%RBP),%RDX

(963) 0x4506c7 MOV	(%RDX,%RAX,8),%R8

(963) 0x4506cb MOV	-0x60(%RBP),%RCX

(963) 0x4506cf MOV	(%RCX,%RAX,8),%RSI

(963) 0x4506d3 MOV	0x8(%RCX,%RAX,8),%RDI

(963) 0x4506d8 LEA	(%RDI,%R8,1),%RDX

(963) 0x4506dc SUB	%RSI,%RDX

(963) 0x4506df CMP	%RDX,%R8

(963) 0x4506e2 JGE	4507a4

(963) 0x4506e8 MOV	-0xc8(%RBP),%RDX

(963) 0x4506ef MOV	0x8(%RDX),%R9

(963) 0x4506f3 SUB	%RSI,%RDI

(963) 0x4506f6 CMP	$0x8,%RDI

(963) 0x4506fa JB	450778

(963) 0x450700 MOV	%RDI,%R10

(963) 0x450703 SHR	$0x3,%R10

(963) 0x450707 LEA	0x38(%R9,%R8,8),%R11

(963) 0x45070c NOPL	(%RAX)

  (970) 0x450710 MOV	-0x38(%R11),%RDX

  (970) 0x450714 MOV	(%RBX,%RDX,8),%RDX

  (970) 0x450718 MOV	%RAX,(%R14,%RDX,8)

  (970) 0x45071c MOV	-0x30(%R11),%RDX

  (970) 0x450720 MOV	(%RBX,%RDX,8),%RDX

  (970) 0x450724 MOV	%RAX,(%R14,%RDX,8)

  (970) 0x450728 MOV	-0x28(%R11),%RDX

  (970) 0x45072c MOV	(%RBX,%RDX,8),%RDX

  (970) 0x450730 MOV	%RAX,(%R14,%RDX,8)

  (970) 0x450734 MOV	-0x20(%R11),%RDX

  (970) 0x450738 MOV	(%RBX,%RDX,8),%RDX

  (970) 0x45073c MOV	%RAX,(%R14,%RDX,8)

  (970) 0x450740 MOV	-0x18(%R11),%RDX

  (970) 0x450744 MOV	(%RBX,%RDX,8),%RDX

  (970) 0x450748 MOV	%RAX,(%R14,%RDX,8)

  (970) 0x45074c MOV	-0x10(%R11),%RDX

  (970) 0x450750 MOV	(%RBX,%RDX,8),%RDX

  (970) 0x450754 MOV	%RAX,(%R14,%RDX,8)

  (970) 0x450758 MOV	-0x8(%R11),%RDX

  (970) 0x45075c MOV	(%RBX,%RDX,8),%RDX

  (970) 0x450760 MOV	%RAX,(%R14,%RDX,8)

  (970) 0x450764 MOV	(%R11),%RDX

  (970) 0x450767 MOV	(%RBX,%RDX,8),%RDX

  (970) 0x45076b MOV	%RAX,(%R14,%RDX,8)

  (970) 0x45076f ADD	$0x40,%R11

  (970) 0x450773 DEC	%R10

  (970) 0x450776 JNE	450710

(963) 0x450778 MOV	%RDI,%R10

(963) 0x45077b AND	$-0x8,%R10

(963) 0x45077f CMP	%RDI,%R10

(963) 0x450782 JAE	4507a4

(963) 0x450784 LEA	(%R9,%R8,8),%R8

(963) 0x450788 NOPL	(%RAX,%RAX,1)

  (969) 0x450790 MOV	(%R8,%R10,8),%RDX

  (969) 0x450794 MOV	(%RBX,%RDX,8),%RDX

  (969) 0x450798 MOV	%RAX,(%R14,%RDX,8)

  (969) 0x45079c INC	%R10

  (969) 0x45079f CMP	%R10,%RDI

  (969) 0x4507a2 JNE	450790

(963) 0x4507a4 MOV	-0x60(%RBP),%RCX

(963) 0x4507a8 MOV	(%RCX,%RAX,8),%RDI

(963) 0x4507ac MOV	-0x80(%RBP),%RCX

(963) 0x4507b0 MOV	(%RCX,%RAX,8),%R8

(963) 0x4507b4 MOV	0x8(%RCX,%RAX,8),%R10

(963) 0x4507b9 CMP	%R10,%R8

(963) 0x4507bc JGE	4508c0

(963) 0x4507c2 MOV	-0xb0(%RBP),%RCX

(963) 0x4507c9 LEA	(%RCX,%R8,8),%R9

(963) 0x4507cd MOV	-0xd0(%RBP),%RSI

(963) 0x4507d4 JMP	450810

0x4507d6 NOPW	%CS:(%RAX,%RAX,1)

0x4507e5 NOPW	%CS:(%RAX,%RAX,1)

0x4507f4 NOPW	%CS:(%RAX,%RAX,1)

  (968) 0x450800 INC	%R8

  (968) 0x450803 ADD	$0x8,%R9

  (968) 0x450807 CMP	%R10,%R8

  (968) 0x45080a JGE	4508c0

  (968) 0x450810 MOV	%R9,%RDX

  (968) 0x450813 TEST	%RSI,%RSI

  (968) 0x450816 JE	450826

  (968) 0x450818 MOV	(%R9),%RDX

  (968) 0x45081b MOV	-0x110(%RBP),%R11

  (968) 0x450822 LEA	(%R11,%RDX,8),%RDX

  (968) 0x450826 MOV	(%RDX),%R11

  (968) 0x450829 CMPQ	$-0x3,(%R12,%R11,8)

  (968) 0x45082e JE	450865

  (968) 0x450830 CMPQ	$0x1,-0xa0(%RBP)

  (968) 0x450838 JE	450858

  (968) 0x45083a MOV	-0x90(%RBP),%RDX

  (968) 0x450841 MOV	(%RDX,%RAX,8),%RDX

  (968) 0x450845 MOV	%R12,%RCX

  (968) 0x450848 MOV	-0xf0(%RBP),%R12

  (968) 0x45084f CMP	(%R12,%R11,8),%RDX

  (968) 0x450853 MOV	%RCX,%R12

  (968) 0x450856 JNE	450865

  (968) 0x450858 MOV	-0x98(%RBP),%RCX

  (968) 0x45085f VADDSD	(%RCX,%R8,8),%XMM3,%XMM3

  (968) 0x450865 CMP	$-0x1,%R11

  (968) 0x450869 JE	450800

  (968) 0x45086b CMP	%RAX,(%R14,%R11,8)

  (968) 0x45086f JNE	450800

  (968) 0x450871 MOV	-0x98(%RBP),%R10

  (968) 0x450878 VMOVSD	(%R10,%R8,8),%XMM5

  (968) 0x45087e MOV	-0x48(%RBP),%RCX

  (968) 0x450882 VMOVSD	%XMM5,(%RCX,%RDI,8)

  (968) 0x450887 MOV	-0x100(%RBP),%RDX

  (968) 0x45088e MOV	(%RDX,%R11,8),%RDX

  (968) 0x450892 MOV	-0xf8(%RBP),%RCX

  (968) 0x450899 MOV	%RDX,(%RCX,%RDI,8)

  (968) 0x45089d INC	%RDI

  (968) 0x4508a0 VADDSD	(%R10,%R8,8),%XMM4,%XMM4

  (968) 0x4508a6 MOV	-0x80(%RBP),%RCX

  (968) 0x4508aa MOV	0x8(%RCX,%RAX,8),%R10

  (968) 0x4508af JMP	450800

0x4508b4 NOPW	%CS:(%RAX,%RAX,1)

(963) 0x4508c0 MOV	-0x68(%RBP),%RCX

(963) 0x4508c4 MOV	(%RCX,%RAX,8),%RDX

(963) 0x4508c8 MOV	-0x70(%RBP),%RCX

(963) 0x4508cc VMULSD	(%RCX,%RDX,8),%XMM4,%XMM4

(963) 0x4508d1 VUCOMISD	%XMM0,%XMM4

(963) 0x4508d5 JE	4508df

(963) 0x4508d7 VXORPD	%XMM1,%XMM3,%XMM2

(963) 0x4508db VDIVSD	%XMM4,%XMM2,%XMM2

(963) 0x4508df MOV	-0x58(%RBP),%RCX

(963) 0x4508e3 MOV	(%RCX,%RAX,8),%R9

(963) 0x4508e7 MOV	-0x30(%RBP),%RSI

(963) 0x4508eb MOV	%RSI,%R10

(963) 0x4508ee SUB	%R9,%R10

(963) 0x4508f1 MOV	-0x48(%RBP),%RDX

(963) 0x4508f5 MOV	-0x88(%RBP),%RCX

(963) 0x4508fc JLE	4509a4

(963) 0x450902 MOV	%R10,%R8

(963) 0x450905 AND	$-0x4,%R8

(963) 0x450909 JE	450980

(963) 0x45090b LEA	-0x1(%R8),%R11

(963) 0x45090f VBROADCASTSD	%XMM2,%YMM3

(963) 0x450914 LEA	(%RCX,%R9,8),%RSI

(963) 0x450918 XOR	%EDX,%EDX

(963) 0x45091a NOPW	(%RAX,%RAX,1)

  (967) 0x450920 VMULPD	(%RSI,%RDX,8),%YMM3,%YMM4

  (967) 0x450925 VMOVUPD	%YMM4,(%RSI,%RDX,8)

  (967) 0x45092a ADD	$0x4,%RDX

  (967) 0x45092e CMP	%R11,%RDX

  (967) 0x450931 JBE	450920

(963) 0x450933 CMP	%R8,%R10

(963) 0x450936 MOV	-0x48(%RBP),%RDX

(963) 0x45093a MOV	-0x30(%RBP),%RSI

(963) 0x45093e JNE	450983

(963) 0x450940 JMP	4509a4

0x450942 NOPW	%CS:(%RAX,%RAX,1)

0x450951 NOPW	%CS:(%RAX,%RAX,1)

0x450960 NOPW	%CS:(%RAX,%RAX,1)

0x45096f NOPW	%CS:(%RAX,%RAX,1)

0x45097e XCHG	%AX,%AX

(963) 0x450980 XOR	%R8D,%R8D

(963) 0x450983 ADD	%R9,%R8

(963) 0x450986 NOPW	%CS:(%RAX,%RAX,1)

  (966) 0x450990 VMULSD	(%RCX,%R8,8),%XMM2,%XMM3

  (966) 0x450996 VMOVSD	%XMM3,(%RCX,%R8,8)

  (966) 0x45099c INC	%R8

  (966) 0x45099f CMP	%R8,%RSI

  (966) 0x4509a2 JNE	450990

(963) 0x4509a4 MOV	-0x60(%RBP),%RCX

(963) 0x4509a8 MOV	(%RCX,%RAX,8),%RCX

(963) 0x4509ac MOV	%RDI,%R8

(963) 0x4509af SUB	%RCX,%R8

(963) 0x4509b2 MOV	-0x40(%RBP),%R10

(963) 0x4509b6 JLE	450480

(963) 0x4509bc MOV	%R8,%RAX

(963) 0x4509bf AND	$-0x4,%RAX

(963) 0x4509c3 JE	450a40

(963) 0x4509c5 LEA	-0x1(%RAX),%R9

(963) 0x4509c9 VBROADCASTSD	%XMM2,%YMM3

(963) 0x4509ce LEA	(%RDX,%RCX,8),%RSI

(963) 0x4509d2 XOR	%EDX,%EDX

(963) 0x4509d4 NOPW	%CS:(%RAX,%RAX,1)

  (965) 0x4509e0 VMULPD	(%RSI,%RDX,8),%YMM3,%YMM4

  (965) 0x4509e5 VMOVUPD	%YMM4,(%RSI,%RDX,8)

  (965) 0x4509ea ADD	$0x4,%RDX

  (965) 0x4509ee CMP	%R9,%RDX

  (965) 0x4509f1 JBE	4509e0

(963) 0x4509f3 CMP	%RAX,%R8

(963) 0x4509f6 MOV	-0x48(%RBP),%RDX

(963) 0x4509fa JE	450480

(963) 0x450a00 JMP	450a42

0x450a02 NOPW	%CS:(%RAX,%RAX,1)

0x450a11 NOPW	%CS:(%RAX,%RAX,1)

0x450a20 NOPW	%CS:(%RAX,%RAX,1)

0x450a2f NOPW	%CS:(%RAX,%RAX,1)

0x450a3e XCHG	%AX,%AX

(963) 0x450a40 XOR	%EAX,%EAX

(963) 0x450a42 ADD	%RCX,%RAX

(963) 0x450a45 NOPW	%CS:(%RAX,%RAX,1)

  (964) 0x450a50 VMULSD	(%RDX,%RAX,8),%XMM2,%XMM3

  (964) 0x450a55 VMOVSD	%XMM3,(%RDX,%RAX,8)

  (964) 0x450a5a INC	%RAX

  (964) 0x450a5d CMP	%RAX,%RDI

  (964) 0x450a60 JNE	450a50

(963) 0x450a62 JMP	450480

0x450a67 NOPW	%CS:(%RAX,%RAX,1)

0x450a76 NOPW	%CS:(%RAX,%RAX,1)

0x450a80 MOV	%R13,%RDI

0x450a83 VZEROUPPER

0x450a86 CALL	51b990 <hypre_Free>

0x450a8b MOV	%R14,%RDI

0x450a8e ADD	$0xe8,%RSP

0x450a95 POP	%RBX

0x450a96 POP	%R12

0x450a98 POP	%R13

0x450a9a POP	%R14

0x450a9c POP	%R15

0x450a9e POP	%RBP

0x450a9f JMP	51b990

0x450aa4 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_4

Source file and lines	par_multi_interp.c:1575-1663
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575,1585-1599,1605-1663.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 32.83 to 4.00 cycles (8.21x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 32.83 to 6.50 cycles (5.05x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__intel_avx_rep_memset: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1591
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1593
hypre_CAlloc: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1586
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1589
hypre_Free: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1662
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1596
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1597

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1598
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1598
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1662

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1598

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 312 bytes. The binary function is storing 256 bytes.

General properties

nb instructions	182
nb uops	197
loop length	1083
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	57

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	32.83 cycles
front end	32.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.50	8.00	15.00	15.00	22.50	7.60	7.50	22.50	22.50	22.50	7.40	15.00
cycles	7.50	11.40	15.00	15.00	22.50	7.60	7.50	22.50	22.50	22.50	7.40	15.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

16.00

Cycles summary

Front-end	32.83
Dispatch	22.50
DIV/SQRT	16.00
Overall L1	32.83

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	3%

all	50%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	6%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	18%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	9%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 32.83 cycles. At this rate:

4% of peak load performance is reached (9.50 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (7.80 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 32.83 to 22.50 cycles (1.46x speedup).

ASM code

In the binary file, the address of the function is: 4501a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xe8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xe8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xe0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x108(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd8(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xd0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xb8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x98(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x90(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x88(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x80(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x78(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x70(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x68(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x40(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %RDI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 4503c0 <hypre_BoomerAMGBuildMultipass.extracted.27+0x220>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 51b840 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 4503cc <hypre_BoomerAMGBuildMultipass.extracted.27+0x22c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 51b840 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0xa8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 450348 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 5277f0 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 450362 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1c2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 5277f0 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
CALL 51da60 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 51da50 <hypre_NumActiveThreads>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x50(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x20,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JE 450400 <hypre_BoomerAMGBuildMultipass.extracted.27+0x260>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RCX	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
JMP 450407 <hypre_BoomerAMGBuildMultipass.extracted.27+0x267>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 45031b <hypre_BoomerAMGBuildMultipass.extracted.27+0x17b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV -0xa8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JG 450337 <hypre_BoomerAMGBuildMultipass.extracted.27+0x197>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 450348 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1a8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
DIV %ECX	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV -0x40(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R9,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
DEC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA 0x1(%R9),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RAX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
CMP %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVE %R8,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 450a80 <hypre_BoomerAMGBuildMultipass.extracted.27+0x8e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVDDUP 0xda771(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 450491 <hypre_BoomerAMGBuildMultipass.extracted.27+0x2f1>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 51b990 <hypre_Free>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD $0xe8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 51b990 <hypre_Free>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_4

Source file and lines	par_multi_interp.c:1575-1663
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575,1585-1599,1605-1663.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 32.83 to 4.00 cycles (8.21x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__intel_avx_rep_memset: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1591
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1593
hypre_CAlloc: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1586
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1589
hypre_Free: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1662
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1596
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1597

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1598
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1598
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1662

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1598

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 312 bytes. The binary function is storing 256 bytes.

General properties

nb instructions	182
nb uops	197
loop length	1083
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	57

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	32.83 cycles
front end	32.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.50	8.00	15.00	15.00	22.50	7.60	7.50	22.50	22.50	22.50	7.40	15.00
cycles	7.50	11.40	15.00	15.00	22.50	7.60	7.50	22.50	22.50	22.50	7.40	15.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

16.00

Cycles summary

Front-end	32.83
Dispatch	22.50
DIV/SQRT	16.00
Overall L1	32.83

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	3%

all	50%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	6%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	18%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	9%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 32.83 cycles. At this rate:

4% of peak load performance is reached (9.50 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (7.80 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4501a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xe8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xe8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xe0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x108(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd8(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xd0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xb8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x98(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x90(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x88(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x80(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x78(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x70(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x68(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x40(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %RDI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 4503c0 <hypre_BoomerAMGBuildMultipass.extracted.27+0x220>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 51b840 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 4503cc <hypre_BoomerAMGBuildMultipass.extracted.27+0x22c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 51b840 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0xa8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 450348 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 5277f0 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 450362 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1c2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 5277f0 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
CALL 51da60 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 51da50 <hypre_NumActiveThreads>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x50(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x20,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JE 450400 <hypre_BoomerAMGBuildMultipass.extracted.27+0x260>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RCX	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
JMP 450407 <hypre_BoomerAMGBuildMultipass.extracted.27+0x267>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 45031b <hypre_BoomerAMGBuildMultipass.extracted.27+0x17b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV -0xa8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JG 450337 <hypre_BoomerAMGBuildMultipass.extracted.27+0x197>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 450348 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1a8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
DIV %ECX	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
MOV -0x40(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R9,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
DEC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA 0x1(%R9),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RAX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
CMP %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVE %R8,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 450a80 <hypre_BoomerAMGBuildMultipass.extracted.27+0x8e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVDDUP 0xda771(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 450491 <hypre_BoomerAMGBuildMultipass.extracted.27+0x2f1>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 51b990 <hypre_Free>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD $0xe8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 51b990 <hypre_Free>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass.extracted.27–	0.36	0.19
▼Loop 963 - par_multi_interp.c:1585-1660 - exec–	0.05	0.02
○Loop 971 - par_multi_interp.c:1618-1628 - exec	0.30	0.13
○Loop 972 - par_multi_interp.c:1612-1615 - exec	0.01	0.01
○Loop 968 - par_multi_interp.c:1622-1652 - exec	0.00	0.00
○Loop 966 - par_multi_interp.c:1657-1658 - exec	0.00	0.00
○Loop 967 - par_multi_interp.c:1657-1658 - exec	0.00	0.00
○Loop 969 - par_multi_interp.c:1633-1636 - exec	0.00	0.00
○Loop 964 - par_multi_interp.c:1659-1660 - exec	0.00	0.00
○Loop 965 - par_multi_interp.c:1659-1660 - exec	0.00	0.00
○Loop 970 - par_multi_interp.c:1633-1636 - exec	0.00	0.00
○Loop 973 - par_multi_interp.c:1612-1615 - exec	0.00	0.00

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Complex instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code