OV - exec - Function hypre_BoomerAMGCoarsenPMIS.extracted.25

	Function: hypre_BoomerAMGCoarsenPMIS.extracted.25	Module: exec	Source: par_coarsen.c:2327-2334	Coverage (incl. loops): 0.06% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2327 - 2334

--------------------------------------------------------------------------------

2327: #pragma omp parallel for private(ig, i) HYPRE_SMP_SCHEDULE

2328: #endif

2329:         for (ig = 0; ig < graph_size; ig++)

2330:         {

2331:            i = graph_array[ig];

2332:            if (measure_array[i] > 1)

2333:            {

2334:               CF_marker[i] = 1;

0x42bb20 PUSH	%RBP

0x42bb21 MOV	%RSP,%RBP

0x42bb24 PUSH	%R15

0x42bb26 PUSH	%R14

0x42bb28 PUSH	%R12

0x42bb2a PUSH	%RBX

0x42bb2b SUB	$0x20,%RSP

0x42bb2f MOVL	$0,-0x24(%RBP)

0x42bb36 MOV	%R8,%R14

0x42bb39 MOV	%RCX,%R15

0x42bb3c MOV	%RDX,%R12

0x42bb3f MOV	(%RDI),%EBX

0x42bb41 MOVQ	$0,-0x30(%RBP)

0x42bb49 MOVQ	$0x1,-0x38(%RBP)

0x42bb51 SUB	$0x8,%RSP

0x42bb55 LEA	-0x38(%RBP),%RAX

0x42bb59 LEA	-0x24(%RBP),%RCX

0x42bb5d LEA	-0x30(%RBP),%R8

0x42bb61 LEA	0x10(%RBP),%R9

0x42bb65 MOV	$0x55b5d0,%EDI

0x42bb6a MOV	%EBX,%ESI

0x42bb6c MOV	$0x22,%EDX

0x42bb71 PUSH	$0x1

0x42bb73 PUSH	$0x1

0x42bb75 PUSH	%RAX

0x42bb76 CALL	410430 <__kmpc_for_static_init_8@plt>

0x42bb7b ADD	$0x20,%RSP

0x42bb7f MOV	-0x30(%RBP),%RAX

0x42bb83 MOV	0x10(%RBP),%RCX

0x42bb87 CMP	%RCX,%RAX

0x42bb8a JA	42bc00

0x42bb8c INC	%RCX

0x42bb8f MOV	%RCX,%RDX

0x42bb92 SUB	%RAX,%RDX

0x42bb95 CMP	$0x8,%RDX

0x42bb99 JAE	42bc40

0x42bb9f MOV	%RDX,%RSI

0x42bba2 AND	$-0x8,%RSI

0x42bba6 CMP	%RDX,%RSI

0x42bba9 JAE	42bc00

0x42bbab ADD	%RSI,%RAX

0x42bbae VMOVSD	0xfe45a(%RIP),%XMM0

0x42bbb6 JMP	42bbc8

0x42bbb8 NOPL	(%RAX,%RAX,1)

(293) 0x42bbc0 INC	%RAX

(293) 0x42bbc3 CMP	%RAX,%RCX

(293) 0x42bbc6 JE	42bc00

(293) 0x42bbc8 MOV	(%R14,%RAX,8),%RDX

(293) 0x42bbcc VUCOMISD	(%R15,%RDX,8),%XMM0

(293) 0x42bbd2 JAE	42bbc0

(293) 0x42bbd4 MOVQ	$0x1,(%R12,%RDX,8)

(293) 0x42bbdc JMP	42bbc0

0x42bbde NOPW	%CS:(%RAX,%RAX,1)

0x42bbed NOPW	%CS:(%RAX,%RAX,1)

0x42bbfc NOPL	(%RAX)

0x42bc00 MOV	$0x55b5f0,%EDI

0x42bc05 MOV	%EBX,%ESI

0x42bc07 ADD	$0x20,%RSP

0x42bc0b POP	%RBX

0x42bc0c POP	%R12

0x42bc0e POP	%R14

0x42bc10 POP	%R15

0x42bc12 POP	%RBP

0x42bc13 JMP	410180

0x42bc18 NOPW	%CS:(%RAX,%RAX,1)

0x42bc27 NOPW	%CS:(%RAX,%RAX,1)

0x42bc36 NOPW	%CS:(%RAX,%RAX,1)

0x42bc40 MOV	%RDX,%RSI

0x42bc43 SHR	$0x3,%RSI

0x42bc47 LEA	0x38(%R14,%RAX,8),%RDI

0x42bc4c VMOVSD	0xfe3bc(%RIP),%XMM0

0x42bc54 JMP	42bc8d

0x42bc56 NOPW	%CS:(%RAX,%RAX,1)

0x42bc65 NOPW	%CS:(%RAX,%RAX,1)

0x42bc74 NOPW	%CS:(%RAX,%RAX,1)

(294) 0x42bc80 ADD	$0x40,%RDI

(294) 0x42bc84 DEC	%RSI

(294) 0x42bc87 JE	42bb9f

(294) 0x42bc8d MOV	-0x38(%RDI),%R8

(294) 0x42bc91 VUCOMISD	(%R15,%R8,8),%XMM0

(294) 0x42bc97 JB	42bd40

(294) 0x42bc9d MOV	-0x30(%RDI),%R8

(294) 0x42bca1 VUCOMISD	(%R15,%R8,8),%XMM0

(294) 0x42bca7 JB	42bd58

(294) 0x42bcad MOV	-0x28(%RDI),%R8

(294) 0x42bcb1 VUCOMISD	(%R15,%R8,8),%XMM0

(294) 0x42bcb7 JB	42bd70

(294) 0x42bcbd MOV	-0x20(%RDI),%R8

(294) 0x42bcc1 VUCOMISD	(%R15,%R8,8),%XMM0

(294) 0x42bcc7 JB	42bd88

(294) 0x42bccd MOV	-0x18(%RDI),%R8

(294) 0x42bcd1 VUCOMISD	(%R15,%R8,8),%XMM0

(294) 0x42bcd7 JB	42bda0

(294) 0x42bcdd MOV	-0x10(%RDI),%R8

(294) 0x42bce1 VUCOMISD	(%R15,%R8,8),%XMM0

(294) 0x42bce7 JB	42bdb8

(294) 0x42bced MOV	-0x8(%RDI),%R8

(294) 0x42bcf1 VUCOMISD	(%R15,%R8,8),%XMM0

(294) 0x42bcf7 JB	42bdd0

(294) 0x42bcfd MOV	(%RDI),%R8

(294) 0x42bd00 VUCOMISD	(%R15,%R8,8),%XMM0

(294) 0x42bd06 JAE	42bc80

(294) 0x42bd0c JMP	42bde7

0x42bd11 NOPW	%CS:(%RAX,%RAX,1)

0x42bd20 NOPW	%CS:(%RAX,%RAX,1)

0x42bd2f NOPW	%CS:(%RAX,%RAX,1)

0x42bd3e XCHG	%AX,%AX

(294) 0x42bd40 MOVQ	$0x1,(%R12,%R8,8)

(294) 0x42bd48 MOV	-0x30(%RDI),%R8

(294) 0x42bd4c VUCOMISD	(%R15,%R8,8),%XMM0

(294) 0x42bd52 JAE	42bcad

(294) 0x42bd58 MOVQ	$0x1,(%R12,%R8,8)

(294) 0x42bd60 MOV	-0x28(%RDI),%R8

(294) 0x42bd64 VUCOMISD	(%R15,%R8,8),%XMM0

(294) 0x42bd6a JAE	42bcbd

(294) 0x42bd70 MOVQ	$0x1,(%R12,%R8,8)

(294) 0x42bd78 MOV	-0x20(%RDI),%R8

(294) 0x42bd7c VUCOMISD	(%R15,%R8,8),%XMM0

(294) 0x42bd82 JAE	42bccd

(294) 0x42bd88 MOVQ	$0x1,(%R12,%R8,8)

(294) 0x42bd90 MOV	-0x18(%RDI),%R8

(294) 0x42bd94 VUCOMISD	(%R15,%R8,8),%XMM0

(294) 0x42bd9a JAE	42bcdd

(294) 0x42bda0 MOVQ	$0x1,(%R12,%R8,8)

(294) 0x42bda8 MOV	-0x10(%RDI),%R8

(294) 0x42bdac VUCOMISD	(%R15,%R8,8),%XMM0

(294) 0x42bdb2 JAE	42bced

(294) 0x42bdb8 MOVQ	$0x1,(%R12,%R8,8)

(294) 0x42bdc0 MOV	-0x8(%RDI),%R8

(294) 0x42bdc4 VUCOMISD	(%R15,%R8,8),%XMM0

(294) 0x42bdca JAE	42bcfd

(294) 0x42bdd0 MOVQ	$0x1,(%R12,%R8,8)

(294) 0x42bdd8 MOV	(%RDI),%R8

(294) 0x42bddb VUCOMISD	(%R15,%R8,8),%XMM0

(294) 0x42bde1 JAE	42bc80

(294) 0x42bde7 MOVQ	$0x1,(%R12,%R8,8)

(294) 0x42bdef JMP	42bc80

0x42bdf4 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_4

Source file and lines	par_coarsen.c:2327-2334
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2327-2334.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.17 to 1.50 cycles (8.11x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.17 to 0.87 cycles (14.05x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2327

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	72
nb uops	73
loop length	381
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.17 cycles
front end	12.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.80	2.80	3.33	3.33	6.00	2.80	2.80	6.00	6.00	6.00	2.80	3.33
cycles	2.80	2.80	3.33	3.33	6.00	2.80	2.80	6.00	6.00	6.00	2.80	3.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.17
Dispatch	6.00
Overall L1	12.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	9%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.17 cycles. At this rate:

1% of peak load performance is reached (2.96 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.64 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.17 to 6.00 cycles (2.03x speedup).

ASM code

In the binary file, the address of the function is: 42bb20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVL $0,-0x24(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x1,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x24(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x10(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x55b5d0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 410430 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 42bc00 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0xe0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMP $0x8,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 42bc40 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x120>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x8,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
CMP %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 42bc00 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0xe0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD 0xfe45a(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 42bbc8 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0xa8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x55b5f0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 410180 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x3,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
LEA 0x38(%R14,%RAX,8),%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSD 0xfe3bc(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 42bc8d <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x16d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_4

Source file and lines	par_coarsen.c:2327-2334
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2327-2334.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.17 to 1.50 cycles (8.11x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2327

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	72
nb uops	73
loop length	381
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.17 cycles
front end	12.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.80	2.80	3.33	3.33	6.00	2.80	2.80	6.00	6.00	6.00	2.80	3.33
cycles	2.80	2.80	3.33	3.33	6.00	2.80	2.80	6.00	6.00	6.00	2.80	3.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.17
Dispatch	6.00
Overall L1	12.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	9%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.17 cycles. At this rate:

1% of peak load performance is reached (2.96 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.64 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 42bb20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVL $0,-0x24(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x1,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x24(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x10(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x55b5d0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 410430 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 42bc00 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0xe0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMP $0x8,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 42bc40 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x120>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x8,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
CMP %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 42bc00 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0xe0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD 0xfe45a(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 42bbc8 <hypre_BoomerAMGCoarsenPMIS.extracted.25+0xa8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x55b5f0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 410180 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x3,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
LEA 0x38(%R14,%RAX,8),%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSD 0xfe3bc(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 42bc8d <hypre_BoomerAMGCoarsenPMIS.extracted.25+0x16d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCoarsenPMIS.extracted.25–	0.06	0.03
○Loop 294 - par_coarsen.c:2327-2334 - exec	0.06	0.03
○Loop 293 - par_coarsen.c:2327-2334 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code