OV - exec - Loop 91

	Loop Id: 91	Module: exec	Source: par_coarsen.c:2354-2381	Coverage: 0.11%

0x42dbc0 ADD	$0x8,%RDI

0x42dbc4 CMP	%RDI,%RDX

0x42dbc7 JE	42dcd8

0x42dbcd MOV	(%RDI),%R8

0x42dbd0 VMOVSD	(%RCX,%R8,8),%XMM1

0x42dbd6 LEA	(,%R8,8),%R12

0x42dbde VCOMISD	%XMM2,%XMM1

0x42dbe2 JBE	42dbc0

0x42dbe4 MOV	-0x48(%RBP),%R13

0x42dbe8 LEA	0x8(%R12),%R9

0x42dbed MOV	(%R13,%R8,8),%RAX

0x42dbf2 LEA	(%R13,%R9,1),%R13

0x42dbf7 MOV	(%R13),%RSI

0x42dbfb CMP	%RSI,%RAX

0x42dbfe JGE	42dc58

0x42dc00 MOV	%R15,-0x38(%RBP)

0x42dc04 JMP	42dc2a

  (93) 0x42dc10 VCOMISD	%XMM1,%XMM0

  (93) 0x42dc14 JBE	42dc22

  (93) 0x42dc16 MOVQ	$0,(%R14,%R12,1)

  (93) 0x42dc1e MOV	(%R13),%RSI

  (93) 0x42dc22 INC	%RAX

  (93) 0x42dc25 CMP	%RSI,%RAX

  (93) 0x42dc28 JGE	42dc54

  (93) 0x42dc2a MOV	(%R10,%RAX,8),%R15

  (93) 0x42dc2e VMOVSD	(%RCX,%R15,8),%XMM0

  (93) 0x42dc34 VCOMISD	%XMM2,%XMM0

  (93) 0x42dc38 JBE	42dc22

  (93) 0x42dc3a VCOMISD	%XMM0,%XMM1

  (93) 0x42dc3e JBE	42dc10

  (93) 0x42dc40 MOVQ	$0,(%R14,%R15,8)

  (93) 0x42dc48 INC	%RAX

  (93) 0x42dc4b MOV	(%R13),%RSI

  (93) 0x42dc4f CMP	%RSI,%RAX

  (93) 0x42dc52 JL	42dc2a

0x42dc54 MOV	-0x38(%RBP),%R15

0x42dc58 MOV	-0x40(%RBP),%R13

0x42dc5c ADD	%R13,%R9

0x42dc5f MOV	(%R13,%R8,8),%RAX

0x42dc64 MOV	(%R9),%R13

0x42dc67 CMP	%R13,%RAX

0x42dc6a JL	42dcac

0x42dc6c JMP	42dbc0

  (92) 0x42dc78 VCOMISD	%XMM1,%XMM3

  (92) 0x42dc7c JBE	42dca0

  (92) 0x42dc7e MOVQ	$0,(%R14,%R12,1)

  (92) 0x42dc86 MOV	(%R9),%R13

  (92) 0x42dc89 NOPW	%CS:(%RAX,%RAX,1)

  (92) 0x42dc94 NOPW	%CS:(%RAX,%RAX,1)

  (92) 0x42dc9f NOP

  (92) 0x42dca0 INC	%RAX

  (92) 0x42dca3 CMP	%R13,%RAX

  (92) 0x42dca6 JGE	42dbc0

  (92) 0x42dcac MOV	(%R11,%RAX,8),%RSI

  (92) 0x42dcb0 LEA	(%RBX,%RSI,1),%R8

  (92) 0x42dcb4 VMOVSD	(%RCX,%R8,8),%XMM3

  (92) 0x42dcba VCOMISD	%XMM2,%XMM3

  (92) 0x42dcbe JBE	42dca0

  (92) 0x42dcc0 VCOMISD	%XMM3,%XMM1

  (92) 0x42dcc4 JBE	42dc78

  (92) 0x42dcc6 MOVQ	$0,(%R15,%RSI,8)

  (92) 0x42dcce MOV	(%R9),%R13

  (92) 0x42dcd1 JMP	42dca0

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2354 - 2381

--------------------------------------------------------------------------------

2354: #pragma omp parallel for private(ig, i, jS, j, jj) HYPRE_SMP_SCHEDULE

2355: #endif

2356:         for (ig = 0; ig < graph_size; ig++)

2357:         {

2358:            i = graph_array[ig];

2359:            if (measure_array[i] > 1)

2360:            {

2361:               for (jS = S_diag_i[i]; jS < S_diag_i[i+1]; jS++)

2362:               {

2363:                  j = S_diag_j[jS];

2364:                  if (measure_array[j] > 1)

2365:                  {

2366:                     if (measure_array[i] > measure_array[j])

2367:                        CF_marker[j] = 0;

2368:                     else if (measure_array[j] > measure_array[i])

2369:                        CF_marker[i] = 0;

2370:                  }

2371:               } /* for each local neighbor j of i */

2372:               for (jS = S_offd_i[i]; jS < S_offd_i[i+1]; jS++)

2373:               {

2374:                  jj = S_offd_j[jS];

2375:                  j = num_variables+jj;

2376:                  if (measure_array[j] > 1)

2377:                  {

2378:                     if (measure_array[i] > measure_array[j])

2379:                        CF_marker_offd[jj] = 0;

2380:                     else if (measure_array[j] > measure_array[i])

2381:                        CF_marker[i] = 0;

Coverage (%)	Name	Source Location	Module
○98.62	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.38	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.67
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.39
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.6
Source	par_coarsen.c:2354-2354,par_coarsen.c:2359-2361,par_coarsen.c:2372-2372
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.17
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	4.17
CQA cycles if fully vectorized	0.52
Front-end cycles	4.17
P0 cycles	2.50
P1 cycles	1.40
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	0.50
P5 cycles	1.40
P6 cycles	2.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	1.20
P11 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	25.00
Nb loads	9.00
Nb stores	1.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.20
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.67
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.39
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.6
Source	par_coarsen.c:2354-2354,par_coarsen.c:2359-2361,par_coarsen.c:2372-2372
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.17
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	4.17
CQA cycles if fully vectorized	0.52
Front-end cycles	4.17
P0 cycles	2.50
P1 cycles	1.40
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	0.50
P5 cycles	1.40
P6 cycles	2.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	1.20
P11 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	25.00
Nb loads	9.00
Nb stores	1.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.20
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.6
Source file and lines	par_coarsen.c:2354-2381
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354-2381.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354,2359-2361,2372.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=26
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 26 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.17 to 2.50 cycles (1.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 4.17 to 0.52 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes (9 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

General properties

nb instructions	25
nb uops	25
loop length	99
used x86 registers	11
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.17 cycles
front end	4.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.50	1.40	3.00	3.00	0.50	1.40	2.50	0.50	0.50	0.50	1.20	3.00
cycles	2.50	1.40	3.00	3.00	0.50	1.40	2.50	0.50	0.50	0.50	1.20	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.17
Dispatch	3.00
Overall L1	4.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.17 cycles. At this rate:

8% of peak load performance is reached (17.28 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.92 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.17 to 3.00 cycles (1.39x speedup).

ASM code

In the binary file, the address of the loop is: 42dbcd

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ADD $0x8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 42dcd8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x1d8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%RDI),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RCX,%R8,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (,%R8,8),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VCOMISD %XMM2,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 42dbc0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0xc0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x48(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x8(%R12),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R13,%R8,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R13,%R9,1),%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R13),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 42dc58 <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x158>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 42dc2a <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x12a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0x38(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x40(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R13,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV (%R13,%R8,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R9),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R13,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JL 42dcac <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x1ac>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 42dbc0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0xc0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.6
Source file and lines	par_coarsen.c:2354-2381
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=26
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.17 to 2.50 cycles (1.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 4.17 to 0.52 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

General properties

nb instructions	25
nb uops	25
loop length	99
used x86 registers	11
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.17 cycles
front end	4.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.50	1.40	3.00	3.00	0.50	1.40	2.50	0.50	0.50	0.50	1.20	3.00
cycles	2.50	1.40	3.00	3.00	0.50	1.40	2.50	0.50	0.50	0.50	1.20	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.17
Dispatch	3.00
Overall L1	4.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.17 cycles. At this rate:

8% of peak load performance is reached (17.28 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.92 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 42dbcd

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ADD $0x8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 42dcd8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x1d8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%RDI),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RCX,%R8,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (,%R8,8),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VCOMISD %XMM2,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 42dbc0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0xc0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x48(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x8(%R12),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R13,%R8,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R13,%R9,1),%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R13),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 42dc58 <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x158>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 42dc2a <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x12a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0x38(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x40(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R13,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV (%R13,%R8,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R9),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R13,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JL 42dcac <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x1ac>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 42dbc0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0xc0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code