OV - exec - Loop 736

	Loop Id: 736	Module: exec	Source: par_lr_interp.c:1264-1532 [...]	Coverage: 0.01%

0x46ea58 MOV	(%R11,%RAX,8),%RDX

0x46ea5c ADD	%RDI,%RSI

0x46ea5f CMP	%RDX,(%RSI)

0x46ea62 JGE	46ea73

0x46ea64 MOV	%RBX,(%RSI)

0x46ea67 MOV	-0x50(%RBP),%R13

0x46ea6b INC	%RBX

0x46ea6e MOV	0x8(%R13,%RAX,8),%R8

0x46ea73 INC	%R9

0x46ea76 CMP	%R8,%R9

0x46ea79 JGE	46eb10

0x46ea7f MOV	(%R15,%R9,8),%R10

0x46ea83 MOV	(%R14,%R10,8),%RCX

0x46ea87 LEA	(,%R10,8),%RSI

0x46ea8f TEST	%RCX,%RCX

0x46ea92 JNS	46ea58

0x46ea94 CMP	$-0x3,%RCX

0x46ea98 JE	46ea73

0x46ea9a MOV	-0x50(%RBP),%R12

0x46ea9e ADD	$0x8,%RSI

0x46eaa2 LEA	(%R12,%RSI,1),%R13

0x46eaa6 MOV	(%R12,%R10,8),%RDX

0x46eaaa MOV	(%R13),%R12

0x46eaae CMP	%R12,%RDX

0x46eab1 JGE	46eae9

0x46eab3 NOPL	(%RAX,%RAX,1)

  (739) 0x46eab8 MOV	(%R15,%RDX,8),%R8

  (739) 0x46eabc CMPQ	$0,(%R14,%R8,8)

  (739) 0x46eac1 LEA	(,%R8,8),%RCX

  (739) 0x46eac9 JS	46eae1

  (739) 0x46eacb MOV	(%R11,%RAX,8),%R8

  (739) 0x46eacf ADD	%RDI,%RCX

  (739) 0x46ead2 CMP	%R8,(%RCX)

  (739) 0x46ead5 JGE	46eae1

  (739) 0x46ead7 MOV	%RBX,(%RCX)

  (739) 0x46eada INC	%RBX

  (739) 0x46eadd MOV	(%R13),%R12

  (739) 0x46eae1 INC	%RDX

  (739) 0x46eae4 CMP	%R12,%RDX

  (739) 0x46eae7 JL	46eab8

0x46eae9 MOV	-0xb8(%RBP),%RDX

0x46eaf0 CMPQ	$0x1,(%RDX)

0x46eaf4 JG	46fad0

0x46eafa MOV	-0x50(%RBP),%RSI

0x46eafe INC	%R9

0x46eb01 MOV	0x8(%RSI,%RAX,8),%R8

0x46eb06 CMP	%R8,%R9

0x46eb09 JL	46ea7f

0x46fad0 MOV	-0x80(%RBP),%R13

0x46fad4 MOV	(%R13,%R10,8),%RDX

0x46fad9 ADD	%R13,%RSI

0x46fadc CMP	(%RSI),%RDX

0x46fadf JGE	46eafa

0x46fae5 MOV	-0xe0(%RBP),%R10

0x46faec CMPQ	$0,-0xd8(%RBP)

0x46faf4 MOV	0xf0(%R10),%RCX

0x46fafb MOV	%RDI,-0x190(%RBP)

0x46fb02 MOV	(%RCX),%R13

0x46fb05 MOV	-0xc8(%RBP),%R8

0x46fb0c MOV	-0x90(%RBP),%RCX

0x46fb13 JE	470e90

0x46fb19 MOV	%R9,-0x198(%RBP)

0x46fb20 MOV	-0xd8(%RBP),%RDI

0x46fb27 NOPW	(%RAX,%RAX,1)

  (738) 0x46fb30 MOV	(%RCX,%RDX,8),%R9

  (738) 0x46fb34 MOV	(%RDI,%R9,8),%R10

  (738) 0x46fb38 CMPQ	$0,(%R13,%R10,8)

  (738) 0x46fb3e LEA	(,%R10,8),%R12

  (738) 0x46fb46 JS	46fb70

  (738) 0x46fb48 MOV	-0x60(%RBP),%R9

  (738) 0x46fb4c ADD	%R9,%R12

  (738) 0x46fb4f MOV	-0x58(%RBP),%R9

  (738) 0x46fb53 MOV	(%R9,%RAX,8),%R9

  (738) 0x46fb57 CMP	%R9,(%R12)

  (738) 0x46fb5b JGE	46fb70

  (738) 0x46fb5d MOV	-0x68(%RBP),%R9

  (738) 0x46fb61 MOVQ	$0x1,(%R9,%R10,8)

  (738) 0x46fb69 MOV	%R8,(%R12)

  (738) 0x46fb6d INC	%R8

  (738) 0x46fb70 INC	%RDX

  (738) 0x46fb73 CMP	%RDX,(%RSI)

  (738) 0x46fb76 JG	46fb30

0x46fb78 MOV	%R8,-0xc8(%RBP)

0x46fb7f MOV	-0x190(%RBP),%RDI

0x46fb86 MOV	-0x198(%RBP),%R9

0x46fb8d JMP	46eafa

0x470e90 MOV	%R9,-0x198(%RBP)

0x470e97 NOPW	(%RAX,%RAX,1)

  (737) 0x470ea0 MOV	(%RCX,%RDX,8),%R10

  (737) 0x470ea4 CMPQ	$0,(%R13,%R10,8)

  (737) 0x470eaa LEA	(,%R10,8),%R12

  (737) 0x470eb2 JS	470edc

  (737) 0x470eb4 MOV	-0x60(%RBP),%RDI

  (737) 0x470eb8 ADD	%RDI,%R12

  (737) 0x470ebb MOV	(%R12),%R9

  (737) 0x470ebf MOV	-0x58(%RBP),%RDI

  (737) 0x470ec3 CMP	%R9,(%RDI,%RAX,8)

  (737) 0x470ec7 JLE	470edc

  (737) 0x470ec9 MOV	-0x68(%RBP),%RDI

  (737) 0x470ecd MOVQ	$0x1,(%RDI,%R10,8)

  (737) 0x470ed5 MOV	%R8,(%R12)

  (737) 0x470ed9 INC	%R8

  (737) 0x470edc INC	%RDX

  (737) 0x470edf CMP	%RDX,(%RSI)

  (737) 0x470ee2 JG	470ea0

0x470ee4 JMP	46fb78

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1264 - 1532

--------------------------------------------------------------------------------

1264:            for (jj = S_diag_i[i]; jj < S_diag_i[i+1]; jj++)

1265:            {

1266:              i1 = S_diag_j[jj];

1267:              if (CF_marker[i1] >= 0)

1268:              { /* i1 is a C point */

1269:                if (P_marker[i1] < P_diag_i[i])

1270:                {

1271:                  P_marker[i1] = jj_counter;

1272:                  jj_counter++;

1273:                }

1274:              }

1275:              else if (CF_marker[i1] != -3)

1276:              { /* i1 is a F point, loop through it's strong neighbors */

1277:                for (kk = S_diag_i[i1]; kk < S_diag_i[i1+1]; kk++)

1278:                {

1279:                  k1 = S_diag_j[kk];

1280:                  if (CF_marker[k1] >= 0)

1281:                  {

1282:                    if(P_marker[k1] < P_diag_i[i])

1283:                    {

1284:                      P_marker[k1] = jj_counter;

1285:                      jj_counter++;

1286:                    }

1287:                  }

1288:                }

1289:                if(num_procs > 1)

1290:                {

1291:                  for (kk = S_offd_i[i1]; kk < S_offd_i[i1+1]; kk++)

1292:                  {

1293:                    if(col_offd_S_to_A)

1294:                      k1 = col_offd_S_to_A[S_offd_j[kk]];

1295:                    else

1296:                      k1 = S_offd_j[kk];

1297:                    if (CF_marker_offd[k1] >= 0)

1298:                    {

1299:                      if(P_marker_offd[k1] < P_offd_i[i])

1300:                      {

1301:                        tmp_CF_marker_offd[k1] = 1;

1302:                        P_marker_offd[k1] = jj_counter_offd;

1303:                        jj_counter_offd++;

[...]

1532:                  for (kk = S_offd_i[i1]; kk < S_offd_i[i1+1]; kk++)

Coverage (%)	Name	Source Location	Module
○99.08	gomp_thread_start	team.c:130	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source	par_lr_interp.c:1264-1264,par_lr_interp.c:1267-1272,par_lr_interp.c:1275-1277,par_lr_interp.c:1289-1291,par_lr_interp.c:1297-1297,par_lr_interp.c:1532-1532
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.50
CQA cycles if no scalar integer	9.50
CQA cycles if FP arith vectorized	9.50
CQA cycles if fully vectorized	1.19
Front-end cycles	9.50
P0 cycles	4.50
P1 cycles	3.80
P2 cycles	8.33
P3 cycles	8.33
P4 cycles	2.50
P5 cycles	3.60
P6 cycles	4.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	3.60
P11 cycles	8.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	57.00
Nb uops	57.00
Nb loads	25.00
Nb stores	5.00
Nb stack references	9.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.26
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	40.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source	par_lr_interp.c:1264-1264,par_lr_interp.c:1267-1272,par_lr_interp.c:1275-1277,par_lr_interp.c:1289-1291,par_lr_interp.c:1297-1297,par_lr_interp.c:1532-1532
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.50
CQA cycles if no scalar integer	9.50
CQA cycles if FP arith vectorized	9.50
CQA cycles if fully vectorized	1.19
Front-end cycles	9.50
P0 cycles	4.50
P1 cycles	3.80
P2 cycles	8.33
P3 cycles	8.33
P4 cycles	2.50
P5 cycles	3.60
P6 cycles	4.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	3.60
P11 cycles	8.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	57.00
Nb uops	57.00
Nb loads	25.00
Nb stores	5.00
Nb stack references	9.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.26
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	40.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source file and lines	par_lr_interp.c:1264-1532
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1264-1303,1532.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1264,1267-1272,1275-1277,1289-1291,1297,1532.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 35 paths individually, rerun with max-paths=35
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 35 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 9.50 to 1.19 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 200 bytes. The binary loop is storing 40 bytes.

General properties

nb instructions	57
nb uops	57
loop length	277
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.50	3.80	8.33	8.33	2.50	3.60	4.50	2.50	2.50	2.50	3.60	8.33
cycles	4.50	3.80	8.33	8.33	2.50	3.60	4.50	2.50	2.50	2.50	3.60	8.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.50
Dispatch	8.33
Overall L1	9.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.50 cycles. At this rate:

10% of peak load performance is reached (21.05 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.21 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.50 to 8.33 cycles (1.14x speedup).

ASM code

In the binary file, the address of the loop is: 46ea7f

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV (%R11,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDI,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RDX,(%RSI)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 46ea73 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x303>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,(%RSI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x50(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x8(%R13,%RAX,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 46eb10 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R15,%R9,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14,%R10,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R10,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNS 46ea58 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2e8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $-0x3,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46ea73 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x303>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x50(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R12,%RSI,1),%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R12,%R10,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R13),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R12,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 46eae9 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x379>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0xb8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0x1,(%RDX)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JG 46fad0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1360>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x50(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RSI,%RAX,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %R8,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 46ea7f <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x30f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x80(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R13,%R10,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R13,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP (%RSI),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 46eafa <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x38a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xe0(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0,-0xd8(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV 0xf0(%R10),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0x190(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RCX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xc8(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x90(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 470e90 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2720>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9,-0x198(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xd8(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x190(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x198(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 46eafa <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x38a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %R9,-0x198(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 46fb78 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1408>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source file and lines	par_lr_interp.c:1264-1532
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 35 paths individually, rerun with max-paths=35
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 9.50 to 1.19 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 200 bytes. The binary loop is storing 40 bytes.

General properties

nb instructions	57
nb uops	57
loop length	277
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.50	3.80	8.33	8.33	2.50	3.60	4.50	2.50	2.50	2.50	3.60	8.33
cycles	4.50	3.80	8.33	8.33	2.50	3.60	4.50	2.50	2.50	2.50	3.60	8.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.50
Dispatch	8.33
Overall L1	9.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.50 cycles. At this rate:

10% of peak load performance is reached (21.05 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.21 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 46ea7f

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV (%R11,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDI,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RDX,(%RSI)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 46ea73 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x303>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,(%RSI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x50(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x8(%R13,%RAX,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 46eb10 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x3a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R15,%R9,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14,%R10,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R10,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNS 46ea58 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2e8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $-0x3,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46ea73 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x303>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x50(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R12,%RSI,1),%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R12,%R10,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R13),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R12,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 46eae9 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x379>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0xb8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0x1,(%RDX)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JG 46fad0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1360>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x50(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RSI,%RAX,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %R8,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 46ea7f <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x30f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x80(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R13,%R10,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R13,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP (%RSI),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 46eafa <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x38a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xe0(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0,-0xd8(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV 0xf0(%R10),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0x190(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RCX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xc8(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x90(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 470e90 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2720>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9,-0x198(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xd8(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x190(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x198(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 46eafa <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x38a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %R9,-0x198(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 46fb78 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1408>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code