OV - exec - Loop 721

	Loop Id: 721	Module: exec	Source: par_lr_interp.c:1624-1628	Coverage: 0.10%

0x46f9e3 MOV	(%RDI,%R9,8),%R10    [2]

0x46f9e7 CMP	(%R13,%R10,8),%RDX    [1]

0x46f9ec JLE	46f9f3

0x46f9ee CMP	%RAX,%R10

0x46f9f1 JNE	46fa09

0x46f9f3 VMOVSD	(%R15,%R9,8),%XMM14    [4]

0x46f9f9 VMULSD	%XMM0,%XMM14,%XMM15

0x46f9fd VCOMISD	%XMM15,%XMM3

0x46fa02 JBE	46fa09

0x46fa04 VADDSD	%XMM14,%XMM2,%XMM2

0x46fa09 INC	%R9

0x46fa0c MOV	(%RDI,%R9,8),%RCX    [2]

0x46fa10 CMP	(%R13,%RCX,8),%RDX    [1]

0x46fa15 JLE	46fa1c

0x46fa17 CMP	%RAX,%RCX

0x46fa1a JNE	46fa30

0x46fa1c VMOVSD	(%R15,%R9,8),%XMM4    [4]

0x46fa22 VMULSD	%XMM0,%XMM4,%XMM7

0x46fa26 VCOMISD	%XMM7,%XMM3

0x46fa2a JBE	46fa30

0x46fa2c VADDSD	%XMM4,%XMM2,%XMM2

0x46fa30 LEA	0x1(%R9),%R10

0x46fa34 MOV	(%RDI,%R10,8),%RCX    [2]

0x46fa38 CMP	(%R13,%RCX,8),%RDX    [1]

0x46fa3d JLE	46fa44

0x46fa3f CMP	%RAX,%RCX

0x46fa42 JNE	46fa5a

0x46fa44 VMOVSD	(%R15,%R10,8),%XMM9    [4]

0x46fa4a VMULSD	%XMM0,%XMM9,%XMM8

0x46fa4e VCOMISD	%XMM8,%XMM3

0x46fa53 JBE	46fa5a

0x46fa55 VADDSD	%XMM9,%XMM2,%XMM2

0x46fa5a LEA	0x2(%R9),%R10

0x46fa5e MOV	(%RDI,%R10,8),%RCX    [2]

0x46fa62 CMP	(%R13,%RCX,8),%RDX    [1]

0x46fa67 JLE	46fa6e

0x46fa69 CMP	%RAX,%RCX

0x46fa6c JNE	46fa84

0x46fa6e VMOVSD	(%R15,%R10,8),%XMM11    [4]

0x46fa74 VMULSD	%XMM0,%XMM11,%XMM12

0x46fa78 VCOMISD	%XMM12,%XMM3

0x46fa7d JBE	46fa84

0x46fa7f VADDSD	%XMM11,%XMM2,%XMM2

0x46fa84 MOV	-0xd0(%RBP),%R10    [3]

0x46fa8b ADD	$0x3,%R9

0x46fa8f CMP	%R10,%R9

0x46fa92 JNE	46f9e3

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1624 - 1628

--------------------------------------------------------------------------------

1624:                for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1625:                {

1626:                  i2 = A_diag_j[jj1];

1627:                  if((P_marker[i2] >= jj_begin_row || i2 == i) && (sgn*A_diag_data[jj1]) < 0)

1628:                    sum += A_diag_data[jj1];

Coverage (%)	Name	Source Location	Module
○98.99	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.01	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.13
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P0, P6,
Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source	par_lr_interp.c:1624-1628
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.50
CQA cycles if no scalar integer	8.50
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	1.06
Front-end cycles	8.33
P0 cycles	8.50
P1 cycles	5.40
P2 cycles	4.33
P3 cycles	4.33
P4 cycles	0.00
P5 cycles	5.40
P6 cycles	8.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	5.20
P11 cycles	4.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	46.00
Nb loads	13.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	0.94
Nb FLOP add-sub	4.00
Nb FLOP mul	4.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.24
Bytes prefetched	0.00
Bytes loaded	104.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.13
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P0, P6,
Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source	par_lr_interp.c:1624-1628
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.50
CQA cycles if no scalar integer	8.50
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	1.06
Front-end cycles	8.33
P0 cycles	8.50
P1 cycles	5.40
P2 cycles	4.33
P3 cycles	4.33
P4 cycles	0.00
P5 cycles	5.40
P6 cycles	8.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	5.20
P11 cycles	4.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	46.00
Nb loads	13.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	0.94
Nb FLOP add-sub	4.00
Nb FLOP mul	4.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.24
Bytes prefetched	0.00
Bytes loaded	104.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source file and lines	par_lr_interp.c:1624-1628
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1624-1628.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 625 paths individually, rerun with max-paths=625
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 625 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 8.50 to 1.06 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Recompile with march=sapphirerapids. CQA target is Granite_Rapids_ad (Intel(R) Xeon(R) Granite Rapids) but specialization flags are -march=graniterapids
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Type of elements and instruction set

12 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction
4: multiply

The binary loop is loading 104 bytes (13 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	47
nb uops	46
loop length	181
used x86 registers	9
used mmx registers	0
used xmm registers	11
used ymm registers	0
used zmm registers	0
nb stack references	1
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.33 cycles
front end	8.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.50	5.40	4.33	4.33	0.00	5.40	8.50	0.00	0.00	0.00	5.20	4.33
cycles	8.50	5.40	4.33	4.33	0.00	5.40	8.50	0.00	0.00	0.00	5.20	4.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.33
Dispatch	8.50
Overall L1	8.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.50 cycles. At this rate:

6% of peak load performance is reached (12.24 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 46f9e3

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOV (%RDI,%R9,8),%R10	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP (%R13,%R10,8),%RDX	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JLE 46f9f3 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1283>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP %RAX,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JNE 46fa09 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1299>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VMOVSD (%R15,%R9,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM14,%XMM15	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM15,%XMM3	1	1	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 46fa09 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1299>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VADDSD %XMM14,%XMM2,%XMM2	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
INC %R9	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI,%R9,8),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP (%R13,%RCX,8),%RDX	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JLE 46fa1c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x12ac>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JNE 46fa30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x12c0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VMOVSD (%R15,%R9,8),%XMM4	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM4,%XMM7	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM7,%XMM3	1	1	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 46fa30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x12c0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VADDSD %XMM4,%XMM2,%XMM2	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
LEA 0x1(%R9),%R10	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDI,%R10,8),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP (%R13,%RCX,8),%RDX	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JLE 46fa44 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x12d4>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JNE 46fa5a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x12ea>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VMOVSD (%R15,%R10,8),%XMM9	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM9,%XMM8	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM8,%XMM3	1	1	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 46fa5a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x12ea>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VADDSD %XMM9,%XMM2,%XMM2	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
LEA 0x2(%R9),%R10	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDI,%R10,8),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP (%R13,%RCX,8),%RDX	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JLE 46fa6e <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x12fe>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JNE 46fa84 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1314>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VMOVSD (%R15,%R10,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM11,%XMM12	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM12,%XMM3	1	1	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 46fa84 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1314>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VADDSD %XMM11,%XMM2,%XMM2	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
MOV -0xd0(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
ADD $0x3,%R9	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 46f9e3 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1273>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source file and lines	par_lr_interp.c:1624-1628
Module	exec

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 625 paths individually, rerun with max-paths=625
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 8.50 to 1.06 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Recompile with march=sapphirerapids. CQA target is Granite_Rapids_ad (Intel(R) Xeon(R) Granite Rapids) but specialization flags are -march=graniterapids
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Type of elements and instruction set

12 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction
4: multiply

The binary loop is loading 104 bytes (13 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	47
nb uops	46
loop length	181
used x86 registers	9
used mmx registers	0
used xmm registers	11
used ymm registers	0
used zmm registers	0
nb stack references	1
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.33 cycles
front end	8.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.50	5.40	4.33	4.33	0.00	5.40	8.50	0.00	0.00	0.00	5.20	4.33
cycles	8.50	5.40	4.33	4.33	0.00	5.40	8.50	0.00	0.00	0.00	5.20	4.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.33
Dispatch	8.50
Overall L1	8.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.50 cycles. At this rate:

6% of peak load performance is reached (12.24 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 46f9e3

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOV (%RDI,%R9,8),%R10	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP (%R13,%R10,8),%RDX	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JLE 46f9f3 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1283>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP %RAX,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JNE 46fa09 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1299>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VMOVSD (%R15,%R9,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM14,%XMM15	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM15,%XMM3	1	1	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 46fa09 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1299>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VADDSD %XMM14,%XMM2,%XMM2	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
INC %R9	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI,%R9,8),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP (%R13,%RCX,8),%RDX	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JLE 46fa1c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x12ac>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JNE 46fa30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x12c0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VMOVSD (%R15,%R9,8),%XMM4	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM4,%XMM7	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM7,%XMM3	1	1	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 46fa30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x12c0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VADDSD %XMM4,%XMM2,%XMM2	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
LEA 0x1(%R9),%R10	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDI,%R10,8),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP (%R13,%RCX,8),%RDX	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JLE 46fa44 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x12d4>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JNE 46fa5a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x12ea>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VMOVSD (%R15,%R10,8),%XMM9	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM9,%XMM8	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM8,%XMM3	1	1	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 46fa5a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x12ea>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VADDSD %XMM9,%XMM2,%XMM2	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
LEA 0x2(%R9),%R10	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDI,%R10,8),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP (%R13,%RCX,8),%RDX	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JLE 46fa6e <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x12fe>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JNE 46fa84 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1314>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VMOVSD (%R15,%R10,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM11,%XMM12	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM12,%XMM3	1	1	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 46fa84 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1314>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VADDSD %XMM11,%XMM2,%XMM2	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
MOV -0xd0(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
ADD $0x3,%R9	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 46f9e3 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1273>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code