OV - exec - Loop 719

	Loop Id: 719	Module: exec	Source: par_lr_interp.c:1644-1651	Coverage: 0.04%

0x4710a0 VMOVSD	(%R15,%R9,8),%XMM12    [3]

0x4710a6 VMULSD	%XMM0,%XMM12,%XMM15

0x4710aa VCOMISD	%XMM15,%XMM2

0x4710af JA	471825

0x4710b5 LEA	0x1(%R9),%RCX

0x4710b9 MOV	(%RDI,%RCX,8),%R9    [4]

0x4710bd MOV	(%R13,%R9,8),%RSI    [5]

0x4710c2 CMP	%RSI,%RDX

0x4710c5 JG	4712b8

0x4710cb VMOVSD	(%R15,%RCX,8),%XMM14    [3]

0x4710d1 VMULSD	%XMM0,%XMM14,%XMM4

0x4710d5 VCOMISD	%XMM4,%XMM2

0x4710d9 JA	4712a6

0x4710df LEA	0x1(%RCX),%R9

0x4710e3 MOV	(%RDI,%R9,8),%R10    [4]

0x4710e7 MOV	(%R13,%R10,8),%RBX    [5]

0x4710ec CMP	%RBX,%RDX

0x4710ef JG	47127e

0x4710f5 VMOVSD	(%R15,%R9,8),%XMM12    [3]

0x4710fb VMULSD	%XMM0,%XMM12,%XMM8

0x4710ff VCOMISD	%XMM8,%XMM2

0x471104 JA	47126d

0x47110a LEA	0x2(%RCX),%R9

0x47110e MOV	(%RDI,%R9,8),%R10    [4]

0x471112 MOV	(%R13,%R10,8),%RBX    [5]

0x471117 CMP	%RBX,%RDX

0x47111a JG	471245

0x471120 VMOVSD	(%R15,%R9,8),%XMM3    [3]

0x471126 VMULSD	%XMM0,%XMM3,%XMM14

0x47112a VCOMISD	%XMM14,%XMM2

0x47112f JA	471234

0x471135 LEA	0x3(%RCX),%R9

0x471139 MOV	-0xd0(%RBP),%RCX    [6]

0x471140 CMP	%RCX,%R9

0x471143 JGE	4712e0

0x471149 MOV	(%RDI,%R9,8),%RSI    [4]

0x47114d MOV	(%R13,%RSI,8),%RCX    [5]

0x471152 CMP	%RCX,%RDX

0x471155 JLE	4710a0

0x47115b CMP	%RAX,%RSI

0x47115e JNE	4710b5

0x471164 VMOVSD	(%R15,%R9,8),%XMM13    [3]

0x47116a VMULSD	%XMM0,%XMM13,%XMM3

0x47116e VCOMISD	%XMM3,%XMM2

0x471172 JBE	4710b5

0x471178 VFMADD231SD	%XMM13,%XMM7,%XMM1

0x47117d JMP	4710b5

0x471234 MOV	-0x48(%RBP),%RSI    [6]

0x471238 LEA	(%RSI,%RBX,8),%RBX

0x47123c VFMADD213SD	(%RBX),%XMM7,%XMM3    [8]

0x471241 VMOVSD	%XMM3,(%RBX)    [8]

0x471245 CMP	%RAX,%R10

0x471248 JNE	471135

0x47124e VMOVSD	(%R15,%R9,8),%XMM4    [3]

0x471254 VMULSD	%XMM0,%XMM4,%XMM9

0x471258 VCOMISD	%XMM9,%XMM2

0x47125d JBE	471135

0x471263 VFMADD231SD	%XMM4,%XMM7,%XMM1

0x471268 JMP	471135

0x47126d MOV	-0x48(%RBP),%RSI    [6]

0x471271 LEA	(%RSI,%RBX,8),%RBX

0x471275 VFMADD213SD	(%RBX),%XMM7,%XMM12    [7]

0x47127a VMOVSD	%XMM12,(%RBX)    [7]

0x47127e CMP	%RAX,%R10

0x471281 JNE	47110a

0x471287 VMOVSD	(%R15,%R9,8),%XMM15    [3]

0x47128d VMULSD	%XMM0,%XMM15,%XMM13

0x471291 VCOMISD	%XMM13,%XMM2

0x471296 JBE	47110a

0x47129c VFMADD231SD	%XMM15,%XMM7,%XMM1

0x4712a1 JMP	47110a

0x4712a6 MOV	-0x48(%RBP),%RBX    [6]

0x4712aa LEA	(%RBX,%RSI,8),%R10

0x4712ae VFMADD213SD	(%R10),%XMM7,%XMM14    [2]

0x4712b3 VMOVSD	%XMM14,(%R10)    [2]

0x4712b8 CMP	%RAX,%R9

0x4712bb JNE	4710df

0x4712c1 VMOVSD	(%R15,%RCX,8),%XMM9    [3]

0x4712c7 VMULSD	%XMM0,%XMM9,%XMM11

0x4712cb VCOMISD	%XMM11,%XMM2

0x4712d0 JBE	4710df

0x4712d6 VFMADD231SD	%XMM9,%XMM7,%XMM1

0x4712db JMP	4710df

0x471825 MOV	-0x48(%RBP),%RBX    [6]

0x471829 LEA	(%RBX,%RCX,8),%R10

0x47182d VFMADD213SD	(%R10),%XMM7,%XMM12    [1]

0x471832 VMOVSD	%XMM12,(%R10)    [1]

0x471837 JMP	47115b

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1644 - 1651

--------------------------------------------------------------------------------

1644:                  for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1645:                  {

1646:                    i2 = A_diag_j[jj1];

1647:                    if(P_marker[i2] >= jj_begin_row && (sgn*A_diag_data[jj1]) < 0)

1648:                       P_diag_data[P_marker[i2]] +=

1649:                       distribute*A_diag_data[jj1];

1650:                        if(i2 == i && (sgn*A_diag_data[jj1]) < 0)

1651:                          diagonal += distribute*A_diag_data[jj1];

Coverage (%)	Name	Source Location	Module
○98.61	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.39	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	1.83
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source	par_lr_interp.c:1644-1651
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.67
CQA cycles if no scalar integer	14.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	1.83
Front-end cycles	14.67
P0 cycles	14.00
P1 cycles	14.00
P2 cycles	8.33
P3 cycles	8.33
P4 cycles	2.00
P5 cycles	4.60
P6 cycles	13.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	4.40
P11 cycles	8.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	88.00
Nb uops	88.00
Nb loads	25.00
Nb stores	4.00
Nb stack references	2.00
FLOP/cycle	1.64
Nb FLOP add-sub	0.00
Nb FLOP mul	8.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.82
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	1.83
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source	par_lr_interp.c:1644-1651
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.67
CQA cycles if no scalar integer	14.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	1.83
Front-end cycles	14.67
P0 cycles	14.00
P1 cycles	14.00
P2 cycles	8.33
P3 cycles	8.33
P4 cycles	2.00
P5 cycles	4.60
P6 cycles	13.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	4.40
P11 cycles	8.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	88.00
Nb uops	88.00
Nb loads	25.00
Nb stores	4.00
Nb stack references	2.00
FLOP/cycle	1.64
Nb FLOP add-sub	0.00
Nb FLOP mul	8.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.82
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source file and lines	par_lr_interp.c:1644-1651
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1644-1651.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 2401 paths individually, rerun with max-paths=2401
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 2401 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 14.67 to 1.83 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 8 FMA (fused multiply-add) operations.

Type of elements and instruction set

24 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
16: multiply (8 inside FMA instructions)

The binary loop is loading 200 bytes (25 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	88
nb uops	88
loop length	421
used x86 registers	11
used mmx registers	0
used xmm registers	13
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.67 cycles
front end	14.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	14.00	14.00	8.33	8.33	2.00	4.60	13.00	2.00	2.00	2.00	4.40	8.33
cycles	14.00	14.00	8.33	8.33	2.00	4.60	13.00	2.00	2.00	2.00	4.40	8.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.67
Dispatch	14.00
Overall L1	14.67

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.67 cycles. At this rate:

7% of peak load performance is reached (13.64 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.18 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 471149

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVSD (%R15,%R9,8),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM12,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM15,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JA 471825 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x30b5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%R9),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDI,%RCX,8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R13,%R9,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JG 4712b8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2b48>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%RCX,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM14,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM4,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JA 4712a6 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2b36>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%RCX),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDI,%R9,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R13,%R10,8),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RBX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JG 47127e <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2b0e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%R9,8),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM12,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM8,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JA 47126d <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2afd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x2(%RCX),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDI,%R9,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R13,%R10,8),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RBX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JG 471245 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2ad5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%R9,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM3,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM14,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JA 471234 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2ac4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x3(%RCX),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0xd0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4712e0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2b70>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%RDI,%R9,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R13,%RSI,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 4710a0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2930>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 4710b5 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2945>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%R9,8),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM13,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM3,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 4710b5 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2945>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VFMADD231SD %XMM13,%XMM7,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 4710b5 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2945>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0x48(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%RBX,8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VFMADD213SD (%RBX),%XMM7,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM3,(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 471135 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x29c5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%R9,8),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM4,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM9,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 471135 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x29c5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VFMADD231SD %XMM4,%XMM7,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 471135 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x29c5>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0x48(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%RBX,8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VFMADD213SD (%RBX),%XMM7,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM12,(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 47110a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x299a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%R9,8),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM15,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM13,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 47110a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x299a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VFMADD231SD %XMM15,%XMM7,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 47110a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x299a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0x48(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RBX,%RSI,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VFMADD213SD (%R10),%XMM7,%XMM14	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM14,(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RAX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 4710df <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x296f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%RCX,8),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM9,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM11,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 4710df <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x296f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VFMADD231SD %XMM9,%XMM7,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 4710df <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x296f>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0x48(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RBX,%RCX,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VFMADD213SD (%R10),%XMM7,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM12,(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 47115b <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x29eb>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source file and lines	par_lr_interp.c:1644-1651
Module	exec

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 2401 paths individually, rerun with max-paths=2401
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 14.67 to 1.83 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 8 FMA (fused multiply-add) operations.

Type of elements and instruction set

24 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
16: multiply (8 inside FMA instructions)

The binary loop is loading 200 bytes (25 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	88
nb uops	88
loop length	421
used x86 registers	11
used mmx registers	0
used xmm registers	13
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.67 cycles
front end	14.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	14.00	14.00	8.33	8.33	2.00	4.60	13.00	2.00	2.00	2.00	4.40	8.33
cycles	14.00	14.00	8.33	8.33	2.00	4.60	13.00	2.00	2.00	2.00	4.40	8.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.67
Dispatch	14.00
Overall L1	14.67

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.67 cycles. At this rate:

7% of peak load performance is reached (13.64 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.18 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 471149

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVSD (%R15,%R9,8),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM12,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM15,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JA 471825 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x30b5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%R9),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDI,%RCX,8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R13,%R9,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JG 4712b8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2b48>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%RCX,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM14,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM4,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JA 4712a6 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2b36>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%RCX),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDI,%R9,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R13,%R10,8),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RBX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JG 47127e <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2b0e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%R9,8),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM12,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM8,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JA 47126d <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2afd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x2(%RCX),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDI,%R9,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R13,%R10,8),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RBX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JG 471245 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2ad5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%R9,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM3,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM14,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JA 471234 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2ac4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x3(%RCX),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0xd0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4712e0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2b70>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%RDI,%R9,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R13,%RSI,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 4710a0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2930>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 4710b5 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2945>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%R9,8),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM13,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM3,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 4710b5 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2945>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VFMADD231SD %XMM13,%XMM7,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 4710b5 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2945>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0x48(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%RBX,8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VFMADD213SD (%RBX),%XMM7,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM3,(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 471135 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x29c5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%R9,8),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM4,%XMM9	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM9,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 471135 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x29c5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VFMADD231SD %XMM4,%XMM7,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 471135 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x29c5>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0x48(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%RBX,8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VFMADD213SD (%RBX),%XMM7,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM12,(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 47110a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x299a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%R9,8),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM15,%XMM13	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM13,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 47110a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x299a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VFMADD231SD %XMM15,%XMM7,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 47110a <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x299a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0x48(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RBX,%RSI,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VFMADD213SD (%R10),%XMM7,%XMM14	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM14,(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RAX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 4710df <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x296f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%RCX,8),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM0,%XMM9,%XMM11	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM11,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 4710df <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x296f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VFMADD231SD %XMM9,%XMM7,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 4710df <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x296f>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0x48(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RBX,%RCX,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VFMADD213SD (%R10),%XMM7,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM12,(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 47115b <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x29eb>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code