OV - exec - Loop 694

	Loop Id: 694	Module: exec	Source: par_multi_interp.c:554-557	Coverage: 0.01%

0x46a432 MOV	(%R13,%RAX,8),%RDX    [1]

0x46a437 CMP	%R12,(%R14,%RDX,8)    [2]

0x46a43b JE	46a77f

0x46a441 MOV	0x8(%R13,%RAX,8),%RDX    [1]

0x46a446 CMP	%R12,(%R14,%RDX,8)    [2]

0x46a44a JE	46a77f

0x46a450 MOV	0x10(%R13,%RAX,8),%RDX    [1]

0x46a455 CMP	%R12,(%R14,%RDX,8)    [2]

0x46a459 JE	46a77f

0x46a45f MOV	0x18(%R13,%RAX,8),%RDX    [1]

0x46a464 CMP	%R12,(%R14,%RDX,8)    [2]

0x46a468 JE	46a77f

0x46a46e MOV	0x20(%R13,%RAX,8),%RDX    [1]

0x46a473 CMP	%R12,(%R14,%RDX,8)    [2]

0x46a477 JE	46a77f

0x46a47d MOV	0x28(%R13,%RAX,8),%RDX    [1]

0x46a482 CMP	%R12,(%R14,%RDX,8)    [2]

0x46a486 JE	46a77f

0x46a48c MOV	0x30(%R13,%RAX,8),%RDX    [1]

0x46a491 CMP	%R12,(%R14,%RDX,8)    [2]

0x46a495 JE	46a77f

0x46a49b MOV	0x38(%R13,%RAX,8),%RDX    [1]

0x46a4a0 CMP	%R12,(%R14,%RDX,8)    [2]

0x46a4a4 JE	46a77f

0x46a4aa ADD	$0x8,%RAX

0x46a4ae CMP	%RDI,%RAX

0x46a4b1 JNE	46a432

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 554 - 557

--------------------------------------------------------------------------------

554:          for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

555:          {

556:             j1 = S_diag_j[j];

557:             if (assigned[j1] == pass-1)

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:554-557
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.67
CQA cycles if no scalar integer	5.67
CQA cycles if FP arith vectorized	5.67
CQA cycles if fully vectorized	0.71
Front-end cycles	5.67
P0 cycles	4.50
P1 cycles	2.80
P2 cycles	5.33
P3 cycles	5.33
P4 cycles	0.00
P5 cycles	2.60
P6 cycles	4.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	2.60
P11 cycles	5.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	26.00
Nb loads	16.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.59
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:554-557
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.67
CQA cycles if no scalar integer	5.67
CQA cycles if FP arith vectorized	5.67
CQA cycles if fully vectorized	0.71
Front-end cycles	5.67
P0 cycles	4.50
P1 cycles	2.80
P2 cycles	5.33
P3 cycles	5.33
P4 cycles	0.00
P5 cycles	2.60
P6 cycles	4.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	2.60
P11 cycles	5.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	26.00
Nb loads	16.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.59
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:554-557
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:554-557.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.67 to 0.71 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 128 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	27
nb uops	26
loop length	133
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.67 cycles
front end	5.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.50	2.80	5.33	5.33	0.00	2.60	4.50	0.00	0.00	0.00	2.60	5.33
cycles	4.50	2.80	5.33	5.33	0.00	2.60	4.50	0.00	0.00	0.00	2.60	5.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.67
Dispatch	5.33
Data deps.	1.00
Overall L1	5.67

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.67 cycles. At this rate:

11% of peak load performance is reached (22.59 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.67 to 5.33 cycles (1.06x speedup).

ASM code

In the binary file, the address of the loop is: 46a432

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOV (%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV 0x8(%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV 0x10(%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV 0x18(%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV 0x20(%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV 0x28(%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV 0x30(%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV 0x38(%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDI,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 46a432 <hypre_BoomerAMGBuildMultipass+0x1112>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:554-557
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.67 to 0.71 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 128 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	27
nb uops	26
loop length	133
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.67 cycles
front end	5.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.50	2.80	5.33	5.33	0.00	2.60	4.50	0.00	0.00	0.00	2.60	5.33
cycles	4.50	2.80	5.33	5.33	0.00	2.60	4.50	0.00	0.00	0.00	2.60	5.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.67
Dispatch	5.33
Data deps.	1.00
Overall L1	5.67

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.67 cycles. At this rate:

11% of peak load performance is reached (22.59 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 46a432

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOV (%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV 0x8(%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV 0x10(%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV 0x18(%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV 0x20(%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV 0x28(%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV 0x30(%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV 0x38(%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDI,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 46a432 <hypre_BoomerAMGBuildMultipass+0x1112>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code