OV - exec - Loop 692

	Loop Id: 692	Module: exec	Source: par_multi_interp.c:550-576 [...]	Coverage: 0.07%

0x46a34c MOV	-0x250(%RBP),%RBX

0x46a353 LEA	(%RBX,%RSI,8),%R9

0x46a357 MOV	(%R9),%RCX

0x46a35a LEA	(,%RCX,8),%RBX

0x46a362 MOV	(%R15,%RCX,8),%RAX

0x46a366 MOV	0x8(%R15,%RBX,1),%RDI

0x46a36b CMP	%RDI,%RAX

0x46a36e JGE	46a4b7

0x46a374 MOV	%RDI,%RDX

0x46a377 SUB	%RAX,%RDX

0x46a37a AND	$0x7,%EDX

0x46a37d JE	46a432

0x46a383 CMP	$0x1,%RDX

0x46a387 JE	46a417

0x46a38d CMP	$0x2,%RDX

0x46a391 JE	46a405

0x46a393 CMP	$0x3,%RDX

0x46a397 JE	46a3f3

0x46a399 CMP	$0x4,%RDX

0x46a39d JE	46a3e1

0x46a39f CMP	$0x5,%RDX

0x46a3a3 JE	46a3cf

0x46a3a5 CMP	$0x6,%RDX

0x46a3a9 JE	46a3bd

0x46a3ab MOV	(%R13,%RAX,8),%RDX

0x46a3b0 INC	%RAX

0x46a3b3 CMP	%R12,(%R14,%RDX,8)

0x46a3b7 JE	46a77f

0x46a3bd MOV	(%R13,%RAX,8),%RDX

0x46a3c2 INC	%RAX

0x46a3c5 CMP	%R12,(%R14,%RDX,8)

0x46a3c9 JE	46a77f

0x46a3cf MOV	(%R13,%RAX,8),%RDX

0x46a3d4 INC	%RAX

0x46a3d7 CMP	%R12,(%R14,%RDX,8)

0x46a3db JE	46a77f

0x46a3e1 MOV	(%R13,%RAX,8),%RDX

0x46a3e6 INC	%RAX

0x46a3e9 CMP	%R12,(%R14,%RDX,8)

0x46a3ed JE	46a77f

0x46a3f3 MOV	(%R13,%RAX,8),%RDX

0x46a3f8 INC	%RAX

0x46a3fb CMP	%R12,(%R14,%RDX,8)

0x46a3ff JE	46a77f

0x46a405 MOV	(%R13,%RAX,8),%RDX

0x46a40a INC	%RAX

0x46a40d CMP	%R12,(%R14,%RDX,8)

0x46a411 JE	46a77f

0x46a417 MOV	(%R13,%RAX,8),%RDX

0x46a41c CMP	%R12,(%R14,%RDX,8)

0x46a420 JE	46a77f

0x46a426 INC	%RAX

0x46a429 CMP	%RDI,%RAX

0x46a42c JE	46a4b7

  (694) 0x46a432 MOV	(%R13,%RAX,8),%RDX

  (694) 0x46a437 CMP	%R12,(%R14,%RDX,8)

  (694) 0x46a43b JE	46a77f

  (694) 0x46a441 MOV	0x8(%R13,%RAX,8),%RDX

  (694) 0x46a446 CMP	%R12,(%R14,%RDX,8)

  (694) 0x46a44a JE	46a77f

  (694) 0x46a450 MOV	0x10(%R13,%RAX,8),%RDX

  (694) 0x46a455 CMP	%R12,(%R14,%RDX,8)

  (694) 0x46a459 JE	46a77f

  (694) 0x46a45f MOV	0x18(%R13,%RAX,8),%RDX

  (694) 0x46a464 CMP	%R12,(%R14,%RDX,8)

  (694) 0x46a468 JE	46a77f

  (694) 0x46a46e MOV	0x20(%R13,%RAX,8),%RDX

  (694) 0x46a473 CMP	%R12,(%R14,%RDX,8)

  (694) 0x46a477 JE	46a77f

  (694) 0x46a47d MOV	0x28(%R13,%RAX,8),%RDX

  (694) 0x46a482 CMP	%R12,(%R14,%RDX,8)

  (694) 0x46a486 JE	46a77f

  (694) 0x46a48c MOV	0x30(%R13,%RAX,8),%RDX

  (694) 0x46a491 CMP	%R12,(%R14,%RDX,8)

  (694) 0x46a495 JE	46a77f

  (694) 0x46a49b MOV	0x38(%R13,%RAX,8),%RDX

  (694) 0x46a4a0 CMP	%R12,(%R14,%RDX,8)

  (694) 0x46a4a4 JE	46a77f

  (694) 0x46a4aa ADD	$0x8,%RAX

  (694) 0x46a4ae CMP	%RDI,%RAX

  (694) 0x46a4b1 JNE	46a432

0x46a4b7 MOV	-0x338(%RBP),%RDI

0x46a4be MOV	(%RDI,%RCX,8),%RAX

0x46a4c2 MOV	0x8(%RDI,%RBX,1),%RBX

0x46a4c7 CMP	%RBX,%RAX

0x46a4ca JGE	46a607

0x46a4d0 MOV	%RBX,%RDX

0x46a4d3 SUB	%RAX,%RDX

0x46a4d6 AND	$0x7,%EDX

0x46a4d9 JE	46a587

0x46a4df CMP	$0x1,%RDX

0x46a4e3 JE	46a56d

0x46a4e9 CMP	$0x2,%RDX

0x46a4ed JE	46a55c

0x46a4ef CMP	$0x3,%RDX

0x46a4f3 JE	46a54b

0x46a4f5 CMP	$0x4,%RDX

0x46a4f9 JE	46a53a

0x46a4fb CMP	$0x5,%RDX

0x46a4ff JE	46a529

0x46a501 CMP	$0x6,%RDX

0x46a505 JE	46a518

0x46a507 MOV	(%R10,%RAX,8),%RDI

0x46a50b INC	%RAX

0x46a50e CMP	%R12,(%R8,%RDI,8)

0x46a512 JE	46a77f

0x46a518 MOV	(%R10,%RAX,8),%RDX

0x46a51c INC	%RAX

0x46a51f CMP	%R12,(%R8,%RDX,8)

0x46a523 JE	46a77f

0x46a529 MOV	(%R10,%RAX,8),%RDI

0x46a52d INC	%RAX

0x46a530 CMP	%R12,(%R8,%RDI,8)

0x46a534 JE	46a77f

0x46a53a MOV	(%R10,%RAX,8),%RDX

0x46a53e INC	%RAX

0x46a541 CMP	%R12,(%R8,%RDX,8)

0x46a545 JE	46a77f

0x46a54b MOV	(%R10,%RAX,8),%RDI

0x46a54f INC	%RAX

0x46a552 CMP	%R12,(%R8,%RDI,8)

0x46a556 JE	46a77f

0x46a55c MOV	(%R10,%RAX,8),%RDX

0x46a560 INC	%RAX

0x46a563 CMP	%R12,(%R8,%RDX,8)

0x46a567 JE	46a77f

0x46a56d MOV	(%R10,%RAX,8),%RDI

0x46a571 CMP	%R12,(%R8,%RDI,8)

0x46a575 JE	46a77f

0x46a57b INC	%RAX

0x46a57e CMP	%RBX,%RAX

0x46a581 JE	46a607

  (693) 0x46a587 MOV	(%R10,%RAX,8),%RDX

  (693) 0x46a58b CMP	%R12,(%R8,%RDX,8)

  (693) 0x46a58f JE	46a77f

  (693) 0x46a595 MOV	0x8(%R10,%RAX,8),%RDI

  (693) 0x46a59a CMP	%R12,(%R8,%RDI,8)

  (693) 0x46a59e JE	46a77f

  (693) 0x46a5a4 MOV	0x10(%R10,%RAX,8),%RDX

  (693) 0x46a5a9 CMP	%R12,(%R8,%RDX,8)

  (693) 0x46a5ad JE	46a77f

  (693) 0x46a5b3 MOV	0x18(%R10,%RAX,8),%RDI

  (693) 0x46a5b8 CMP	%R12,(%R8,%RDI,8)

  (693) 0x46a5bc JE	46a77f

  (693) 0x46a5c2 MOV	0x20(%R10,%RAX,8),%RDX

  (693) 0x46a5c7 CMP	%R12,(%R8,%RDX,8)

  (693) 0x46a5cb JE	46a77f

  (693) 0x46a5d1 MOV	0x28(%R10,%RAX,8),%RDI

  (693) 0x46a5d6 CMP	%R12,(%R8,%RDI,8)

  (693) 0x46a5da JE	46a77f

  (693) 0x46a5e0 MOV	0x30(%R10,%RAX,8),%RDX

  (693) 0x46a5e5 CMP	%R12,(%R8,%RDX,8)

  (693) 0x46a5e9 JE	46a77f

  (693) 0x46a5ef MOV	0x38(%R10,%RAX,8),%RDI

  (693) 0x46a5f4 CMP	%R12,(%R8,%RDI,8)

  (693) 0x46a5f8 JE	46a77f

  (693) 0x46a5fe ADD	$0x8,%RAX

  (693) 0x46a602 CMP	%RBX,%RAX

  (693) 0x46a605 JNE	46a587

0x46a607 DEC	%RSI

0x46a60a CMP	%RSI,%R11

0x46a60d JLE	46a34c

0x46a77f MOV	-0x250(%RBP),%RAX

0x46a786 LEA	(%RAX,%R11,8),%RBX

0x46a78a MOV	(%RBX),%RDX

0x46a78d INC	%R11

0x46a790 MOV	%RDX,(%R9)

0x46a793 MOV	-0x268(%RBP),%R9

0x46a79a MOV	%RCX,(%RBX)

0x46a79d MOV	%R9,(%R14,%RCX,8)

0x46a7a1 JMP	46a60a

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 550 - 576

--------------------------------------------------------------------------------

550:       for (i = pass_array_size-1; i > cnt-1; i--)

551:       {

552:          i1 = pass_array[i];

553:          no_break = 1;

554:          for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

555:          {

556:             j1 = S_diag_j[j];

557:             if (assigned[j1] == pass-1)

[...]

568:             for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

569:             {

570:                j1 = S_offd_j[j];

571:                if (assigned_offd[j1] == pass-1)

572:                {

573:                   pass_array[i++] = pass_array[cnt];

574:                   pass_array[cnt++] = i1;

575:                   assigned[i1] = pass;

576:                   break;

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.32
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:550-554,par_multi_interp.c:557-557,par_multi_interp.c:568-568,par_multi_interp.c:571-576
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	21.83
CQA cycles if no scalar integer	21.83
CQA cycles if FP arith vectorized	21.83
CQA cycles if fully vectorized	2.73
Front-end cycles	21.83
P0 cycles	16.50
P1 cycles	11.80
P2 cycles	12.67
P3 cycles	12.67
P4 cycles	1.50
P5 cycles	11.60
P6 cycles	16.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	11.60
P11 cycles	12.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	117.00
Nb uops	117.00
Nb loads	38.00
Nb stores	3.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.02
Bytes prefetched	0.00
Bytes loaded	304.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.32
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:550-554,par_multi_interp.c:557-557,par_multi_interp.c:568-568,par_multi_interp.c:571-576
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	21.83
CQA cycles if no scalar integer	21.83
CQA cycles if FP arith vectorized	21.83
CQA cycles if fully vectorized	2.73
Front-end cycles	21.83
P0 cycles	16.50
P1 cycles	11.80
P2 cycles	12.67
P3 cycles	12.67
P4 cycles	1.50
P5 cycles	11.60
P6 cycles	16.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	11.60
P11 cycles	12.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	117.00
Nb uops	117.00
Nb loads	38.00
Nb stores	3.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.02
Bytes prefetched	0.00
Bytes loaded	304.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:550-576
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:550-557,568-576.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:550-554,557,568,571-576.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 1820 paths individually, rerun with max-paths=1820
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 1820 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 21.83 to 2.73 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 304 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	117
nb uops	117
loop length	489
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.83 cycles
front end	21.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	16.50	11.80	12.67	12.67	1.50	11.60	16.50	1.50	1.50	1.50	11.60	12.67
cycles	16.50	11.80	12.67	12.67	1.50	11.60	16.50	1.50	1.50	1.50	11.60	12.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.83
Dispatch	16.50
Overall L1	21.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 21.83 cycles. At this rate:

7% of peak load performance is reached (13.92 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.10 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 21.83 to 16.50 cycles (1.32x speedup).

ASM code

In the binary file, the address of the loop is: 46a34c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x250(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RBX,%RSI,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R9),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RCX,8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R15,%RCX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R15,%RBX,1),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 46a4b7 <hypre_BoomerAMGBuildMultipass+0x1197>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x7,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 46a432 <hypre_BoomerAMGBuildMultipass+0x1112>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a417 <hypre_BoomerAMGBuildMultipass+0x10f7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a405 <hypre_BoomerAMGBuildMultipass+0x10e5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a3f3 <hypre_BoomerAMGBuildMultipass+0x10d3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a3e1 <hypre_BoomerAMGBuildMultipass+0x10c1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a3cf <hypre_BoomerAMGBuildMultipass+0x10af>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a3bd <hypre_BoomerAMGBuildMultipass+0x109d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a4b7 <hypre_BoomerAMGBuildMultipass+0x1197>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x338(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI,%RCX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RDI,%RBX,1),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RBX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 46a607 <hypre_BoomerAMGBuildMultipass+0x12e7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x7,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 46a587 <hypre_BoomerAMGBuildMultipass+0x1267>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a56d <hypre_BoomerAMGBuildMultipass+0x124d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a55c <hypre_BoomerAMGBuildMultipass+0x123c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a54b <hypre_BoomerAMGBuildMultipass+0x122b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a53a <hypre_BoomerAMGBuildMultipass+0x121a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a529 <hypre_BoomerAMGBuildMultipass+0x1209>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a518 <hypre_BoomerAMGBuildMultipass+0x11f8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R10,%RAX,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,(%R8,%RDI,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R10,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,(%R8,%RDX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R10,%RAX,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,(%R8,%RDI,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R10,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,(%R8,%RDX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R10,%RAX,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,(%R8,%RDI,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R10,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,(%R8,%RDX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R10,%RAX,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R12,(%R8,%RDI,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RBX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a607 <hypre_BoomerAMGBuildMultipass+0x12e7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
DEC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RSI,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 46a34c <hypre_BoomerAMGBuildMultipass+0x102c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x250(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RAX,%R11,8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RBX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,(%R9)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x268(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,(%R14,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 46a60a <hypre_BoomerAMGBuildMultipass+0x12ea>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:550-576
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 1820 paths individually, rerun with max-paths=1820
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 304 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	117
nb uops	117
loop length	489
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.83 cycles
front end	21.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	16.50	11.80	12.67	12.67	1.50	11.60	16.50	1.50	1.50	1.50	11.60	12.67
cycles	16.50	11.80	12.67	12.67	1.50	11.60	16.50	1.50	1.50	1.50	11.60	12.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.83
Dispatch	16.50
Overall L1	21.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 21.83 cycles. At this rate:

7% of peak load performance is reached (13.92 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.10 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 46a34c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x250(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RBX,%RSI,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R9),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RCX,8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R15,%RCX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R15,%RBX,1),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 46a4b7 <hypre_BoomerAMGBuildMultipass+0x1197>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x7,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 46a432 <hypre_BoomerAMGBuildMultipass+0x1112>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a417 <hypre_BoomerAMGBuildMultipass+0x10f7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a405 <hypre_BoomerAMGBuildMultipass+0x10e5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a3f3 <hypre_BoomerAMGBuildMultipass+0x10d3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a3e1 <hypre_BoomerAMGBuildMultipass+0x10c1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a3cf <hypre_BoomerAMGBuildMultipass+0x10af>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a3bd <hypre_BoomerAMGBuildMultipass+0x109d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R13,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R12,(%R14,%RDX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a4b7 <hypre_BoomerAMGBuildMultipass+0x1197>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x338(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI,%RCX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RDI,%RBX,1),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RBX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 46a607 <hypre_BoomerAMGBuildMultipass+0x12e7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x7,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 46a587 <hypre_BoomerAMGBuildMultipass+0x1267>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a56d <hypre_BoomerAMGBuildMultipass+0x124d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a55c <hypre_BoomerAMGBuildMultipass+0x123c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a54b <hypre_BoomerAMGBuildMultipass+0x122b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a53a <hypre_BoomerAMGBuildMultipass+0x121a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a529 <hypre_BoomerAMGBuildMultipass+0x1209>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a518 <hypre_BoomerAMGBuildMultipass+0x11f8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R10,%RAX,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,(%R8,%RDI,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R10,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,(%R8,%RDX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R10,%RAX,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,(%R8,%RDI,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R10,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,(%R8,%RDX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R10,%RAX,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,(%R8,%RDI,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R10,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,(%R8,%RDX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R10,%RAX,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R12,(%R8,%RDI,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 46a77f <hypre_BoomerAMGBuildMultipass+0x145f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RBX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 46a607 <hypre_BoomerAMGBuildMultipass+0x12e7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
DEC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RSI,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 46a34c <hypre_BoomerAMGBuildMultipass+0x102c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x250(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RAX,%R11,8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RBX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,(%R9)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x268(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,(%R14,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 46a60a <hypre_BoomerAMGBuildMultipass+0x12ea>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code