OV - exec - Loop 614

	Loop Id: 614	Module: exec	Source: par_multi_interp.c:1811-1837	Coverage: 0.82%

0x466f90 MOV	-0x88(%RBP),%RDX

0x466f97 MOV	-0x48(%RBP),%R8

0x466f9b MOV	(%RDX,%RCX,8),%RCX

0x466f9f CMP	%RCX,(%RDX,%R8,1)

0x466fa3 JE	466fde

0x466fa5 ADD	$0x8,%RSI

0x466fa9 ADD	$0x8,%RAX

0x466fad CMP	%RSI,-0x38(%RBP)

0x466fb1 JE	466ff0

0x466fb3 MOV	(%RSI),%RCX

0x466fb6 MOV	-0x40(%RBP),%R15

0x466fba LEA	(,%RCX,8),%R8

0x466fc2 CMP	(%R15,%RCX,8),%RDI

0x466fc6 JE	467128

0x466fcc MOV	-0x80(%RBP),%R14

0x466fd0 CMPQ	$-0x3,(%R14,%RCX,8)

0x466fd5 JE	466fa5

0x466fd7 CMPQ	$0x1,-0x50(%RBP)

0x466fdc JNE	466f90

0x466fde ADD	$0x8,%RSI

0x466fe2 VADDSD	(%RAX),%XMM0,%XMM0

0x466fe6 ADD	$0x8,%RAX

0x466fea CMP	%RSI,-0x38(%RBP)

0x466fee JNE	466fb3

0x467128 MOV	-0xc0(%RBP),%R15

0x46712f MOV	(%R15,%RCX,8),%RDX

0x467133 MOV	0x8(%R15,%R8,1),%R15

0x467138 CMP	%R15,%RDX

0x46713b JGE	4672aa

0x467141 MOV	%R15,%R14

0x467144 SUB	%RDX,%R14

0x467147 AND	$0x3,%R14D

0x46714b JE	4671ee

0x467151 CMP	$0x1,%R14

0x467155 JE	4671b7

0x467157 CMP	$0x2,%R14

0x46715b JE	467189

0x46715d VMOVSD	(%RAX),%XMM5

0x467161 MOV	(%R13,%RDX,8),%R14

0x467166 VMULSD	(%R12,%RDX,8),%XMM5,%XMM6

0x46716c MOV	(%R9,%R14,8),%R14

0x467170 INC	%RDX

0x467173 LEA	(%R12,%R14,8),%R14

0x467177 VADDSD	(%R14),%XMM6,%XMM7

0x46717c VADDSD	%XMM6,%XMM1,%XMM1

0x467180 VADDSD	%XMM6,%XMM0,%XMM0

0x467184 VMOVSD	%XMM7,(%R14)

0x467189 VMOVSD	(%RAX),%XMM8

0x46718d MOV	(%R13,%RDX,8),%R14

0x467192 VMULSD	(%R12,%RDX,8),%XMM8,%XMM9

0x467198 MOV	(%R9,%R14,8),%R14

0x46719c INC	%RDX

0x46719f LEA	(%R12,%R14,8),%R14

0x4671a3 VADDSD	(%R14),%XMM9,%XMM10

0x4671a8 VADDSD	%XMM9,%XMM1,%XMM1

0x4671ad VADDSD	%XMM9,%XMM0,%XMM0

0x4671b2 VMOVSD	%XMM10,(%R14)

0x4671b7 VMOVSD	(%RAX),%XMM11

0x4671bb MOV	(%R13,%RDX,8),%R14

0x4671c0 VMULSD	(%R12,%RDX,8),%XMM11,%XMM12

0x4671c6 MOV	(%R9,%R14,8),%R14

0x4671ca INC	%RDX

0x4671cd LEA	(%R12,%R14,8),%R14

0x4671d1 VADDSD	(%R14),%XMM12,%XMM13

0x4671d6 VADDSD	%XMM12,%XMM1,%XMM1

0x4671db VADDSD	%XMM12,%XMM0,%XMM0

0x4671e0 VMOVSD	%XMM13,(%R14)

0x4671e5 CMP	%R15,%RDX

0x4671e8 JE	4672aa

  (616) 0x4671ee VMOVSD	(%RAX),%XMM14

  (616) 0x4671f2 MOV	(%R13,%RDX,8),%R14

  (616) 0x4671f7 VMULSD	(%R12,%RDX,8),%XMM14,%XMM15

  (616) 0x4671fd MOV	(%R9,%R14,8),%R14

  (616) 0x467201 LEA	(%R12,%R14,8),%R14

  (616) 0x467205 VADDSD	(%R14),%XMM15,%XMM2

  (616) 0x46720a VADDSD	%XMM15,%XMM1,%XMM6

  (616) 0x46720f VADDSD	%XMM15,%XMM0,%XMM7

  (616) 0x467214 VMOVSD	%XMM2,(%R14)

  (616) 0x467219 VMOVSD	(%RAX),%XMM5

  (616) 0x46721d MOV	0x8(%R13,%RDX,8),%R14

  (616) 0x467222 VMULSD	0x8(%R12,%RDX,8),%XMM5,%XMM8

  (616) 0x467229 MOV	(%R9,%R14,8),%R14

  (616) 0x46722d LEA	(%R12,%R14,8),%R14

  (616) 0x467231 VADDSD	(%R14),%XMM8,%XMM9

  (616) 0x467236 VADDSD	%XMM8,%XMM6,%XMM10

  (616) 0x46723b VADDSD	%XMM8,%XMM7,%XMM11

  (616) 0x467240 VMOVSD	%XMM9,(%R14)

  (616) 0x467245 VMOVSD	(%RAX),%XMM12

  (616) 0x467249 MOV	0x10(%R13,%RDX,8),%R14

  (616) 0x46724e VMULSD	0x10(%R12,%RDX,8),%XMM12,%XMM13

  (616) 0x467255 MOV	(%R9,%R14,8),%R14

  (616) 0x467259 LEA	(%R12,%R14,8),%R14

  (616) 0x46725d VADDSD	(%R14),%XMM13,%XMM1

  (616) 0x467262 VADDSD	%XMM13,%XMM10,%XMM14

  (616) 0x467267 VADDSD	%XMM13,%XMM11,%XMM0

  (616) 0x46726c VMOVSD	%XMM1,(%R14)

  (616) 0x467271 VMOVSD	(%RAX),%XMM15

  (616) 0x467275 MOV	0x18(%R13,%RDX,8),%R14

  (616) 0x46727a VMULSD	0x18(%R12,%RDX,8),%XMM15,%XMM12

  (616) 0x467281 MOV	(%R9,%R14,8),%R14

  (616) 0x467285 ADD	$0x4,%RDX

  (616) 0x467289 LEA	(%R12,%R14,8),%R14

  (616) 0x46728d VADDSD	(%R14),%XMM12,%XMM2

  (616) 0x467292 VADDSD	%XMM12,%XMM14,%XMM1

  (616) 0x467297 VADDSD	%XMM12,%XMM0,%XMM0

  (616) 0x46729c VMOVSD	%XMM2,(%R14)

  (616) 0x4672a1 CMP	%R15,%RDX

  (616) 0x4672a4 JNE	4671ee

0x4672aa MOV	-0xb8(%RBP),%R15

0x4672b1 MOV	(%R15,%RCX,8),%RDX

0x4672b5 MOV	0x8(%R15,%R8,1),%R8

0x4672ba CMP	%R8,%RDX

0x4672bd JGE	466fa5

0x4672c3 MOV	%R8,%RCX

0x4672c6 SUB	%RDX,%RCX

0x4672c9 AND	$0x3,%ECX

0x4672cc JE	467366

0x4672d2 CMP	$0x1,%RCX

0x4672d6 JE	467332

0x4672d8 CMP	$0x2,%RCX

0x4672dc JE	467307

0x4672de VMOVSD	(%RAX),%XMM6

0x4672e2 MOV	(%R10,%RDX,8),%R14

0x4672e6 VMULSD	(%R11,%RDX,8),%XMM6,%XMM7

0x4672ec MOV	(%RBX,%R14,8),%R15

0x4672f0 INC	%RDX

0x4672f3 LEA	(%R11,%R15,8),%RCX

0x4672f7 VADDSD	(%RCX),%XMM7,%XMM5

0x4672fb VADDSD	%XMM7,%XMM1,%XMM1

0x4672ff VADDSD	%XMM7,%XMM0,%XMM0

0x467303 VMOVSD	%XMM5,(%RCX)

0x467307 VMOVSD	(%RAX),%XMM8

0x46730b MOV	(%R10,%RDX,8),%R14

0x46730f VMULSD	(%R11,%RDX,8),%XMM8,%XMM9

0x467315 MOV	(%RBX,%R14,8),%R15

0x467319 INC	%RDX

0x46731c LEA	(%R11,%R15,8),%RCX

0x467320 VADDSD	(%RCX),%XMM9,%XMM10

0x467324 VADDSD	%XMM9,%XMM1,%XMM1

0x467329 VADDSD	%XMM9,%XMM0,%XMM0

0x46732e VMOVSD	%XMM10,(%RCX)

0x467332 VMOVSD	(%RAX),%XMM11

0x467336 MOV	(%R10,%RDX,8),%R14

0x46733a VMULSD	(%R11,%RDX,8),%XMM11,%XMM12

0x467340 MOV	(%RBX,%R14,8),%R15

0x467344 INC	%RDX

0x467347 LEA	(%R11,%R15,8),%RCX

0x46734b VADDSD	(%RCX),%XMM12,%XMM13

0x46734f VADDSD	%XMM12,%XMM1,%XMM1

0x467354 VADDSD	%XMM12,%XMM0,%XMM0

0x467359 VMOVSD	%XMM13,(%RCX)

0x46735d CMP	%R8,%RDX

0x467360 JE	466fa5

  (615) 0x467366 VMOVSD	(%RAX),%XMM12

  (615) 0x46736a MOV	(%R10,%RDX,8),%R14

  (615) 0x46736e VMULSD	(%R11,%RDX,8),%XMM12,%XMM14

  (615) 0x467374 MOV	(%RBX,%R14,8),%R15

  (615) 0x467378 MOV	0x8(%R10,%RDX,8),%R14

  (615) 0x46737d LEA	(%R11,%R15,8),%RCX

  (615) 0x467381 MOV	(%RBX,%R14,8),%R15

  (615) 0x467385 VADDSD	(%RCX),%XMM14,%XMM15

  (615) 0x467389 MOV	0x10(%R10,%RDX,8),%R14

  (615) 0x46738e VADDSD	%XMM14,%XMM1,%XMM1

  (615) 0x467393 VMOVSD	%XMM15,(%RCX)

  (615) 0x467397 VMOVSD	(%RAX),%XMM2

  (615) 0x46739b LEA	(%R11,%R15,8),%RCX

  (615) 0x46739f VMULSD	0x8(%R11,%RDX,8),%XMM2,%XMM6

  (615) 0x4673a6 MOV	(%RBX,%R14,8),%R15

  (615) 0x4673aa VADDSD	%XMM14,%XMM0,%XMM0

  (615) 0x4673af MOV	0x18(%R10,%RDX,8),%R14

  (615) 0x4673b4 VADDSD	(%RCX),%XMM6,%XMM7

  (615) 0x4673b8 VADDSD	%XMM6,%XMM1,%XMM8

  (615) 0x4673bc VADDSD	%XMM6,%XMM0,%XMM9

  (615) 0x4673c0 VMOVSD	%XMM7,(%RCX)

  (615) 0x4673c4 VMOVSD	(%RAX),%XMM5

  (615) 0x4673c8 LEA	(%R11,%R15,8),%RCX

  (615) 0x4673cc VMULSD	0x10(%R11,%RDX,8),%XMM5,%XMM10

  (615) 0x4673d3 MOV	(%RBX,%R14,8),%R15

  (615) 0x4673d7 VADDSD	(%RCX),%XMM10,%XMM11

  (615) 0x4673db VADDSD	%XMM10,%XMM8,%XMM13

  (615) 0x4673e0 VADDSD	%XMM10,%XMM9,%XMM14

  (615) 0x4673e5 VMOVSD	%XMM11,(%RCX)

  (615) 0x4673e9 VMOVSD	(%RAX),%XMM12

  (615) 0x4673ed LEA	(%R11,%R15,8),%RCX

  (615) 0x4673f1 VMULSD	0x18(%R11,%RDX,8),%XMM12,%XMM12

  (615) 0x4673f8 ADD	$0x4,%RDX

  (615) 0x4673fc VADDSD	(%RCX),%XMM12,%XMM15

  (615) 0x467400 VADDSD	%XMM12,%XMM13,%XMM1

  (615) 0x467405 VADDSD	%XMM12,%XMM14,%XMM0

  (615) 0x46740a VMOVSD	%XMM15,(%RCX)

  (615) 0x46740e CMP	%R8,%RDX

  (615) 0x467411 JNE	467366

0x467417 JMP	466fa5

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1811 - 1837

--------------------------------------------------------------------------------

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

Coverage (%)	Name	Source Location	Module
○97.71	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.29	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.64
CQA speedup if FP arith vectorized	2.20
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.26
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.10
Source	par_multi_interp.c:1811-1811,par_multi_interp.c:1814-1816,par_multi_interp.c:1819-1824,par_multi_interp.c:1827-1830,par_multi_interp.c:1835-1837
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	20.50
CQA cycles if no scalar integer	12.50
CQA cycles if FP arith vectorized	9.33
CQA cycles if fully vectorized	2.56
Front-end cycles	20.50
P0 cycles	11.80
P1 cycles	12.50
P2 cycles	16.33
P3 cycles	16.33
P4 cycles	3.00
P5 cycles	11.80
P6 cycles	11.90
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	11.80
P11 cycles	16.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	115.00
Nb uops	115.00
Nb loads	49.00
Nb stores	6.00
Nb stack references	8.00
FLOP/cycle	1.22
Nb FLOP add-sub	19.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.46
Bytes prefetched	0.00
Bytes loaded	392.00
Bytes stored	48.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.64
CQA speedup if FP arith vectorized	2.20
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.26
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.10
Source	par_multi_interp.c:1811-1811,par_multi_interp.c:1814-1816,par_multi_interp.c:1819-1824,par_multi_interp.c:1827-1830,par_multi_interp.c:1835-1837
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	20.50
CQA cycles if no scalar integer	12.50
CQA cycles if FP arith vectorized	9.33
CQA cycles if fully vectorized	2.56
Front-end cycles	20.50
P0 cycles	11.80
P1 cycles	12.50
P2 cycles	16.33
P3 cycles	16.33
P4 cycles	3.00
P5 cycles	11.80
P6 cycles	11.90
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	11.80
P11 cycles	16.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	115.00
Nb uops	115.00
Nb loads	49.00
Nb stores	6.00
Nb stack references	8.00
FLOP/cycle	1.22
Nb FLOP add-sub	19.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.46
Bytes prefetched	0.00
Bytes loaded	392.00
Bytes stored	48.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.10
Source file and lines	par_multi_interp.c:1811-1837
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1811-1837.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1811,1814-1816,1819-1824,1827-1830,1835-1837.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 68 paths individually, rerun with max-paths=68
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 68 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.50 to 12.50 cycles (1.64x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 20.50 to 2.56 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Recompile with march=sapphirerapids. CQA target is Granite_Rapids_ad (Intel(R) Xeon(R) Granite Rapids) but specialization flags are -march=graniterapids
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Type of elements and instruction set

25 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 25 FP arithmetical operations:

19: addition or subtraction
6: multiply

The binary loop is loading 392 bytes (49 double precision FP elements). The binary loop is storing 48 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	115
nb uops	115
loop length	487
used x86 registers	15
used mmx registers	0
used xmm registers	11
used ymm registers	0
used zmm registers	0
nb stack references	8
ADD-SUB / MUL ratio	3.17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.50 cycles
front end	20.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	11.80	11.70	16.33	16.33	3.00	11.80	11.90	3.00	3.00	3.00	11.80	16.33
cycles	11.80	12.50	16.33	16.33	3.00	11.80	11.90	3.00	3.00	3.00	11.80	16.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	20.50
Dispatch	16.33
Overall L1	20.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.50 cycles. At this rate:

9% of peak load performance is reached (19.12 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.34 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 20.50 to 16.33 cycles (1.26x speedup).

ASM code

In the binary file, the address of the loop is: 466fb3

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x88(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RCX,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RCX,(%RDX,%R8,1)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 466fde <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x96e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RSI,-0x38(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 466ff0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x980>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%RSI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x40(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RCX,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP (%R15,%RCX,8),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 467128 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xab8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x80(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $-0x3,(%R14,%RCX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 466fa5 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x935>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPQ $0x1,-0x50(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JNE 466f90 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x920>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDSD (%RAX),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RSI,-0x38(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JNE 466fb3 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x943>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xc0(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R15,%RCX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R15,%R8,1),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R15,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4672aa <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc3a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RDX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x3,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4671ee <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb7e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4671b7 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb47>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 467189 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb19>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RAX),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R13,%RDX,8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD (%R12,%RDX,8),%XMM5,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R9,%R14,8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R12,%R14,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VADDSD (%R14),%XMM6,%XMM7	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VADDSD %XMM6,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM6,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM7,(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R13,%RDX,8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD (%R12,%RDX,8),%XMM8,%XMM9	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R9,%R14,8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R12,%R14,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VADDSD (%R14),%XMM9,%XMM10	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VADDSD %XMM9,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM9,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM10,(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R13,%RDX,8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD (%R12,%RDX,8),%XMM11,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R9,%R14,8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R12,%R14,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VADDSD (%R14),%XMM12,%XMM13	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VADDSD %XMM12,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM12,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM13,(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %R15,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4672aa <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc3a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xb8(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R15,%RCX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R15,%R8,1),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R8,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 466fa5 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x935>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x3,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 467366 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xcf6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 467332 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xcc2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 467307 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc97>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RAX),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R10,%RDX,8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD (%R11,%RDX,8),%XMM6,%XMM7	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%RBX,%R14,8),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R11,%R15,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VADDSD (%RCX),%XMM7,%XMM5	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VADDSD %XMM7,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM7,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM5,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R10,%RDX,8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD (%R11,%RDX,8),%XMM8,%XMM9	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%RBX,%R14,8),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R11,%R15,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VADDSD (%RCX),%XMM9,%XMM10	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VADDSD %XMM9,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM9,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM10,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R10,%RDX,8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD (%R11,%RDX,8),%XMM11,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%RBX,%R14,8),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R11,%R15,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VADDSD (%RCX),%XMM12,%XMM13	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VADDSD %XMM12,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM12,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM13,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %R8,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JE 466fa5 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x935>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 466fa5 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x935>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	hypre_BoomerAMGBuildMultipass._omp_fn.10
Source file and lines	par_multi_interp.c:1811-1837
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 68 paths individually, rerun with max-paths=68
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 20.50 to 2.56 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Recompile with march=sapphirerapids. CQA target is Granite_Rapids_ad (Intel(R) Xeon(R) Granite Rapids) but specialization flags are -march=graniterapids
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Type of elements and instruction set

25 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 25 FP arithmetical operations:

19: addition or subtraction
6: multiply

The binary loop is loading 392 bytes (49 double precision FP elements). The binary loop is storing 48 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	115
nb uops	115
loop length	487
used x86 registers	15
used mmx registers	0
used xmm registers	11
used ymm registers	0
used zmm registers	0
nb stack references	8
ADD-SUB / MUL ratio	3.17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.50 cycles
front end	20.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	11.80	11.70	16.33	16.33	3.00	11.80	11.90	3.00	3.00	3.00	11.80	16.33
cycles	11.80	12.50	16.33	16.33	3.00	11.80	11.90	3.00	3.00	3.00	11.80	16.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	20.50
Dispatch	16.33
Overall L1	20.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.50 cycles. At this rate:

9% of peak load performance is reached (19.12 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.34 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 466fb3

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x88(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RCX,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RCX,(%RDX,%R8,1)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 466fde <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x96e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RSI,-0x38(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 466ff0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x980>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%RSI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x40(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RCX,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP (%R15,%RCX,8),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 467128 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xab8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x80(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $-0x3,(%R14,%RCX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 466fa5 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x935>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPQ $0x1,-0x50(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JNE 466f90 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x920>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDSD (%RAX),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RSI,-0x38(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JNE 466fb3 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x943>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xc0(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R15,%RCX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R15,%R8,1),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R15,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4672aa <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc3a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RDX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x3,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4671ee <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb7e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4671b7 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb47>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 467189 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb19>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RAX),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R13,%RDX,8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD (%R12,%RDX,8),%XMM5,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R9,%R14,8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R12,%R14,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VADDSD (%R14),%XMM6,%XMM7	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VADDSD %XMM6,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM6,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM7,(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R13,%RDX,8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD (%R12,%RDX,8),%XMM8,%XMM9	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R9,%R14,8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R12,%R14,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VADDSD (%R14),%XMM9,%XMM10	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VADDSD %XMM9,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM9,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM10,(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R13,%RDX,8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD (%R12,%RDX,8),%XMM11,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R9,%R14,8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R12,%R14,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VADDSD (%R14),%XMM12,%XMM13	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VADDSD %XMM12,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM12,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM13,(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %R15,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4672aa <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc3a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xb8(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R15,%RCX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R15,%R8,1),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R8,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 466fa5 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x935>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x3,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 467366 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xcf6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 467332 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xcc2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 467307 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc97>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RAX),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R10,%RDX,8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD (%R11,%RDX,8),%XMM6,%XMM7	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%RBX,%R14,8),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R11,%R15,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VADDSD (%RCX),%XMM7,%XMM5	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VADDSD %XMM7,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM7,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM5,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R10,%RDX,8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD (%R11,%RDX,8),%XMM8,%XMM9	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%RBX,%R14,8),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R11,%R15,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VADDSD (%RCX),%XMM9,%XMM10	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VADDSD %XMM9,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM9,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM10,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%R10,%RDX,8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULSD (%R11,%RDX,8),%XMM11,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%RBX,%R14,8),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R11,%R15,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VADDSD (%RCX),%XMM12,%XMM13	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VADDSD %XMM12,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM12,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM13,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %R8,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JE 466fa5 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x935>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 466fa5 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x935>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code