OV - exec - Loop 581

	Loop Id: 581	Module: exec	Source: par_multi_interp.c:939-999 [...]	Coverage: 0.07%

0x462420 MOV	-0xb0(%RBP),%R14

0x462427 MOV	-0x68(%RBP),%R8

0x46242b MOV	-0x80(%RBP),%R10

0x46242f MOV	(%R14,%R8,8),%RAX

0x462433 MOV	-0x78(%RBP),%R11

0x462437 MOV	%RDI,(%R10,%RAX,8)

0x46243b MOV	%RCX,(%R11,%RAX,8)

0x46243f MOV	-0xd0(%RBP),%R12

0x462446 LEA	0x8(,%RAX,8),%RSI

0x46244e MOV	(%R12,%RAX,8),%RDX

0x462452 ADD	%RSI,%R12

0x462455 MOV	-0x60(%RBP),%RBX

0x462459 MOV	-0x58(%RBP),%R14

0x46245d MOV	(%R12),%R8

0x462461 MOV	%R12,-0x90(%RBP)

0x462468 LEA	(%RBX,%RSI,1),%R11

0x46246c LEA	(%R14,%RSI,1),%R10

0x462470 CMP	%R8,%RDX

0x462473 JGE	462927

0x462479 MOV	%RSI,-0xc0(%RBP)

0x462480 MOV	%R10,-0x38(%RBP)

0x462484 MOV	-0x48(%RBP),%R14

0x462488 JMP	4624ac

  (584) 0x4624a0 INC	%RDX

  (584) 0x4624a3 CMP	%R8,%RDX

  (584) 0x4624a6 JGE	462920

  (584) 0x4624ac MOV	-0x40(%RBP),%RSI

  (584) 0x4624b0 MOV	(%RSI,%RDX,8),%RSI

  (584) 0x4624b4 LEA	(,%RSI,8),%R12

  (584) 0x4624bc CMP	%R9,(%R14,%RSI,8)

  (584) 0x4624c0 JNE	4624a0

  (584) 0x4624c2 MOV	-0x80(%RBP),%R8

  (584) 0x4624c6 MOV	-0x60(%RBP),%RBX

  (584) 0x4624ca MOV	(%R8,%RSI,8),%R8

  (584) 0x4624ce MOV	0x8(%RBX,%R12,1),%R10

  (584) 0x4624d3 ADD	%R8,%R10

  (584) 0x4624d6 MOV	%R10,-0x88(%RBP)

  (584) 0x4624dd CMP	%R10,%R8

  (584) 0x4624e0 JGE	4626d8

  (584) 0x4624e6 MOV	-0x70(%RBP),%RBX

  (584) 0x4624ea MOV	-0xe8(%RBP),%R10

  (584) 0x4624f1 MOV	-0x8(%R10,%RBX,1),%R10

  (584) 0x4624f6 MOV	-0x88(%RBP),%RBX

  (584) 0x4624fd LEA	(%R10,%R8,8),%R8

  (584) 0x462501 LEA	(%R10,%RBX,8),%R10

  (584) 0x462505 MOV	%R10,-0x88(%RBP)

  (584) 0x46250c SUB	%R8,%R10

  (584) 0x46250f SUB	$0x8,%R10

  (584) 0x462513 SHR	$0x3,%R10

  (584) 0x462517 INC	%R10

  (584) 0x46251a AND	$0x7,%R10D

  (584) 0x46251e JE	46260c

  (584) 0x462524 CMP	$0x1,%R10

  (584) 0x462528 JE	4625e6

  (584) 0x46252e CMP	$0x2,%R10

  (584) 0x462532 JE	4625cd

  (584) 0x462538 CMP	$0x3,%R10

  (584) 0x46253c JE	4625b4

  (584) 0x46253e CMP	$0x4,%R10

  (584) 0x462542 JE	46259b

  (584) 0x462544 CMP	$0x5,%R10

  (584) 0x462548 JE	462582

  (584) 0x46254a CMP	$0x6,%R10

  (584) 0x46254e JE	462569

  (584) 0x462550 MOV	(%R8),%RBX

  (584) 0x462553 LEA	(%R15,%RBX,8),%R10

  (584) 0x462557 CMP	(%R10),%RAX

  (584) 0x46255a JE	462565

  (584) 0x46255c INCQ	(%R11)

  (584) 0x46255f MOV	%RAX,(%R10)

  (584) 0x462562 INC	%RDI

  (584) 0x462565 ADD	$0x8,%R8

  (584) 0x462569 MOV	(%R8),%RBX

  (584) 0x46256c LEA	(%R15,%RBX,8),%R10

  (584) 0x462570 CMP	(%R10),%RAX

  (584) 0x462573 JE	46257e

  (584) 0x462575 INCQ	(%R11)

  (584) 0x462578 MOV	%RAX,(%R10)

  (584) 0x46257b INC	%RDI

  (584) 0x46257e ADD	$0x8,%R8

  (584) 0x462582 MOV	(%R8),%RBX

  (584) 0x462585 LEA	(%R15,%RBX,8),%R10

  (584) 0x462589 CMP	(%R10),%RAX

  (584) 0x46258c JE	462597

  (584) 0x46258e INCQ	(%R11)

  (584) 0x462591 MOV	%RAX,(%R10)

  (584) 0x462594 INC	%RDI

  (584) 0x462597 ADD	$0x8,%R8

  (584) 0x46259b MOV	(%R8),%RBX

  (584) 0x46259e LEA	(%R15,%RBX,8),%R10

  (584) 0x4625a2 CMP	(%R10),%RAX

  (584) 0x4625a5 JE	4625b0

  (584) 0x4625a7 INCQ	(%R11)

  (584) 0x4625aa MOV	%RAX,(%R10)

  (584) 0x4625ad INC	%RDI

  (584) 0x4625b0 ADD	$0x8,%R8

  (584) 0x4625b4 MOV	(%R8),%RBX

  (584) 0x4625b7 LEA	(%R15,%RBX,8),%R10

  (584) 0x4625bb CMP	(%R10),%RAX

  (584) 0x4625be JE	4625c9

  (584) 0x4625c0 INCQ	(%R11)

  (584) 0x4625c3 MOV	%RAX,(%R10)

  (584) 0x4625c6 INC	%RDI

  (584) 0x4625c9 ADD	$0x8,%R8

  (584) 0x4625cd MOV	(%R8),%RBX

  (584) 0x4625d0 LEA	(%R15,%RBX,8),%R10

  (584) 0x4625d4 CMP	(%R10),%RAX

  (584) 0x4625d7 JE	4625e2

  (584) 0x4625d9 INCQ	(%R11)

  (584) 0x4625dc MOV	%RAX,(%R10)

  (584) 0x4625df INC	%RDI

  (584) 0x4625e2 ADD	$0x8,%R8

  (584) 0x4625e6 MOV	(%R8),%RBX

  (584) 0x4625e9 LEA	(%R15,%RBX,8),%R10

  (584) 0x4625ed CMP	(%R10),%RAX

  (584) 0x4625f0 JE	4625fb

  (584) 0x4625f2 INCQ	(%R11)

  (584) 0x4625f5 MOV	%RAX,(%R10)

  (584) 0x4625f8 INC	%RDI

  (584) 0x4625fb ADD	$0x8,%R8

  (584) 0x4625ff CMP	%R8,-0x88(%RBP)

  (584) 0x462606 JE	4626d8

  (584) 0x46260c MOV	-0x38(%RBP),%R10

    (586) 0x462610 MOV	(%R8),%RBX

    (586) 0x462613 LEA	(%R15,%RBX,8),%RBX

    (586) 0x462617 CMP	(%RBX),%RAX

    (586) 0x46261a JE	462625

    (586) 0x46261c INCQ	(%R11)

    (586) 0x46261f MOV	%RAX,(%RBX)

    (586) 0x462622 INC	%RDI

    (586) 0x462625 LEA	0x8(%R8),%RBX

    (586) 0x462629 MOV	0x8(%R8),%R8

    (586) 0x46262d LEA	(%R15,%R8,8),%R8

    (586) 0x462631 CMP	(%R8),%RAX

    (586) 0x462634 JE	46263f

    (586) 0x462636 INCQ	(%R11)

    (586) 0x462639 MOV	%RAX,(%R8)

    (586) 0x46263c INC	%RDI

    (586) 0x46263f MOV	0x8(%RBX),%R8

    (586) 0x462643 LEA	(%R15,%R8,8),%R8

    (586) 0x462647 CMP	(%R8),%RAX

    (586) 0x46264a JE	462655

    (586) 0x46264c INCQ	(%R11)

    (586) 0x46264f MOV	%RAX,(%R8)

    (586) 0x462652 INC	%RDI

    (586) 0x462655 MOV	0x10(%RBX),%R8

    (586) 0x462659 LEA	(%R15,%R8,8),%R8

    (586) 0x46265d CMP	(%R8),%RAX

    (586) 0x462660 JE	46266b

    (586) 0x462662 INCQ	(%R11)

    (586) 0x462665 MOV	%RAX,(%R8)

    (586) 0x462668 INC	%RDI

    (586) 0x46266b MOV	0x18(%RBX),%R8

    (586) 0x46266f LEA	(%R15,%R8,8),%R8

    (586) 0x462673 CMP	(%R8),%RAX

    (586) 0x462676 JE	462681

    (586) 0x462678 INCQ	(%R11)

    (586) 0x46267b MOV	%RAX,(%R8)

    (586) 0x46267e INC	%RDI

    (586) 0x462681 MOV	0x20(%RBX),%R8

    (586) 0x462685 LEA	(%R15,%R8,8),%R8

    (586) 0x462689 CMP	(%R8),%RAX

    (586) 0x46268c JE	462697

    (586) 0x46268e INCQ	(%R11)

    (586) 0x462691 MOV	%RAX,(%R8)

    (586) 0x462694 INC	%RDI

    (586) 0x462697 MOV	0x28(%RBX),%R8

    (586) 0x46269b LEA	(%R15,%R8,8),%R8

    (586) 0x46269f CMP	(%R8),%RAX

    (586) 0x4626a2 JE	4626ad

    (586) 0x4626a4 INCQ	(%R11)

    (586) 0x4626a7 MOV	%RAX,(%R8)

    (586) 0x4626aa INC	%RDI

    (586) 0x4626ad MOV	0x30(%RBX),%R8

    (586) 0x4626b1 LEA	(%R15,%R8,8),%R8

    (586) 0x4626b5 CMP	(%R8),%RAX

    (586) 0x4626b8 JE	4626c3

    (586) 0x4626ba INCQ	(%R11)

    (586) 0x4626bd MOV	%RAX,(%R8)

    (586) 0x4626c0 INC	%RDI

    (586) 0x4626c3 LEA	0x38(%RBX),%R8

    (586) 0x4626c7 CMP	%R8,-0x88(%RBP)

    (586) 0x4626ce JNE	462610

  (584) 0x4626d4 MOV	%R10,-0x38(%RBP)

  (584) 0x4626d8 MOV	-0x78(%RBP),%R10

  (584) 0x4626dc MOV	-0x58(%RBP),%RBX

  (584) 0x4626e0 MOV	(%R10,%RSI,8),%RSI

  (584) 0x4626e4 MOV	0x8(%RBX,%R12,1),%R12

  (584) 0x4626e9 ADD	%RSI,%R12

  (584) 0x4626ec CMP	%R12,%RSI

  (584) 0x4626ef JGE	462903

  (584) 0x4626f5 MOV	-0xe0(%RBP),%R8

  (584) 0x4626fc MOV	-0x70(%RBP),%R10

  (584) 0x462700 MOV	-0x8(%R8,%R10,1),%RBX

  (584) 0x462705 LEA	(%RBX,%R12,8),%R12

  (584) 0x462709 LEA	(%RBX,%RSI,8),%RSI

  (584) 0x46270d MOV	%R12,%R8

  (584) 0x462710 SUB	%RSI,%R8

  (584) 0x462713 SUB	$0x8,%R8

  (584) 0x462717 SHR	$0x3,%R8

  (584) 0x46271b INC	%R8

  (584) 0x46271e AND	$0x7,%R8D

  (584) 0x462722 JE	462833

  (584) 0x462728 CMP	$0x1,%R8

  (584) 0x46272c JE	46280c

  (584) 0x462732 CMP	$0x2,%R8

  (584) 0x462736 JE	4627ee

  (584) 0x46273c CMP	$0x3,%R8

  (584) 0x462740 JE	4627d0

  (584) 0x462746 CMP	$0x4,%R8

  (584) 0x46274a JE	4627b2

  (584) 0x46274c CMP	$0x5,%R8

  (584) 0x462750 JE	462794

  (584) 0x462752 CMP	$0x6,%R8

  (584) 0x462756 JE	462776

  (584) 0x462758 MOV	(%RSI),%R10

  (584) 0x46275b LEA	(%R13,%R10,8),%RBX

  (584) 0x462760 CMP	(%RBX),%RAX

  (584) 0x462763 JE	462772

  (584) 0x462765 MOV	-0x38(%RBP),%R8

  (584) 0x462769 INC	%RCX

  (584) 0x46276c INCQ	(%R8)

  (584) 0x46276f MOV	%RAX,(%RBX)

  (584) 0x462772 ADD	$0x8,%RSI

  (584) 0x462776 MOV	(%RSI),%R10

  (584) 0x462779 LEA	(%R13,%R10,8),%RBX

  (584) 0x46277e CMP	(%RBX),%RAX

  (584) 0x462781 JE	462790

  (584) 0x462783 MOV	-0x38(%RBP),%R8

  (584) 0x462787 INC	%RCX

  (584) 0x46278a INCQ	(%R8)

  (584) 0x46278d MOV	%RAX,(%RBX)

  (584) 0x462790 ADD	$0x8,%RSI

  (584) 0x462794 MOV	(%RSI),%R10

  (584) 0x462797 LEA	(%R13,%R10,8),%RBX

  (584) 0x46279c CMP	(%RBX),%RAX

  (584) 0x46279f JE	4627ae

  (584) 0x4627a1 MOV	-0x38(%RBP),%R8

  (584) 0x4627a5 INC	%RCX

  (584) 0x4627a8 INCQ	(%R8)

  (584) 0x4627ab MOV	%RAX,(%RBX)

  (584) 0x4627ae ADD	$0x8,%RSI

  (584) 0x4627b2 MOV	(%RSI),%R10

  (584) 0x4627b5 LEA	(%R13,%R10,8),%RBX

  (584) 0x4627ba CMP	(%RBX),%RAX

  (584) 0x4627bd JE	4627cc

  (584) 0x4627bf MOV	-0x38(%RBP),%R8

  (584) 0x4627c3 INC	%RCX

  (584) 0x4627c6 INCQ	(%R8)

  (584) 0x4627c9 MOV	%RAX,(%RBX)

  (584) 0x4627cc ADD	$0x8,%RSI

  (584) 0x4627d0 MOV	(%RSI),%R10

  (584) 0x4627d3 LEA	(%R13,%R10,8),%RBX

  (584) 0x4627d8 CMP	(%RBX),%RAX

  (584) 0x4627db JE	4627ea

  (584) 0x4627dd MOV	-0x38(%RBP),%R8

  (584) 0x4627e1 INC	%RCX

  (584) 0x4627e4 INCQ	(%R8)

  (584) 0x4627e7 MOV	%RAX,(%RBX)

  (584) 0x4627ea ADD	$0x8,%RSI

  (584) 0x4627ee MOV	(%RSI),%R10

  (584) 0x4627f1 LEA	(%R13,%R10,8),%RBX

  (584) 0x4627f6 CMP	(%RBX),%RAX

  (584) 0x4627f9 JE	462808

  (584) 0x4627fb MOV	-0x38(%RBP),%R8

  (584) 0x4627ff INC	%RCX

  (584) 0x462802 INCQ	(%R8)

  (584) 0x462805 MOV	%RAX,(%RBX)

  (584) 0x462808 ADD	$0x8,%RSI

  (584) 0x46280c MOV	(%RSI),%R10

  (584) 0x46280f LEA	(%R13,%R10,8),%RBX

  (584) 0x462814 CMP	(%RBX),%RAX

  (584) 0x462817 JE	462826

  (584) 0x462819 MOV	-0x38(%RBP),%R8

  (584) 0x46281d INC	%RCX

  (584) 0x462820 INCQ	(%R8)

  (584) 0x462823 MOV	%RAX,(%RBX)

  (584) 0x462826 ADD	$0x8,%RSI

  (584) 0x46282a CMP	%RSI,%R12

  (584) 0x46282d JE	462903

  (584) 0x462833 MOV	-0x38(%RBP),%R10

    (585) 0x462837 MOV	(%RSI),%RBX

    (585) 0x46283a LEA	(%R13,%RBX,8),%R8

    (585) 0x46283f CMP	(%R8),%RAX

    (585) 0x462842 JE	46284d

    (585) 0x462844 INCQ	(%R10)

    (585) 0x462847 MOV	%RAX,(%R8)

    (585) 0x46284a INC	%RCX

    (585) 0x46284d LEA	0x8(%RSI),%RBX

    (585) 0x462851 MOV	0x8(%RSI),%RSI

    (585) 0x462855 LEA	(%R13,%RSI,8),%R8

    (585) 0x46285a CMP	(%R8),%RAX

    (585) 0x46285d JE	462868

    (585) 0x46285f INCQ	(%R10)

    (585) 0x462862 MOV	%RAX,(%R8)

    (585) 0x462865 INC	%RCX

    (585) 0x462868 MOV	0x8(%RBX),%RSI

    (585) 0x46286c LEA	(%R13,%RSI,8),%R8

    (585) 0x462871 CMP	(%R8),%RAX

    (585) 0x462874 JE	46287f

    (585) 0x462876 INCQ	(%R10)

    (585) 0x462879 MOV	%RAX,(%R8)

    (585) 0x46287c INC	%RCX

    (585) 0x46287f MOV	0x10(%RBX),%RSI

    (585) 0x462883 LEA	(%R13,%RSI,8),%R8

    (585) 0x462888 CMP	(%R8),%RAX

    (585) 0x46288b JE	462896

    (585) 0x46288d INCQ	(%R10)

    (585) 0x462890 MOV	%RAX,(%R8)

    (585) 0x462893 INC	%RCX

    (585) 0x462896 MOV	0x18(%RBX),%RSI

    (585) 0x46289a LEA	(%R13,%RSI,8),%R8

    (585) 0x46289f CMP	(%R8),%RAX

    (585) 0x4628a2 JE	4628ad

    (585) 0x4628a4 INCQ	(%R10)

    (585) 0x4628a7 MOV	%RAX,(%R8)

    (585) 0x4628aa INC	%RCX

    (585) 0x4628ad MOV	0x20(%RBX),%RSI

    (585) 0x4628b1 LEA	(%R13,%RSI,8),%R8

    (585) 0x4628b6 CMP	(%R8),%RAX

    (585) 0x4628b9 JE	4628c4

    (585) 0x4628bb INCQ	(%R10)

    (585) 0x4628be MOV	%RAX,(%R8)

    (585) 0x4628c1 INC	%RCX

    (585) 0x4628c4 MOV	0x28(%RBX),%RSI

    (585) 0x4628c8 LEA	(%R13,%RSI,8),%R8

    (585) 0x4628cd CMP	(%R8),%RAX

    (585) 0x4628d0 JE	4628db

    (585) 0x4628d2 INCQ	(%R10)

    (585) 0x4628d5 MOV	%RAX,(%R8)

    (585) 0x4628d8 INC	%RCX

    (585) 0x4628db MOV	0x30(%RBX),%RSI

    (585) 0x4628df LEA	(%R13,%RSI,8),%R8

    (585) 0x4628e4 CMP	(%R8),%RAX

    (585) 0x4628e7 JE	4628f2

    (585) 0x4628e9 INCQ	(%R10)

    (585) 0x4628ec MOV	%RAX,(%R8)

    (585) 0x4628ef INC	%RCX

    (585) 0x4628f2 LEA	0x38(%RBX),%RSI

    (585) 0x4628f6 CMP	%RSI,%R12

    (585) 0x4628f9 JNE	462837

  (584) 0x4628ff MOV	%R10,-0x38(%RBP)

  (584) 0x462903 MOV	-0x90(%RBP),%R12

  (584) 0x46290a INC	%RDX

  (584) 0x46290d MOV	(%R12),%R8

  (584) 0x462911 CMP	%R8,%RDX

  (584) 0x462914 JL	4624ac

0x46291a NOPW	(%RAX,%RAX,1)

0x462920 MOV	-0xc0(%RBP),%RSI

0x462927 MOV	-0xc8(%RBP),%RBX

0x46292e MOV	-0x60(%RBP),%R11

0x462932 MOV	(%RBX,%RAX,8),%RDX

0x462936 ADD	%RSI,%RBX

0x462939 MOV	-0x58(%RBP),%R14

0x46293d MOV	(%RBX),%R8

0x462940 LEA	(%R11,%RSI,1),%R12

0x462944 LEA	(%R14,%RSI,1),%R10

0x462948 CMP	%R8,%RDX

0x46294b JGE	462be0

0x462951 MOV	%RBX,-0x90(%RBP)

0x462958 MOV	%R12,-0x88(%RBP)

0x46295f MOV	%R10,-0x38(%RBP)

0x462963 MOV	-0x50(%RBP),%R14

0x462967 MOV	-0xd8(%RBP),%RBX

0x46296e JMP	46298c

  (582) 0x462980 INC	%RDX

  (582) 0x462983 CMP	%R8,%RDX

  (582) 0x462986 JGE	462be0

  (582) 0x46298c MOV	(%R14,%RDX,8),%RSI

  (582) 0x462990 LEA	(,%RSI,8),%R12

  (582) 0x462998 CMP	%R9,(%RBX,%RSI,8)

  (582) 0x46299c JNE	462980

  (582) 0x46299e MOV	-0xa0(%RBP),%R11

  (582) 0x4629a5 MOV	-0x98(%RBP),%R10

  (582) 0x4629ac MOV	(%R11,%RSI,8),%RSI

  (582) 0x4629b0 MOV	0x8(%R10,%R12,1),%R12

  (582) 0x4629b5 ADD	%RSI,%R12

  (582) 0x4629b8 CMP	%R12,%RSI

  (582) 0x4629bb JGE	462980

  (582) 0x4629bd MOV	-0xa8(%RBP),%R8

  (582) 0x4629c4 MOV	-0x70(%RBP),%R11

  (582) 0x4629c8 MOV	(%R8,%R11,1),%R10

  (582) 0x4629cc LEA	(%R10,%R12,8),%R12

  (582) 0x4629d0 LEA	(%R10,%RSI,8),%RSI

  (582) 0x4629d4 MOV	%R12,%R8

  (582) 0x4629d7 SUB	%RSI,%R8

  (582) 0x4629da SUB	$0x8,%R8

  (582) 0x4629de SHR	$0x3,%R8

  (582) 0x4629e2 INC	%R8

  (582) 0x4629e5 AND	$0x3,%R8D

  (582) 0x4629e9 JE	462a79

  (582) 0x4629ef CMP	$0x1,%R8

  (582) 0x4629f3 JE	462a49

  (582) 0x4629f5 CMP	$0x2,%R8

  (582) 0x4629f9 JE	462a22

  (582) 0x4629fb MOV	(%RSI),%R11

  (582) 0x4629fe TEST	%R11,%R11

  (582) 0x462a01 JS	462da0

  (582) 0x462a07 LEA	(%R13,%R11,8),%R8

  (582) 0x462a0c CMP	(%R8),%RAX

  (582) 0x462a0f JE	462a1e

  (582) 0x462a11 MOV	-0x38(%RBP),%R10

  (582) 0x462a15 INC	%RCX

  (582) 0x462a18 INCQ	(%R10)

  (582) 0x462a1b MOV	%RAX,(%R8)

  (582) 0x462a1e ADD	$0x8,%RSI

  (582) 0x462a22 MOV	(%RSI),%R10

  (582) 0x462a25 TEST	%R10,%R10

  (582) 0x462a28 JS	462d78

  (582) 0x462a2e LEA	(%R13,%R10,8),%R11

  (582) 0x462a33 CMP	(%R11),%RAX

  (582) 0x462a36 JE	462a45

  (582) 0x462a38 MOV	-0x38(%RBP),%R8

  (582) 0x462a3c INC	%RCX

  (582) 0x462a3f INCQ	(%R8)

  (582) 0x462a42 MOV	%RAX,(%R11)

  (582) 0x462a45 ADD	$0x8,%RSI

  (582) 0x462a49 MOV	(%RSI),%R8

  (582) 0x462a4c TEST	%R8,%R8

  (582) 0x462a4f JS	462d50

  (582) 0x462a55 LEA	(%R13,%R8,8),%R11

  (582) 0x462a5a CMP	(%R11),%RAX

  (582) 0x462a5d JE	462a6c

  (582) 0x462a5f MOV	-0x38(%RBP),%R10

  (582) 0x462a63 INC	%RCX

  (582) 0x462a66 INCQ	(%R10)

  (582) 0x462a69 MOV	%RAX,(%R11)

  (582) 0x462a6c ADD	$0x8,%RSI

  (582) 0x462a70 CMP	%RSI,%R12

  (582) 0x462a73 JE	462bc7

  (582) 0x462a79 MOV	-0x88(%RBP),%R11

  (582) 0x462a80 MOV	-0x38(%RBP),%R10

  (582) 0x462a84 JMP	462b14

    (583) 0x462a90 LEA	(%R13,%R8,8),%R8

    (583) 0x462a95 CMP	(%R8),%RAX

    (583) 0x462a98 JE	462aa3

    (583) 0x462a9a INCQ	(%R10)

    (583) 0x462a9d MOV	%RAX,(%R8)

    (583) 0x462aa0 INC	%RCX

    (583) 0x462aa3 LEA	0x8(%RSI),%R8

    (583) 0x462aa7 MOV	0x8(%RSI),%RSI

    (583) 0x462aab TEST	%RSI,%RSI

    (583) 0x462aae JS	462b4a

    (583) 0x462ab4 LEA	(%R13,%RSI,8),%RSI

    (583) 0x462ab9 CMP	(%RSI),%RAX

    (583) 0x462abc JE	462ac7

    (583) 0x462abe INCQ	(%R10)

    (583) 0x462ac1 MOV	%RAX,(%RSI)

    (583) 0x462ac4 INC	%RCX

    (583) 0x462ac7 MOV	0x8(%R8),%RSI

    (583) 0x462acb TEST	%RSI,%RSI

    (583) 0x462ace JS	462b70

    (583) 0x462ad4 LEA	(%R13,%RSI,8),%RSI

    (583) 0x462ad9 CMP	(%RSI),%RAX

    (583) 0x462adc JE	462ae7

    (583) 0x462ade INCQ	(%R10)

    (583) 0x462ae1 MOV	%RAX,(%RSI)

    (583) 0x462ae4 INC	%RCX

    (583) 0x462ae7 MOV	0x10(%R8),%RSI

    (583) 0x462aeb TEST	%RSI,%RSI

    (583) 0x462aee JS	462b96

    (583) 0x462af4 LEA	(%R13,%RSI,8),%RSI

    (583) 0x462af9 CMP	(%RSI),%RAX

    (583) 0x462afc JE	462b07

    (583) 0x462afe INCQ	(%R10)

    (583) 0x462b01 MOV	%RAX,(%RSI)

    (583) 0x462b04 INC	%RCX

    (583) 0x462b07 LEA	0x18(%R8),%RSI

    (583) 0x462b0b CMP	%RSI,%R12

    (583) 0x462b0e JE	462bbc

    (583) 0x462b14 MOV	(%RSI),%R8

    (583) 0x462b17 TEST	%R8,%R8

    (583) 0x462b1a JNS	462a90

    (583) 0x462b20 NOT	%R8

    (583) 0x462b23 LEA	(%R15,%R8,8),%R8

    (583) 0x462b27 CMP	(%R8),%RAX

    (583) 0x462b2a JE	462aa3

    (583) 0x462b30 INCQ	(%R11)

    (583) 0x462b33 MOV	%RAX,(%R8)

    (583) 0x462b36 LEA	0x8(%RSI),%R8

    (583) 0x462b3a INC	%RDI

    (583) 0x462b3d MOV	0x8(%RSI),%RSI

    (583) 0x462b41 TEST	%RSI,%RSI

    (583) 0x462b44 JNS	462ab4

    (583) 0x462b4a NOT	%RSI

    (583) 0x462b4d LEA	(%R15,%RSI,8),%RSI

    (583) 0x462b51 CMP	(%RSI),%RAX

    (583) 0x462b54 JE	462ac7

    (583) 0x462b5a INCQ	(%R11)

    (583) 0x462b5d MOV	%RAX,(%RSI)

    (583) 0x462b60 INC	%RDI

    (583) 0x462b63 MOV	0x8(%R8),%RSI

    (583) 0x462b67 TEST	%RSI,%RSI

    (583) 0x462b6a JNS	462ad4

    (583) 0x462b70 NOT	%RSI

    (583) 0x462b73 LEA	(%R15,%RSI,8),%RSI

    (583) 0x462b77 CMP	(%RSI),%RAX

    (583) 0x462b7a JE	462ae7

    (583) 0x462b80 INCQ	(%R11)

    (583) 0x462b83 MOV	%RAX,(%RSI)

    (583) 0x462b86 INC	%RDI

    (583) 0x462b89 MOV	0x10(%R8),%RSI

    (583) 0x462b8d TEST	%RSI,%RSI

    (583) 0x462b90 JNS	462af4

    (583) 0x462b96 NOT	%RSI

    (583) 0x462b99 LEA	(%R15,%RSI,8),%RSI

    (583) 0x462b9d CMP	(%RSI),%RAX

    (583) 0x462ba0 JE	462b07

    (583) 0x462ba6 INCQ	(%R11)

    (583) 0x462ba9 MOV	%RAX,(%RSI)

    (583) 0x462bac LEA	0x18(%R8),%RSI

    (583) 0x462bb0 INC	%RDI

    (583) 0x462bb3 CMP	%RSI,%R12

    (583) 0x462bb6 JNE	462b14

  (582) 0x462bbc MOV	%R11,-0x88(%RBP)

  (582) 0x462bc3 MOV	%R10,-0x38(%RBP)

  (582) 0x462bc7 MOV	-0x90(%RBP),%R12

  (582) 0x462bce INC	%RDX

  (582) 0x462bd1 MOV	(%R12),%R8

  (582) 0x462bd5 CMP	%R8,%RDX

  (582) 0x462bd8 JL	46298c

0x462bde XCHG	%AX,%AX

0x462be0 INCQ	-0x68(%RBP)

0x462be4 MOV	-0x68(%RBP),%R11

0x462be8 CMP	%R11,-0xb8(%RBP)

0x462bef JG	462420

  (582) 0x462d50 NOT	%R8

  (582) 0x462d53 LEA	(%R15,%R8,8),%R8

  (582) 0x462d57 CMP	(%R8),%RAX

  (582) 0x462d5a JE	462a6c

  (582) 0x462d60 MOV	-0x88(%RBP),%R11

  (582) 0x462d67 INC	%RDI

  (582) 0x462d6a INCQ	(%R11)

  (582) 0x462d6d MOV	%RAX,(%R8)

  (582) 0x462d70 JMP	462a6c

  (582) 0x462d78 NOT	%R10

  (582) 0x462d7b LEA	(%R15,%R10,8),%R11

  (582) 0x462d7f CMP	(%R11),%RAX

  (582) 0x462d82 JE	462a45

  (582) 0x462d88 MOV	-0x88(%RBP),%R10

  (582) 0x462d8f INC	%RDI

  (582) 0x462d92 INCQ	(%R10)

  (582) 0x462d95 MOV	%RAX,(%R11)

  (582) 0x462d98 JMP	462a45

  (582) 0x462da0 NOT	%R11

  (582) 0x462da3 LEA	(%R15,%R11,8),%R11

  (582) 0x462da7 CMP	(%R11),%RAX

  (582) 0x462daa JE	462a1e

  (582) 0x462db0 MOV	-0x88(%RBP),%R8

  (582) 0x462db7 INC	%RDI

  (582) 0x462dba INCQ	(%R8)

  (582) 0x462dbd MOV	%RAX,(%R11)

  (582) 0x462dc0 JMP	462a1e

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 939 - 999

--------------------------------------------------------------------------------

939:           for (i=thread_start; i < thread_stop; i++)

940:           {

941:              i1 = pass_array[i];

942:              P_diag_start[i1] = cnt_nz;

943:              P_offd_start[i1] = cnt_nz_offd;

944:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

945:              {

946:                 j1 = S_diag_j[j];

947:                 if (assigned[j1] == pass-1)

948:                 {

949:                    j_start = P_diag_start[j1];

950:                    j_end = j_start+P_diag_i[j1+1];

951:                    for (k=j_start; k < j_end; k++)

952:                    {

953:                       k1 = P_diag_pass[pass-1][k];

954:                       if (P_marker[k1] != i1)

955:                       {

956:                          cnt_nz++;

957:                          P_diag_i[i1+1]++;

958:                          P_marker[k1] = i1;

959:                       }

960:                    }

961:                    j_start = P_offd_start[j1];

962:                    j_end = j_start+P_offd_i[j1+1];

963:                    for (k=j_start; k < j_end; k++)

964:                    {

965:                       k1 = P_offd_pass[pass-1][k];

966:                       if (P_marker_offd[k1] != i1)

967:                       {

968:                          cnt_nz_offd++;

969:                          P_offd_i[i1+1]++;

970:                          P_marker_offd[k1] = i1;

[...]

976:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

977:              {

978:                 j1 = S_offd_j[j];

979:                 if (assigned_offd[j1] == pass-1)

980:                 {

981:                    j_start = Pext_start[j1];

982:                    j_end = j_start+Pext_i[j1+1];

983:                    for (k=j_start; k < j_end; k++)

984:                    {

985:                       k1 = Pext_pass[pass][k];

986:                       if (k1 < 0)

987:                       {

988:                          if (P_marker[-k1-1] != i1)

989:                          {

990:                             cnt_nz++;

991:                             P_diag_i[i1+1]++;

992:                             P_marker[-k1-1] = i1;

993:                          }

994:                       }

995:                       else if (P_marker_offd[k1] != i1)

996:                       {

997:                          cnt_nz_offd++;

998:                          P_offd_i[i1+1]++;

999:                          P_marker_offd[k1] = i1;

Coverage (%)	Name	Source Location	Module
○98.15	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.85	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:939-944,par_multi_interp.c:957-957,par_multi_interp.c:969-969,par_multi_interp.c:976-976,par_multi_interp.c:991-991,par_multi_interp.c:998-998
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.83
CQA cycles if no scalar integer	7.83
CQA cycles if FP arith vectorized	7.83
CQA cycles if fully vectorized	0.98
Front-end cycles	7.83
P0 cycles	1.70
P1 cycles	1.60
P2 cycles	7.33
P3 cycles	7.33
P4 cycles	4.50
P5 cycles	1.60
P6 cycles	1.50
P7 cycles	4.50
P8 cycles	4.50
P9 cycles	4.50
P10 cycles	1.60
P11 cycles	7.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	46.00
Nb uops	47.00
Nb loads	22.00
Nb stores	9.00
Nb stack references	16.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	31.66
Bytes prefetched	0.00
Bytes loaded	176.00
Bytes stored	72.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:939-944,par_multi_interp.c:957-957,par_multi_interp.c:969-969,par_multi_interp.c:976-976,par_multi_interp.c:991-991,par_multi_interp.c:998-998
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.83
CQA cycles if no scalar integer	7.83
CQA cycles if FP arith vectorized	7.83
CQA cycles if fully vectorized	0.98
Front-end cycles	7.83
P0 cycles	1.70
P1 cycles	1.60
P2 cycles	7.33
P3 cycles	7.33
P4 cycles	4.50
P5 cycles	1.60
P6 cycles	1.50
P7 cycles	4.50
P8 cycles	4.50
P9 cycles	4.50
P10 cycles	1.60
P11 cycles	7.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	46.00
Nb uops	47.00
Nb loads	22.00
Nb stores	9.00
Nb stack references	16.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	31.66
Bytes prefetched	0.00
Bytes loaded	176.00
Bytes stored	72.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:939-999
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-970,976-999.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-944,957,969,976,991,998.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 7.83 to 0.98 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

INC: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 176 bytes. The binary loop is storing 72 bytes.

General properties

nb instructions	46
nb uops	47
loop length	215
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	16

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.83 cycles
front end	7.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.70	1.60	7.33	7.33	4.50	1.60	1.50	4.50	4.50	4.50	1.60	7.33
cycles	1.70	1.60	7.33	7.33	4.50	1.60	1.50	4.50	4.50	4.50	1.60	7.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.83
Dispatch	7.33
Overall L1	7.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.83 cycles. At this rate:

11% of peak load performance is reached (22.47 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.19 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 7.83 to 7.33 cycles (1.07x speedup).

ASM code

In the binary file, the address of the loop is: 462420

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0xb0(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x80(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14,%R8,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x78(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,(%R10,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,(%R11,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xd0(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x8(,%RAX,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R12,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RSI,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x60(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x58(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R12),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R12,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RBX,%RSI,1),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R14,%RSI,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R8,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 462927 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x757>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x48(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 4624ac <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x2dc>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0xc0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xc8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x60(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RSI,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x58(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R11,%RSI,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R14,%RSI,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R8,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 462be0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xa10>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x50(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xd8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 46298c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x7bc>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INCQ -0x68(%RBP)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV -0x68(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R11,-0xb8(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JG 462420 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x250>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:939-999
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 7.83 to 0.98 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

INC: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 176 bytes. The binary loop is storing 72 bytes.

General properties

nb instructions	46
nb uops	47
loop length	215
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	16

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.83 cycles
front end	7.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.70	1.60	7.33	7.33	4.50	1.60	1.50	4.50	4.50	4.50	1.60	7.33
cycles	1.70	1.60	7.33	7.33	4.50	1.60	1.50	4.50	4.50	4.50	1.60	7.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.83
Dispatch	7.33
Overall L1	7.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.83 cycles. At this rate:

11% of peak load performance is reached (22.47 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.19 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 462420

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0xb0(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x80(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14,%R8,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x78(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,(%R10,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,(%R11,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xd0(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x8(,%RAX,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R12,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RSI,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x60(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x58(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R12),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R12,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RBX,%RSI,1),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R14,%RSI,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R8,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 462927 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x757>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x48(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 4624ac <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x2dc>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0xc0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xc8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x60(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX,%RAX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RSI,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x58(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R11,%RSI,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R14,%RSI,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R8,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 462be0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xa10>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x50(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xd8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 46298c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x7bc>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INCQ -0x68(%RBP)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV -0x68(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R11,-0xb8(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JG 462420 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x250>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code