OV - exec - Loop 573

	Loop Id: 573	Module: exec	Source: par_multi_interp.c:1072-1125	Coverage: 0.05%

0x462fc0 MOV	-0xb0(%RBP),%R13

0x462fc7 MOV	-0x70(%RBP),%RDI

0x462fcb MOV	-0xd0(%RBP),%R8

0x462fd2 MOV	(%R13,%RDI,8),%RDI

0x462fd7 LEA	0x8(,%RDI,8),%R11

0x462fdf MOV	(%R8,%RDI,8),%RCX

0x462fe3 ADD	%R11,%R8

0x462fe6 MOV	%R8,-0x90(%RBP)

0x462fed MOV	(%R8),%R8

0x462ff0 MOV	%RDI,%RAX

0x462ff3 MOV	%RCX,-0x38(%RBP)

0x462ff7 NOT	%RAX

0x462ffa CMP	%R8,%RCX

0x462ffd JGE	463340

0x463003 MOV	%RDI,-0xc0(%RBP)

0x46300a MOV	%R11,-0xe0(%RBP)

0x463011 MOV	-0x88(%RBP),%RDI

0x463018 MOV	%RBX,%R13

0x46301b JMP	463051

  (576) 0x463040 INCQ	-0x38(%RBP)

  (576) 0x463044 MOV	-0x38(%RBP),%RDX

  (576) 0x463048 CMP	%R8,%RDX

  (576) 0x46304b JGE	463328

  (576) 0x463051 MOV	-0x38(%RBP),%R11

  (576) 0x463055 MOV	-0x40(%RBP),%RDX

  (576) 0x463059 MOV	-0x48(%RBP),%RBX

  (576) 0x46305d MOV	(%RDX,%R11,8),%RCX

  (576) 0x463061 LEA	(,%RCX,8),%R11

  (576) 0x463069 CMP	%R13,(%RBX,%RCX,8)

  (576) 0x46306d JNE	463040

  (576) 0x46306f MOV	-0x80(%RBP),%R8

  (576) 0x463073 MOV	-0x60(%RBP),%RDX

  (576) 0x463077 MOV	(%R8,%RCX,8),%R8

  (576) 0x46307b MOV	0x8(%RDX,%R11,1),%RBX

  (576) 0x463080 ADD	%R8,%RBX

  (576) 0x463083 CMP	%RBX,%R8

  (576) 0x463086 JGE	4631e4

  (576) 0x46308c MOV	-0x8(%R10,%R14,1),%RDX

  (576) 0x463091 LEA	(%RDX,%RBX,8),%RBX

  (576) 0x463095 LEA	(%RDX,%R8,8),%R8

  (576) 0x463099 MOV	%RBX,-0x68(%RBP)

  (576) 0x46309d SUB	%R8,%RBX

  (576) 0x4630a0 SUB	$0x8,%RBX

  (576) 0x4630a4 SHR	$0x3,%RBX

  (576) 0x4630a8 INC	%RBX

  (576) 0x4630ab AND	$0x3,%EBX

  (576) 0x4630ae JE	463157

  (576) 0x4630b4 CMP	$0x1,%RBX

  (576) 0x4630b8 JE	46311e

  (576) 0x4630ba CMP	$0x2,%RBX

  (576) 0x4630be JE	4630ef

  (576) 0x4630c0 MOV	(%R8),%RDX

  (576) 0x4630c3 MOV	%RDX,%RBX

  (576) 0x4630c6 LEA	(%R12,%RDX,8),%RDX

  (576) 0x4630ca MOV	%RDX,-0x88(%RBP)

  (576) 0x4630d1 CMP	%RAX,(%RDX)

  (576) 0x4630d4 JE	4630eb

  (576) 0x4630d6 MOV	(%R10,%R14,1),%RDX

  (576) 0x4630da MOV	%RBX,(%RDX,%RSI,8)

  (576) 0x4630de MOV	-0x88(%RBP),%RBX

  (576) 0x4630e5 INC	%RSI

  (576) 0x4630e8 MOV	%RAX,(%RBX)

  (576) 0x4630eb ADD	$0x8,%R8

  (576) 0x4630ef MOV	(%R8),%RDX

  (576) 0x4630f2 MOV	%RDX,%RBX

  (576) 0x4630f5 LEA	(%R12,%RDX,8),%RDX

  (576) 0x4630f9 MOV	%RDX,-0x88(%RBP)

  (576) 0x463100 CMP	%RAX,(%RDX)

  (576) 0x463103 JE	46311a

  (576) 0x463105 MOV	(%R10,%R14,1),%RDX

  (576) 0x463109 MOV	%RBX,(%RDX,%RSI,8)

  (576) 0x46310d MOV	-0x88(%RBP),%RBX

  (576) 0x463114 INC	%RSI

  (576) 0x463117 MOV	%RAX,(%RBX)

  (576) 0x46311a ADD	$0x8,%R8

  (576) 0x46311e MOV	(%R8),%RDX

  (576) 0x463121 MOV	%RDX,%RBX

  (576) 0x463124 LEA	(%R12,%RDX,8),%RDX

  (576) 0x463128 MOV	%RDX,-0x88(%RBP)

  (576) 0x46312f CMP	%RAX,(%RDX)

  (576) 0x463132 JE	463149

  (576) 0x463134 MOV	(%R10,%R14,1),%RDX

  (576) 0x463138 MOV	%RBX,(%RDX,%RSI,8)

  (576) 0x46313c MOV	-0x88(%RBP),%RBX

  (576) 0x463143 INC	%RSI

  (576) 0x463146 MOV	%RAX,(%RBX)

  (576) 0x463149 ADD	$0x8,%R8

  (576) 0x46314d CMP	%R8,-0x68(%RBP)

  (576) 0x463151 JE	4631e4

  (576) 0x463157 MOV	%RCX,-0x88(%RBP)

  (576) 0x46315e MOV	%RDI,%RBX

    (578) 0x463161 MOV	(%R8),%RDI

    (578) 0x463164 LEA	(%R12,%RDI,8),%RDX

    (578) 0x463168 CMP	%RAX,(%RDX)

    (578) 0x46316b JE	46317b

    (578) 0x46316d MOV	(%R10,%R14,1),%RCX

    (578) 0x463171 MOV	%RDI,(%RCX,%RSI,8)

    (578) 0x463175 MOV	%RAX,(%RDX)

    (578) 0x463178 INC	%RSI

    (578) 0x46317b LEA	0x8(%R8),%RDX

    (578) 0x46317f MOV	0x8(%R8),%R8

    (578) 0x463183 LEA	(%R12,%R8,8),%RDI

    (578) 0x463187 CMP	%RAX,(%RDI)

    (578) 0x46318a JE	46319a

    (578) 0x46318c MOV	(%R10,%R14,1),%RCX

    (578) 0x463190 MOV	%R8,(%RCX,%RSI,8)

    (578) 0x463194 MOV	%RAX,(%RDI)

    (578) 0x463197 INC	%RSI

    (578) 0x46319a MOV	0x8(%RDX),%R8

    (578) 0x46319e LEA	(%R12,%R8,8),%RDI

    (578) 0x4631a2 CMP	%RAX,(%RDI)

    (578) 0x4631a5 JE	4631b5

    (578) 0x4631a7 MOV	(%R10,%R14,1),%RCX

    (578) 0x4631ab MOV	%R8,(%RCX,%RSI,8)

    (578) 0x4631af MOV	%RAX,(%RDI)

    (578) 0x4631b2 INC	%RSI

    (578) 0x4631b5 MOV	0x10(%RDX),%R8

    (578) 0x4631b9 LEA	(%R12,%R8,8),%RDI

    (578) 0x4631bd CMP	%RAX,(%RDI)

    (578) 0x4631c0 JE	4631d0

    (578) 0x4631c2 MOV	(%R10,%R14,1),%RCX

    (578) 0x4631c6 MOV	%R8,(%RCX,%RSI,8)

    (578) 0x4631ca MOV	%RAX,(%RDI)

    (578) 0x4631cd INC	%RSI

    (578) 0x4631d0 LEA	0x18(%RDX),%R8

    (578) 0x4631d4 CMP	%R8,-0x68(%RBP)

    (578) 0x4631d8 JNE	463161

  (576) 0x4631da MOV	-0x88(%RBP),%RCX

  (576) 0x4631e1 MOV	%RBX,%RDI

  (576) 0x4631e4 MOV	-0x78(%RBP),%RBX

  (576) 0x4631e8 MOV	-0x58(%RBP),%RDX

  (576) 0x4631ec MOV	(%RBX,%RCX,8),%RCX

  (576) 0x4631f0 MOV	0x8(%RDX,%R11,1),%R8

  (576) 0x4631f5 ADD	%RCX,%R8

  (576) 0x4631f8 CMP	%R8,%RCX

  (576) 0x4631fb JGE	463710

  (576) 0x463201 MOV	-0x8(%R9,%R14,1),%RBX

  (576) 0x463206 LEA	(%RBX,%RCX,8),%RCX

  (576) 0x46320a LEA	(%RBX,%R8,8),%RBX

  (576) 0x46320e MOV	%RBX,%RDX

  (576) 0x463211 SUB	%RCX,%RDX

  (576) 0x463214 SUB	$0x8,%RDX

  (576) 0x463218 SHR	$0x3,%RDX

  (576) 0x46321c INC	%RDX

  (576) 0x46321f AND	$0x3,%EDX

  (576) 0x463222 JE	46328f

  (576) 0x463224 CMP	$0x1,%RDX

  (576) 0x463228 JE	46326c

  (576) 0x46322a CMP	$0x2,%RDX

  (576) 0x46322e JE	46324e

  (576) 0x463230 MOV	(%RCX),%R11

  (576) 0x463233 LEA	(%R15,%R11,8),%R8

  (576) 0x463237 CMP	%RAX,(%R8)

  (576) 0x46323a JE	46324a

  (576) 0x46323c MOV	(%R9,%R14,1),%RDX

  (576) 0x463240 MOV	%R11,(%RDX,%RDI,8)

  (576) 0x463244 MOV	%RAX,(%R8)

  (576) 0x463247 INC	%RDI

  (576) 0x46324a ADD	$0x8,%RCX

  (576) 0x46324e MOV	(%RCX),%R11

  (576) 0x463251 LEA	(%R15,%R11,8),%R8

  (576) 0x463255 CMP	%RAX,(%R8)

  (576) 0x463258 JE	463268

  (576) 0x46325a MOV	(%R9,%R14,1),%RDX

  (576) 0x46325e MOV	%R11,(%RDX,%RDI,8)

  (576) 0x463262 MOV	%RAX,(%R8)

  (576) 0x463265 INC	%RDI

  (576) 0x463268 ADD	$0x8,%RCX

  (576) 0x46326c MOV	(%RCX),%R11

  (576) 0x46326f LEA	(%R15,%R11,8),%R8

  (576) 0x463273 CMP	%RAX,(%R8)

  (576) 0x463276 JE	463286

  (576) 0x463278 MOV	(%R9,%R14,1),%RDX

  (576) 0x46327c MOV	%R11,(%RDX,%RDI,8)

  (576) 0x463280 MOV	%RAX,(%R8)

  (576) 0x463283 INC	%RDI

  (576) 0x463286 ADD	$0x8,%RCX

  (576) 0x46328a CMP	%RBX,%RCX

  (576) 0x46328d JE	463307

    (577) 0x46328f MOV	(%RCX),%R8

    (577) 0x463292 LEA	(%R15,%R8,8),%RDX

    (577) 0x463296 CMP	%RAX,(%RDX)

    (577) 0x463299 JE	4632a9

    (577) 0x46329b MOV	(%R9,%R14,1),%R11

    (577) 0x46329f MOV	%R8,(%R11,%RDI,8)

    (577) 0x4632a3 MOV	%RAX,(%RDX)

    (577) 0x4632a6 INC	%RDI

    (577) 0x4632a9 MOV	0x8(%RCX),%R8

    (577) 0x4632ad LEA	0x8(%RCX),%RDX

    (577) 0x4632b1 LEA	(%R15,%R8,8),%RCX

    (577) 0x4632b5 CMP	%RAX,(%RCX)

    (577) 0x4632b8 JE	4632c8

    (577) 0x4632ba MOV	(%R9,%R14,1),%R11

    (577) 0x4632be MOV	%R8,(%R11,%RDI,8)

    (577) 0x4632c2 MOV	%RAX,(%RCX)

    (577) 0x4632c5 INC	%RDI

    (577) 0x4632c8 MOV	0x8(%RDX),%R8

    (577) 0x4632cc LEA	(%R15,%R8,8),%RCX

    (577) 0x4632d0 CMP	%RAX,(%RCX)

    (577) 0x4632d3 JE	4632e3

    (577) 0x4632d5 MOV	(%R9,%R14,1),%R11

    (577) 0x4632d9 MOV	%R8,(%R11,%RDI,8)

    (577) 0x4632dd MOV	%RAX,(%RCX)

    (577) 0x4632e0 INC	%RDI

    (577) 0x4632e3 MOV	0x10(%RDX),%R8

    (577) 0x4632e7 LEA	(%R15,%R8,8),%RCX

    (577) 0x4632eb CMP	%RAX,(%RCX)

    (577) 0x4632ee JE	4632fe

    (577) 0x4632f0 MOV	(%R9,%R14,1),%R11

    (577) 0x4632f4 MOV	%R8,(%R11,%RDI,8)

    (577) 0x4632f8 MOV	%RAX,(%RCX)

    (577) 0x4632fb INC	%RDI

    (577) 0x4632fe LEA	0x18(%RDX),%RCX

    (577) 0x463302 CMP	%RBX,%RCX

    (577) 0x463305 JNE	46328f

  (576) 0x463307 INCQ	-0x38(%RBP)

  (576) 0x46330b MOV	-0x90(%RBP),%RBX

  (576) 0x463312 MOV	(%RBX),%R8

  (576) 0x463315 MOV	-0x38(%RBP),%RDX

  (576) 0x463319 CMP	%R8,%RDX

  (576) 0x46331c JL	463051

0x463322 NOPW	(%RAX,%RAX,1)

0x463328 MOV	%RDI,-0x88(%RBP)

0x46332f MOV	-0xe0(%RBP),%R11

0x463336 MOV	-0xc0(%RBP),%RDI

0x46333d MOV	%R13,%RBX

0x463340 MOV	-0xc8(%RBP),%RCX

0x463347 MOV	(%RCX,%RDI,8),%RAX

0x46334b ADD	%R11,%RCX

0x46334e MOV	%RCX,-0xc0(%RBP)

0x463355 MOV	(%RCX),%RCX

0x463358 NOT	%RDI

0x46335b CMP	%RAX,%RCX

0x46335e JLE	463612

0x463364 MOV	%R9,-0x68(%RBP)

0x463368 MOV	%R10,-0x90(%RBP)

0x46336f MOV	-0x88(%RBP),%R8

0x463376 MOV	-0xd8(%RBP),%R13

0x46337d JMP	46338c

  (574) 0x463380 INC	%RAX

  (574) 0x463383 CMP	%RCX,%RAX

  (574) 0x463386 JGE	463600

  (574) 0x46338c MOV	-0x50(%RBP),%R9

  (574) 0x463390 MOV	(%R9,%RAX,8),%RDX

  (574) 0x463394 LEA	(,%RDX,8),%R11

  (574) 0x46339c CMP	%RBX,(%R13,%RDX,8)

  (574) 0x4633a1 JNE	463380

  (574) 0x4633a3 MOV	-0xa0(%RBP),%R10

  (574) 0x4633aa MOV	-0x98(%RBP),%R9

  (574) 0x4633b1 MOV	(%R10,%RDX,8),%RDX

  (574) 0x4633b5 MOV	0x8(%R9,%R11,1),%R11

  (574) 0x4633ba ADD	%RDX,%R11

  (574) 0x4633bd CMP	%R11,%RDX

  (574) 0x4633c0 JGE	463380

  (574) 0x4633c2 MOV	-0xa8(%RBP),%RCX

  (574) 0x4633c9 MOV	(%RCX,%R14,1),%R10

  (574) 0x4633cd LEA	(%R10,%R11,8),%R9

  (574) 0x4633d1 LEA	(%R10,%RDX,8),%RDX

  (574) 0x4633d5 MOV	%R9,-0x38(%RBP)

  (574) 0x4633d9 SUB	%RDX,%R9

  (574) 0x4633dc SUB	$0x8,%R9

  (574) 0x4633e0 SHR	$0x3,%R9

  (574) 0x4633e4 INC	%R9

  (574) 0x4633e7 AND	$0x3,%R9D

  (574) 0x4633eb JE	463488

  (574) 0x4633f1 CMP	$0x1,%R9

  (574) 0x4633f5 JE	463453

  (574) 0x4633f7 CMP	$0x2,%R9

  (574) 0x4633fb JE	463428

  (574) 0x4633fd MOV	(%RDX),%RCX

  (574) 0x463400 TEST	%RCX,%RCX

  (574) 0x463403 JS	463720

  (574) 0x463409 LEA	(%R15,%RCX,8),%R11

  (574) 0x46340d CMP	%RDI,(%R11)

  (574) 0x463410 JE	463424

  (574) 0x463412 MOV	-0x68(%RBP),%R10

  (574) 0x463416 MOV	(%R10,%R14,1),%R9

  (574) 0x46341a MOV	%RCX,(%R9,%R8,8)

  (574) 0x46341e MOV	%RDI,(%R11)

  (574) 0x463421 INC	%R8

  (574) 0x463424 ADD	$0x8,%RDX

  (574) 0x463428 MOV	(%RDX),%RCX

  (574) 0x46342b TEST	%RCX,%RCX

  (574) 0x46342e JS	4636e0

  (574) 0x463434 LEA	(%R15,%RCX,8),%R10

  (574) 0x463438 CMP	%RDI,(%R10)

  (574) 0x46343b JE	46344f

  (574) 0x46343d MOV	-0x68(%RBP),%R9

  (574) 0x463441 MOV	(%R9,%R14,1),%R11

  (574) 0x463445 MOV	%RCX,(%R11,%R8,8)

  (574) 0x463449 MOV	%RDI,(%R10)

  (574) 0x46344c INC	%R8

  (574) 0x46344f ADD	$0x8,%RDX

  (574) 0x463453 MOV	(%RDX),%RCX

  (574) 0x463456 TEST	%RCX,%RCX

  (574) 0x463459 JS	4636b0

  (574) 0x46345f LEA	(%R15,%RCX,8),%R11

  (574) 0x463463 CMP	%RDI,(%R11)

  (574) 0x463466 JE	46347a

  (574) 0x463468 MOV	-0x68(%RBP),%R9

  (574) 0x46346c MOV	(%R9,%R14,1),%R10

  (574) 0x463470 MOV	%RCX,(%R10,%R8,8)

  (574) 0x463474 MOV	%RDI,(%R11)

  (574) 0x463477 INC	%R8

  (574) 0x46347a ADD	$0x8,%RDX

  (574) 0x46347e CMP	%RDX,-0x38(%RBP)

  (574) 0x463482 JE	4635e7

  (574) 0x463488 MOV	%RAX,-0x88(%RBP)

  (574) 0x46348f MOV	-0x68(%RBP),%R9

  (574) 0x463493 MOV	-0x90(%RBP),%R10

  (574) 0x46349a JMP	46350d

    (575) 0x4634a0 LEA	(%R15,%RDX,8),%R11

    (575) 0x4634a4 CMP	%RDI,(%R11)

    (575) 0x4634a7 JE	4634b7

    (575) 0x4634a9 MOV	(%R9,%R14,1),%RAX

    (575) 0x4634ad MOV	%RDX,(%RAX,%R8,8)

    (575) 0x4634b1 MOV	%RDI,(%R11)

    (575) 0x4634b4 INC	%R8

    (575) 0x4634b7 MOV	0x8(%RCX),%RDX

    (575) 0x4634bb TEST	%RDX,%RDX

    (575) 0x4634be JS	463572

    (575) 0x4634c4 LEA	(%R15,%RDX,8),%R11

    (575) 0x4634c8 CMP	%RDI,(%R11)

    (575) 0x4634cb JE	4634db

    (575) 0x4634cd MOV	(%R9,%R14,1),%RAX

    (575) 0x4634d1 MOV	%RDX,(%RAX,%R8,8)

    (575) 0x4634d5 MOV	%RDI,(%R11)

    (575) 0x4634d8 INC	%R8

    (575) 0x4634db MOV	0x10(%RCX),%RDX

    (575) 0x4634df TEST	%RDX,%RDX

    (575) 0x4634e2 JS	4635a3

    (575) 0x4634e8 LEA	(%R15,%RDX,8),%R11

    (575) 0x4634ec CMP	%RDI,(%R11)

    (575) 0x4634ef JE	4634ff

    (575) 0x4634f1 MOV	(%R9,%R14,1),%RAX

    (575) 0x4634f5 MOV	%RDX,(%RAX,%R8,8)

    (575) 0x4634f9 MOV	%RDI,(%R11)

    (575) 0x4634fc INC	%R8

    (575) 0x4634ff LEA	0x18(%RCX),%RDX

    (575) 0x463503 CMP	%RDX,-0x38(%RBP)

    (575) 0x463507 JE	4635d5

    (575) 0x46350d MOV	(%RDX),%RCX

    (575) 0x463510 TEST	%RCX,%RCX

    (575) 0x463513 JS	463680

    (575) 0x463519 LEA	(%R15,%RCX,8),%R11

    (575) 0x46351d CMP	%RDI,(%R11)

    (575) 0x463520 JE	463530

    (575) 0x463522 MOV	(%R9,%R14,1),%RAX

    (575) 0x463526 MOV	%RCX,(%RAX,%R8,8)

    (575) 0x46352a MOV	%RDI,(%R11)

    (575) 0x46352d INC	%R8

    (575) 0x463530 LEA	0x8(%RDX),%RCX

    (575) 0x463534 MOV	0x8(%RDX),%RDX

    (575) 0x463538 TEST	%RDX,%RDX

    (575) 0x46353b JNS	4634a0

    (575) 0x463541 MOV	%RDX,%R11

    (575) 0x463544 NOT	%R11

    (575) 0x463547 LEA	(%R12,%R11,8),%R11

    (575) 0x46354b CMP	%RDI,(%R11)

    (575) 0x46354e JE	4634b7

    (575) 0x463554 MOV	(%R10,%R14,1),%RAX

    (575) 0x463558 NOT	%RDX

    (575) 0x46355b MOV	%RDX,(%RAX,%RSI,8)

    (575) 0x46355f MOV	%RDI,(%R11)

    (575) 0x463562 INC	%RSI

    (575) 0x463565 MOV	0x8(%RCX),%RDX

    (575) 0x463569 TEST	%RDX,%RDX

    (575) 0x46356c JNS	4634c4

    (575) 0x463572 MOV	%RDX,%R11

    (575) 0x463575 NOT	%R11

    (575) 0x463578 LEA	(%R12,%R11,8),%R11

    (575) 0x46357c CMP	%RDI,(%R11)

    (575) 0x46357f JE	4634db

    (575) 0x463585 MOV	(%R10,%R14,1),%RAX

    (575) 0x463589 NOT	%RDX

    (575) 0x46358c MOV	%RDX,(%RAX,%RSI,8)

    (575) 0x463590 MOV	%RDI,(%R11)

    (575) 0x463593 INC	%RSI

    (575) 0x463596 MOV	0x10(%RCX),%RDX

    (575) 0x46359a TEST	%RDX,%RDX

    (575) 0x46359d JNS	4634e8

    (575) 0x4635a3 MOV	%RDX,%R11

    (575) 0x4635a6 NOT	%R11

    (575) 0x4635a9 LEA	(%R12,%R11,8),%R11

    (575) 0x4635ad CMP	%RDI,(%R11)

    (575) 0x4635b0 JE	4634ff

    (575) 0x4635b6 MOV	(%R10,%R14,1),%RAX

    (575) 0x4635ba NOT	%RDX

    (575) 0x4635bd MOV	%RDX,(%RAX,%RSI,8)

    (575) 0x4635c1 LEA	0x18(%RCX),%RDX

    (575) 0x4635c5 MOV	%RDI,(%R11)

    (575) 0x4635c8 INC	%RSI

    (575) 0x4635cb CMP	%RDX,-0x38(%RBP)

    (575) 0x4635cf JNE	46350d

  (574) 0x4635d5 MOV	%R9,-0x68(%RBP)

  (574) 0x4635d9 MOV	%R10,-0x90(%RBP)

  (574) 0x4635e0 MOV	-0x88(%RBP),%RAX

  (574) 0x4635e7 MOV	-0xc0(%RBP),%R9

  (574) 0x4635ee INC	%RAX

  (574) 0x4635f1 MOV	(%R9),%RCX

  (574) 0x4635f4 CMP	%RCX,%RAX

  (574) 0x4635f7 JL	46338c

0x4635fd NOPL	(%RAX)

0x463600 MOV	%R8,-0x88(%RBP)

0x463607 MOV	-0x68(%RBP),%R9

0x46360b MOV	-0x90(%RBP),%R10

0x463612 INCQ	-0x70(%RBP)

0x463616 MOV	-0x70(%RBP),%RDI

0x46361a CMP	%RDI,-0xb8(%RBP)

0x463621 JG	462fc0

    (575) 0x463680 MOV	%RCX,%R11

    (575) 0x463683 NOT	%R11

    (575) 0x463686 LEA	(%R12,%R11,8),%R11

    (575) 0x46368a CMP	%RDI,(%R11)

    (575) 0x46368d JE	463530

    (575) 0x463693 MOV	(%R10,%R14,1),%RAX

    (575) 0x463697 NOT	%RCX

    (575) 0x46369a MOV	%RCX,(%RAX,%RSI,8)

    (575) 0x46369e MOV	%RDI,(%R11)

    (575) 0x4636a1 INC	%RSI

    (575) 0x4636a4 JMP	463530

  (574) 0x4636b0 MOV	%RCX,%R11

  (574) 0x4636b3 NOT	%R11

  (574) 0x4636b6 LEA	(%R12,%R11,8),%R10

  (574) 0x4636ba CMP	%RDI,(%R10)

  (574) 0x4636bd JE	46347a

  (574) 0x4636c3 MOV	-0x90(%RBP),%R9

  (574) 0x4636ca NOT	%RCX

  (574) 0x4636cd MOV	(%R9,%R14,1),%R11

  (574) 0x4636d1 MOV	%RCX,(%R11,%RSI,8)

  (574) 0x4636d5 MOV	%RDI,(%R10)

  (574) 0x4636d8 INC	%RSI

  (574) 0x4636db JMP	46347a

  (574) 0x4636e0 MOV	%RCX,%R10

  (574) 0x4636e3 NOT	%R10

  (574) 0x4636e6 LEA	(%R12,%R10,8),%R11

  (574) 0x4636ea CMP	%RDI,(%R11)

  (574) 0x4636ed JE	46344f

  (574) 0x4636f3 MOV	-0x90(%RBP),%R9

  (574) 0x4636fa NOT	%RCX

  (574) 0x4636fd MOV	(%R9,%R14,1),%R10

  (574) 0x463701 MOV	%RCX,(%R10,%RSI,8)

  (574) 0x463705 MOV	%RDI,(%R11)

  (574) 0x463708 INC	%RSI

  (574) 0x46370b JMP	46344f

  (576) 0x463710 MOV	-0x90(%RBP),%R11

  (576) 0x463717 MOV	(%R11),%R8

  (576) 0x46371a JMP	463040

  (574) 0x463720 MOV	%RCX,%R11

  (574) 0x463723 NOT	%R11

  (574) 0x463726 LEA	(%R12,%R11,8),%R10

  (574) 0x46372a CMP	%RDI,(%R10)

  (574) 0x46372d JE	463424

  (574) 0x463733 MOV	-0x90(%RBP),%R9

  (574) 0x46373a NOT	%RCX

  (574) 0x46373d MOV	(%R9,%R14,1),%R11

  (574) 0x463741 MOV	%RCX,(%R11,%RSI,8)

  (574) 0x463745 MOV	%RDI,(%R10)

  (574) 0x463748 INC	%RSI

  (574) 0x46374b JMP	463424

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1072 - 1125

--------------------------------------------------------------------------------

1072:           for (i=thread_start; i < thread_stop; i++)

1073:           {

1074:              i1 = pass_array[i];

1075:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1076:              {

1077:                 j1 = S_diag_j[j];

1078:                 if (assigned[j1] == pass-1)

1079:                 {

1080:                    j_start = P_diag_start[j1];

1081:                    j_end = j_start+P_diag_i[j1+1];

1082:                    for (k=j_start; k < j_end; k++)

1083:                    {

1084:                       k1 = P_diag_pass[pass-1][k];

1085:                       if (P_marker[k1] != -i1-1)

1086:                       {

1087:                           P_diag_pass[pass][cnt_nz++] = k1;

1088:                           P_marker[k1] = -i1-1;

1089:                       }

1090:                    }

1091:                    j_start = P_offd_start[j1];

1092:                    j_end = j_start+P_offd_i[j1+1];

1093:                    for (k=j_start; k < j_end; k++)

1094:                    {

1095:                       k1 = P_offd_pass[pass-1][k];

1096:                       if (P_marker_offd[k1] != -i1-1)

1097:                       {

1098:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1099:                          P_marker_offd[k1] = -i1-1;

1100:                       }

1101:                    }

1102:                 }

1103:              }

1104:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1105:              {

1106:                 j1 = S_offd_j[j];

1107:                 if (assigned_offd[j1] == pass-1)

1108:                 {

1109:                    j_start = Pext_start[j1];

1110:                    j_end = j_start+Pext_i[j1+1];

1111:                    for (k=j_start; k < j_end; k++)

1112:                    {

1113:                       k1 = Pext_pass[pass][k];

1114:                       if (k1 < 0)

1115:                       {

1116:                          if (P_marker[-k1-1] != -i1-1)

1117:                          {

1118:                             P_diag_pass[pass][cnt_nz++] = -k1-1;

1119:                             P_marker[-k1-1] = -i1-1;

1120:                          }

1121:                       }

1122:                       else if (P_marker_offd[k1] != -i1-1)

1123:                       {

1124:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1125:                          P_marker_offd[k1] = -i1-1;

Coverage (%)	Name	Source Location	Module
○96.92	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○3.08	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1104-1104,par_multi_interp.c:1122-1122
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.67
CQA cycles if no scalar integer	7.67
CQA cycles if FP arith vectorized	7.67
CQA cycles if fully vectorized	0.96
Front-end cycles	7.67
P0 cycles	2.10
P1 cycles	2.00
P2 cycles	6.33
P3 cycles	6.33
P4 cycles	5.00
P5 cycles	2.00
P6 cycles	1.90
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	2.00
P11 cycles	6.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	46.00
Nb loads	19.00
Nb stores	10.00
Nb stack references	12.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.26
Bytes prefetched	0.00
Bytes loaded	152.00
Bytes stored	80.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1104-1104,par_multi_interp.c:1122-1122
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.67
CQA cycles if no scalar integer	7.67
CQA cycles if FP arith vectorized	7.67
CQA cycles if fully vectorized	0.96
Front-end cycles	7.67
P0 cycles	2.10
P1 cycles	2.00
P2 cycles	6.33
P3 cycles	6.33
P4 cycles	5.00
P5 cycles	2.00
P6 cycles	1.90
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	2.00
P11 cycles	6.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	46.00
Nb loads	19.00
Nb stores	10.00
Nb stack references	12.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.26
Bytes prefetched	0.00
Bytes loaded	152.00
Bytes stored	80.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1072-1125
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1125.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1075,1104,1122.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 7.67 to 0.96 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

INC: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 152 bytes. The binary loop is storing 80 bytes.

General properties

nb instructions	45
nb uops	46
loop length	228
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	12

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.67 cycles
front end	7.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.10	2.00	6.33	6.33	5.00	2.00	1.90	5.00	5.00	5.00	2.00	6.33
cycles	2.10	2.00	6.33	6.33	5.00	2.00	1.90	5.00	5.00	5.00	2.00	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.67
Dispatch	6.33
Overall L1	7.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.67 cycles. At this rate:

10% of peak load performance is reached (19.83 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (10.43 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 7.67 to 6.33 cycles (1.21x speedup).

ASM code

In the binary file, the address of the loop is: 462fc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0xb0(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xd0(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R13,%RDI,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x8(,%RDI,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R8,%RDI,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R11,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R8,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%R8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
NOT %RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 463340 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1170>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x88(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RBX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 463051 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xe81>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xe0(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xc0(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R13,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0xc8(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RDI,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R11,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RCX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOT %RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 463612 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1442>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x88(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xd8(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 46338c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x11bc>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x68(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x90(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INCQ -0x70(%RBP)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV -0x70(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDI,-0xb8(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JG 462fc0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdf0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1072-1125
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 7.67 to 0.96 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

INC: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 152 bytes. The binary loop is storing 80 bytes.

General properties

nb instructions	45
nb uops	46
loop length	228
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	12

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.67 cycles
front end	7.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.10	2.00	6.33	6.33	5.00	2.00	1.90	5.00	5.00	5.00	2.00	6.33
cycles	2.10	2.00	6.33	6.33	5.00	2.00	1.90	5.00	5.00	5.00	2.00	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.67
Dispatch	6.33
Overall L1	7.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.67 cycles. At this rate:

10% of peak load performance is reached (19.83 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (10.43 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 462fc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0xb0(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xd0(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R13,%RDI,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x8(,%RDI,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R8,%RDI,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R11,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R8,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%R8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
NOT %RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 463340 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1170>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x88(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RBX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 463051 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xe81>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xe0(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xc0(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R13,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0xc8(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RDI,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R11,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RCX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOT %RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 463612 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1442>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x88(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xd8(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 46338c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x11bc>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x68(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x90(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INCQ -0x70(%RBP)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV -0x70(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDI,-0xb8(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JG 462fc0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdf0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code