OV - exec - Loop 3009

0x550900 LEA	-0x1(%RAX),%RDX

0x550904 CMP	%R8,%RDX

0x550907 JL	55092e

0x550909 LEA	(%R8,%RDX,1),%RCX

0x55090d MOV	%RCX,%RAX

0x550910 SHR	$0x3f,%RAX

0x550914 ADD	%RCX,%RAX

0x550917 SAR	$0x1,%RAX

0x55091a MOV	%RAX,%R9

0x55091d CMP	%RSI,(%RDI,%RAX,8)    [1]

0x550921 JG	550900

0x550923 JGE	550935

0x550925 LEA	0x1(%RAX),%R8

0x550929 CMP	%R8,%RDX

0x55092c JGE	550909

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/utilities/binsearch.c: 35 - 44

--------------------------------------------------------------------------------

35:    while (not_found && low <= high)

36:    {

37:       m = (low + high) / 2;

38:       if (value < list[m])

39:       {

40:          high = m - 1;

41:       }

42:       else if (value > list[m])

43:       {

44:         low = m + 1;

Coverage (%)	Name	Source Location	Module
○93.91	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►3.85+	hypre_BoomerAMGSetup	par_amg_setup.c:1227	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
►1.83+	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17 - 2.67
Bottlenecks
Function	hypre_BinarySearch
Source	binsearch.c:35-44
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.25 - 6.00
CQA cycles if no scalar integer	2.25 - 6.00
CQA cycles if FP arith vectorized	2.25 - 6.00
CQA cycles if fully vectorized	0.28 - 0.75
Front-end cycles	1.92
P0 cycles	2.25
P1 cycles	0.80
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.00
P5 cycles	0.60
P6 cycles	2.25
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.60
P11 cycles	0.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2 - 6
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.50
Nb uops	10.50
Nb loads	1.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.33 - 3.60
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25 - 2.40
Bottlenecks
Function	hypre_BinarySearch
Source	binsearch.c:35-44
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50 - 6.00
CQA cycles if no scalar integer	2.50 - 6.00
CQA cycles if FP arith vectorized	2.50 - 6.00
CQA cycles if fully vectorized	0.31 - 0.75
Front-end cycles	2.00
P0 cycles	2.50
P1 cycles	0.80
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.00
P5 cycles	0.60
P6 cycles	2.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.60
P11 cycles	0.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2 - 6
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	12.00
Nb uops	11.00
Nb loads	1.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.33 - 3.20
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09 - 3.00
Bottlenecks
Function	hypre_BinarySearch
Source	binsearch.c:35-44
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00 - 6.00
CQA cycles if no scalar integer	2.00 - 6.00
CQA cycles if FP arith vectorized	2.00 - 6.00
CQA cycles if fully vectorized	0.25 - 0.75
Front-end cycles	1.83
P0 cycles	2.00
P1 cycles	0.80
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.00
P5 cycles	0.60
P6 cycles	2.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.60
P11 cycles	0.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2 - 6
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	10.00
Nb loads	1.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.33 - 4.00
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BinarySearch
Source file and lines	binsearch.c:35-44
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/utilities/binsearch.c:35-44.

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.00 to 0.75 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes.

General properties

nb instructions	11.50
nb uops	10.50
loop length	36
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	1.92 cycles
front end	1.92 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.25	0.80	0.33	0.33	0.00	0.60	2.25	0.00	0.00	0.00	0.60	0.33
cycles	2.25	0.80	0.33	0.33	0.00	0.60	2.25	0.00	0.00	0.00	0.60	0.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00-6.00

Cycles summary

Front-end	1.92
Dispatch	2.25
Data deps.	2.00-6.00
Overall L1	2.25-6.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

0% of peak load performance is reached (1.33 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	hypre_BinarySearch
Source file and lines	binsearch.c:35-44
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/utilities/binsearch.c:35-44.

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.00 to 0.75 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes.

General properties

nb instructions	12
nb uops	11
loop length	37
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.00 cycles
front end	2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.50	0.80	0.33	0.33	0.00	0.60	2.50	0.00	0.00	0.00	0.60	0.33
cycles	2.50	0.80	0.33	0.33	0.00	0.60	2.50	0.00	0.00	0.00	0.60	0.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00-6.00

Cycles summary

Front-end	2.00
Dispatch	2.50
Data deps.	2.00-6.00
Overall L1	2.50-6.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

0% of peak load performance is reached (1.33 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 550909

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
LEA (%R8,%RDX,1),%RCX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3f,%RAX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
ADD %RCX,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
SAR $0x1,%RAX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RSI,(%RDI,%RAX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JG 550900 <hypre_BinarySearch+0x40>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
JGE 550935 <hypre_BinarySearch+0x75>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
LEA 0x1(%RAX),%R8	1	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R8,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JGE 550909 <hypre_BinarySearch+0x49>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	hypre_BinarySearch
Source file and lines	binsearch.c:35-44
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/utilities/binsearch.c:35-44.

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.00 to 0.75 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes.

General properties

nb instructions	11
nb uops	10
loop length	35
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.83 cycles
front end	1.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	0.80	0.33	0.33	0.00	0.60	2.00	0.00	0.00	0.00	0.60	0.33
cycles	2.00	0.80	0.33	0.33	0.00	0.60	2.00	0.00	0.00	0.00	0.60	0.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00-6.00

Cycles summary

Front-end	1.83
Dispatch	2.00
Data deps.	2.00-6.00
Overall L1	2.00-6.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

0% of peak load performance is reached (1.33 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 550909

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
LEA -0x1(%RAX),%RDX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R8,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JL 55092e <hypre_BinarySearch+0x6e>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
LEA (%R8,%RDX,1),%RCX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3f,%RAX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
ADD %RCX,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
SAR $0x1,%RAX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RSI,(%RDI,%RAX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	N/A
JG 550900 <hypre_BinarySearch+0x40>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code