OV - exec - Loop 2974

0x549b34 VMOVSD	%XMM0,(%R8)    [1]

0x549b39 VMOVSD	%XMM0,0x8(%R8)    [1]

0x549b3f VMOVSD	%XMM0,0x10(%R8)    [1]

0x549b45 VMOVSD	%XMM0,0x18(%R8)    [1]

0x549b4b VMOVSD	%XMM0,0x20(%R8)    [1]

0x549b51 VMOVSD	%XMM0,0x28(%R8)    [1]

0x549b57 VMOVSD	%XMM0,0x30(%R8)    [1]

0x549b5d VMOVSD	%XMM0,0x38(%R8)    [1]

0x549b63 ADD	$0x40,%R8

0x549b67 CMP	%R8,%R9

0x549b6a JNE	549b34

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/vector.c: 271 - 271

--------------------------------------------------------------------------------

271:       vector_data[i] = value;

Coverage (%)	Name	Source Location	Module
○97.70	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.30	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.40
Bottlenecks	P4, P7, P8, P9,
Function	hypre_SeqVectorSetConstantValues._omp_fn.0
Source	vector.c:271-271
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	0.50
Front-end cycles	1.67
P0 cycles	0.50
P1 cycles	0.00
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	4.00
P5 cycles	0.00
P6 cycles	0.50
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.00
P11 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	10.00
Nb loads	0.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.40
Bottlenecks	P4, P7, P8, P9,
Function	hypre_SeqVectorSetConstantValues._omp_fn.0
Source	vector.c:271-271
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	0.50
Front-end cycles	1.67
P0 cycles	0.50
P1 cycles	0.00
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	4.00
P5 cycles	0.00
P6 cycles	0.50
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.00
P11 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	10.00
Nb loads	0.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_SeqVectorSetConstantValues._omp_fn.0
Source file and lines	vector.c:271-271
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/vector.c:271.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.00 to 0.50 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck).

Workaround

Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 64 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	11
nb uops	10
loop length	56
used x86 registers	2
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.67 cycles
front end	1.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	0.50	0.00	0.00	0.00	4.00	0.00	0.50	4.00	4.00	4.00	0.00	0.00
cycles	0.50	0.00	0.00	0.00	4.00	0.00	0.50	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.67
Dispatch	4.00
Data deps.	1.00
Overall L1	4.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

12% of peak store performance is reached (16.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 549b34

Instruction	Nb FU	P0	P1	P4	P5	P6	P7	P8	P9	P10	Latency	Recip. throughput	Vectorization
VMOVSD %XMM0,(%R8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0x8(%R8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0x10(%R8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0x18(%R8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0x20(%R8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0x28(%R8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0x30(%R8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0x38(%R8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
ADD $0x40,%R8	1	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%R9	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
JNE 549b34 <hypre_SeqVectorSetConstantValues._omp_fn.0+0xd4>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A

Function	hypre_SeqVectorSetConstantValues._omp_fn.0
Source file and lines	vector.c:271-271
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/vector.c:271.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.00 to 0.50 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck).

Workaround

Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 64 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	11
nb uops	10
loop length	56
used x86 registers	2
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.67 cycles
front end	1.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	0.50	0.00	0.00	0.00	4.00	0.00	0.50	4.00	4.00	4.00	0.00	0.00
cycles	0.50	0.00	0.00	0.00	4.00	0.00	0.50	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.67
Dispatch	4.00
Data deps.	1.00
Overall L1	4.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

12% of peak store performance is reached (16.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 549b34

Instruction	Nb FU	P0	P1	P4	P5	P6	P7	P8	P9	P10	Latency	Recip. throughput	Vectorization
VMOVSD %XMM0,(%R8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0x8(%R8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0x10(%R8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0x18(%R8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0x20(%R8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0x28(%R8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0x30(%R8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,0x38(%R8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
ADD $0x40,%R8	1	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%R9	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
JNE 549b34 <hypre_SeqVectorSetConstantValues._omp_fn.0+0xd4>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code